TIM-0 PROTOTYPE MODULE SETTING-UP :
			===================================

				MP-UCL, 07-12-2001



NOTE 1:	Default setup is indicated by '#'
=======

NOTE 2:	IC numbers ( Uxx ) refer to the nearest IC receiving the
=======	signal selected by the link/switch etc.

NOTE 3:	Diagram numbers refer to the circuit schematics page with
=======	the relevant link/switch etc.


1)	Set VME Base Address switches :
	-------------------------------
	( Diag.07 )	SW2 : sets A16 - A19	#  default :	SW2 = 0
			SW3 : sets A20 - A23			SW3 = F
			SW5 : sets A24 - A27			SW5 = D
			SW6 : sets A28 - A31			SW6 = 0

			( this default sets the A24-A28 = 13
			  ie. the ROD Crate TIM Slot Geographical Address
			  GA(4-0)* = 10010 ) 



2)	Set various Delay Switches :
	----------------------------

NOTE 4:	Note that the LEAST SIGNIFICANT DELAY BIT "A0" is the top slide
=======	ie. nearest the TOP edge of the TIM PCB, with the bit "A5" ( MSB )
	being the bottom slide.

	The "ON" position ( ie. signal An = 0 ) is with the relevant slide
	towards the FRONT PANEL of the TIM PCB.

	The "OFF" position ( ie. signal An = 1 ) is with the relevant slide
	towards the BACKPLANE CONNECTORs of the TIM PCB.

	Any other lever markings or numbers on actual switch bodies
	are irrelevant.


	( Diag.08/U8 )	SW1:	ROD Setup delay DL2	     #	all ON (ie.=0)

	( Diag.08/U26 ) SW4:	BCCLK1 Setup delay DL3	     #	all ON ( 0 )

	( Diag.08/U40 )	SW8:	TIM Setup delay DL4	     #	all ON ( 0 )

	( Diag.09/U27 )	SW7:	Trig. Window Delay Setup :   #	000101 ( 5 )

	( Diag.09/U9 )	SW9:	Trig. Window Size Comp.  :   #	000100 ( 4 )

									 /cont:

					- 2 -


3)	2-pin Links :
	-------------

	( Diag.07/U38 )	PL4	in  #	bypasses VME interrupt IACK daisy-chain
				out 	enables VME interrupt IACK daisy-chain

	( Diag.07/U38 )	PL6	in	selects switch-set VME Base Address
					( see par. 1 )
				out #	VME Base address set to
					VME GA(4-0)* = 10010

	( Diag.01/J2 )	PL58	in	connects -5V2 bus to Jaux/9A,B,C
				out #	isolates -5V2 bus from Jaux/9A,B,C
			PL59	out #	-ditto-		       Jaux/10A,B,C
			PL60	out #	-ditto-		       J2/4C
			PL61	out #	-ditto-		       J2/7A
			PL62	out #	-ditto-		       J2/13A
			PL63	out #	-ditto-		       J2/19A
			PL65	out #	-ditto-		       J2/19C

	( Diag.14/U53 )	PL64	in	disables -5V2 DC converter
				out #	enables -5V2 DC converter

	( Diag.14/U53 )	PL66	in  #	connects outputs from -5V2 DC converter
					onto -5V2 bus
				out	isolates outputs from -5V2 bus

			PL67	in  #	- ditto -
			PL68	in  #	- ditto -

			NOTE 5:	All three links PL66,67,68 to be used together
			=======

	( Diag.14/U85 )	PL158	in	enables TIM_BUSY_OUT onto backplane
				out #	disables TIM_BUSY_OUT

	( Diag.14/U85 )	PL161	in	overrides P3 b/plane drivers disable
					by ROD_SENSE
				out #	P3 b/plane drivers only enabled
					by correct ROD_SENSE

	( Diag.02/U84 )	PL169	in  #	sets FER = ECR
				out	sets FER independent from ECR

	( Diag.13/U93 )	PL174	in  #	allows TTCB(n) outputs to be enabled
					by correct NTIMOUTEN
				out	disables TTCB(n) outputs

	( Diag.13/U86 )	SB19	in	connects input clock
					onto the test point PL156/A
				out #   isolates input clock
					from the test point PL156/A

	( Diag.07/U23 )	SB1-SB10	VME Clocking Delay Line DL0 setup

			***THESE LINKS ARE ALREADY PROGRAMMED ON PCB***
			===============================================
									/cont:


					- 3 -


4)	3-pin Links :
	-------------

	( Diag.15/U63 )	LK3   pins 2+3 # NIMBUSYOUT = true
				   1+2	 NIMBUSYOUT = inverted

			LK4   pins 2+3 # NIMTRIGINOUT = true
				   1+2	 NIMTRIGINOUT = inverted

			LK5   pins 2+3 # NIMTRIGOUT = true
				   1+2	 NIMTRIGOUT = inverted

	( Diag.15/U74 )	LK8   pins 2+3 # RODBUSYOUT = true
				   1+2	 RODBUSYOUT = inverted

	( Diag.15/SK15)	LK11  pins 2+3 # RODBUSYOUT = NIM standard
				   1+2	 RODBUSYOUT = TTL standard

	( Diag.16/U90 )	LK13  pins 2+3 # ECLBUSYOUT = BUSYOUTB
				   1+2	 ECLBUSYOUT = MEXTBUSYOUT

	( Diag.14/U85 )	PL155 pins 2+3	 TIMOUTEN, which enables TIM backplane
					 outputs, is always enabled 
				   1+2 # NTIMOUTEN is enabled only in the
					 correct TIM slot
					 ( by VME GA(4-0)* = 10010 )



5)	NOTE 6:	The following links are DIAGNOSTIC TEST POINTS ONLY,
	=======			with EVERY PIN "B" CONNECTED TO GND

		DO NOT PUT ANY LINKS BETWEEN PINS "A" and "B"  !
		================================================

	( Diag.04/U67 )		PL122 - PL153	     PLDs spare bus test points

	( Diag.13/U86 )		PL156, PL159, PL165  Input Clock test points

	( Diag.16/U81+U90 )	PL162 - PL173	     TTC(x) output test points