TIM registers. For Firmware Version 26

Address Map
Offset by Base Address (A31 - A16)
Address	D16 Field
0000 - 003E	Register address space
0040 - 00FE	TIM3 Extra Register address space
0100 - 01FE	TIM3 FPGA1 Register address space
0200 - 7FFE	Reserved address space
8000 - FFFE	First word of Sequencer RAM Last word of Sequencer RAM


Register Address Map
Offset	Read/ Write	No	Name	Init Value	CPLD/FPGA
`0x00`	R/W	0	Signal Enables	`0`	2/2
`0x02`	R/W	1	Command & Mode	`0x100`	2/2
`0x04`	R/W	2	Burst Count	`0`	3/2
`0x06`	R/W	3	Frequency Select	`0`	3/2
`0x08`	R/W	4	Trigger Window	`0`	3/2
`0x0A`	R/W	5	Delay	`0`	2/2
`0x0C`	R	6	Status	`0x8A80`	3/2
`0x0E`	R	7	FIFO Status	`0x4040`	5/2
`0x10`	R(/W)	8	Trigger ID Lo	`0xFFFF`	4a/2
`0x12`	R(/W)	9	Trigger ID Hi	`0x00FF`	4a/2
`0x14`	R(/W)	10	Trigger BCID	`0`	4b/2
`0x16`	R(/W)	11	Trigger Type ID	`0`	4b/2
`0x18`	R/W	12	Run Enables	`0`	6/2
`0x1A`	R/W	13	Sequencer Control	`0`	7/2
`0x1C`	R/W	14	Sequencer End	`0`	7/2
`0x1E`	R/W	15	RODBusy Mask	`0`	8/2
`0x20`	R	16	RODBusy Status	`0`	8/2
`0x22`	R/Z	17	RODBusy Latch	`0`	8/2
`0x24`	R/Z	18	RODBusy Monitor	`0`	8/2
`0x26`	R/Z	19	TTC Data	`0`	9/2
`0x28`	R/W	20	TTC Select	`0`	9/2
`0x2A`	R/Z	21	TTC BCID	`0`	4b/2
`0x2C`	R/W	22	TTCrx Control	`0`	9/2
`0x2E`	R	23	TTC Status	`0`	9/2
`0x30`	R/Z	24	TIM Output Latch	`0`	6/2
`0x32`	R	25	TIM ID	`-`	5/2
`0x34`	-	26	reserved	`-`	-
`0x36`	-	27	reserved	`-`	-
`0x38`	-	28	reserved	`-`	-
`0x3A`	-	29	reserved	`-`	-
`0x3C`	-	30	reserved	`-`	-
`0x3E`	-	31	reserved	`-`	-

TIM-3 Only - Extra Registers Address Map
Offset	Read/ Write	No	Name	Init Value	FPGA
`0x40`	-	32	reserved	`-`	2
`0x42`	R/W	33	Enables3	`0`	2
`0x44`	-	34	reserved	`-`	2
`0x46`	R/W	35	Control	`0`	2
`0x48`	-	36	reserved	`-`	2
`0x4A`	R	37	Status3	`0x0640`	2
`0x4C`	R/Z	38	Status Change Latch	`0`	2
`0x4E`	R/Z	39	Status3 Change Latch	`0`	2
`0x50`	-	40	reserved	`-`	2
`0x52`	R/W	41	QPLL Control	`0x00B0`	2
`0x54`	-	42	reserved	`-`	2
`0x56`	R/W	43	Busy Enable3	`0x1000`	2
`0x58`	-	44	reserved	`-`	2
`0x5A`	R	45	Busy Status3	`0x0404`	2
`0x5C`	-	46	reserved	`-`	2
`0x5E`	R/Z	47	Busy Status3 Change Latch	`0`	2
`0x60`	R/Z	48	Overall Busy Count Lo	`0`	2
`0x62`	R/Z	49	Overall Busy Count Hi	`0`	2
`0x64`	R/Z	50	Overall Busy Count Ex	`0`	2
`0x66`	R/W	51	BCID Offset Extended	`0`	2
`0x68`	-	52	reserved	`40000`	2
`0x6A`	R/W	53	FFTV Match Threshhold	`10`	2
`0x6C`	-	54	reserved	`80`	2
`0x6E`	-	55	reserved	`2666`	2
`0x70`	-	56	reserved	`3076`	2
`0x72`	-	57	reserved	`40`	2
`0x74`	R/Z	58	FFTV Count Lo	`0`	2
`0x76`	R/Z	59	FFTV Count Hi	`0`	2
`0x78`	R/Z	60	FFTV Count Ex	`0`	2
`0x7A`	-	61	reserved	`-`	2
`0x7C`	R/Z	62	FFTV Trigger Count Lo	`0`	2
`0x7E`	R/Z	63	FFTV Trigger Count Hi	`0`	2
`0x80`	R/Z	64	Trigger Period FIFO Lo	`0`	2
`0x82`	R/Z	65	Trigger Period FIFO Hi	`0x4000`	2
`0x84`	R/Z	66	Veto ID Lo	`0`	2
`0x86`	R/Z	67	Veto ID Hi	`0`	2
`0x88`	R/W	68	Trigger Osc2 Period Lo	`0`	2
`0x8A`	R/W	69	Trigger Osc2 Period Hi	`0`	2
`0x8C`	-	70	reserved	`-`	2
`0x8E`	R/W	71	Burst Count Hi	`0`	2
`0x90`	-	72	reserved	`0`	2
`0x92`	-	73	reserved	`0`	2
`0x94`	R	74	F2 Timestamp Lo	`-`	2
`0x96`	R	75	F2 Timestamp Hi	`-`	2
`0x98`	-	76	reserved	`0`	2
`0x9A`	-	77	reserved	`0`	2
`0x9C`	R/W	78	F2 Debug Control	`0`	2
`0x9E`	R	79	F2 Debug Status	`-`	2

Registers

TIM RESET means power-up reset, push-button reset, or vRESET command bit
reserved bits are either Read/Write or = 0 if Read only
undefined bits are not implemented and read as any value

0x00. Signal Enables Register [Jump Back to Index]
Signal Enables - `ENABLES`		Stand-alone External/Internal Signal Enables - R/W

Bits	Field	Function
0 0x0001	-	reserved=0
1 0x0002	EnIntTRIG	Enable internal repetitive trigger. DEPRICATED (see Enables3 Reg)
2 0x0004	EnIntECR	Enable internal repetitive ECReset
3 0x0008	EnIntBCR	Enable internal repetitive BCReset
4 0x0010	EnRandom	Enable internal trigger randomizer
5 0x0020	EnIntFER	Enable internal repetitive FEReset
6 0x0040	EnWindow	Enable trigger window
7 0x0080	EnIntBusy	Enable internal Busy (see Busy_En3 Reg)
8 0x0100	EnExtClk	Enable external clock inputs
9 0x0200	EnExtTRIG	Enable external trigger inputs
10 0x0400	EnExtECR	Enable external ECReset inputs
11 0x0800	EnExtBCR	Enable external BCReset inputs
12 0x1000	EnExtCAL	Enable external Calibrate inputs
13 0x2000	EnExtFER	Enable external FEReset inputs
14 0x4000	EnExtSEQ	Enable external Sequencer Go inputs
15 0x8000	EnExtBusy	Enable external Busy inputs (see Busy_En3 Reg)
Register resets to 0. Note: external means ECL or NIM front-panel inputs. EnExtCLK disables the internal clock. Note: IntECR is only available if the internal ECR = FER link is inserted (this is the default hardware setup).

0x02. Command & Mode Register [Jump Back to Index]
Command & Mode - `COMMAND`			Commands and Mode Settings - R/W

Bits	Mode	Field	Function
0 0x0001	-	-	reserved=0
1 0x0002	edge	vTRIG	Single trigger
2 0x0004	edge	vECR	Single ECReset
3 0x0008	edge	vBCR	Single BCReset
4 0x0010	edge	vCAL	Single Calibrate strobe
5 0x0020	edge	vFER	Single FEReset
6 0x0040	edge	vSpare	Single Spare command
7 0x0080	level	vBusy	Set Busy (see Busy_Stat3 Reg)
8 0x0100	level	vRodBusy	Set RodBusy (see Busy_Stat3 Reg)
9 0x0200	level	vBurstMode	Set BURST mode - disable triggers
10 0x0400	edge	vBurstGo	Start BURST triggers - Int or Ext
11 0x0800	-	-	reserved=0
12 0x1000	level	EnRunMode	Enable Run Mode
13 0x2000	level	EnTestBusy	Enable Busy set by next trigger (TestBusy)
14 0x4000	level	ClrTestBusy	Clear TestBusy
15 0x8000	edge	vReset	Overall TIM RESET
Register resets to 0x100. Note: a command bit has one of two modes of operation: 1. level : command is asserted while the bit is set (to 1) 2. edge : command is generated by setting the bit (from 0 to 1, ie the bit must be cleared to re-enable operation)

0x04. Burst Count Register [Jump Back to Index]
Burst Count - `BURST`		Burst Count - R/W

Bits	Field	Function
0-15	BurstCount	Number of triggers in BURST
Register resets to 0. Higher order bits (31:16) are in Burst_Hi Reg

0x06. Frequency Select Register [Jump Back to Index]
Frequency Select - `FREQUENCY`		Trigger/ECR Oscillator Frequency Select - R/W

Bits	Field	Function
0- 4	IntTRIGfreq	Internal trigger look-up table
5- 7	-	reserved=0
8-12	IntFERfreq	Internal ECR/FER look-up table
13-15	-	reserved=0
Register resets to 0. Higher order bits (31:16) are in Burst_Hi Reg

IntTRIGfreq lookup table
Bits (7:0) Hex		Multiplier
Bits (7:0) Hex		x1	x10	x100	x1000
Freq (Hz)	600	11	09	01	00
	300	1A	12	0A	02
	200	1B	13	0B	03
	150	1C	14	0C	04
	120	1D	15	0D	05
	100	1E	16	0E	06
	60	19	11	09	01
	50	1F	17	0F	07

IntFERfreq lookup table
Bits (15:8) Hex		Multiplier
Bits (15:8) Hex		x1	x10	x100	x1000
Freq (Hz)	0.060	11	09	01	00
	0.030	1A	12	0A	02
	0.020	1B	13	0B	03
	0.015	1C	14	0C	04
	0.012	1D	15	0D	05
	0.010	1E	16	0E	06
	0.006	19	11	09	01
	0.005	1F	17	0F	07

Notes:
1. Example: Write 0E06 hex for triggers at 100 kHz and front-end resets at 1 Hz.
2. If the EnRandom bit is set, the average frequency of the random triggers is one quarter of the above internal trigger frequency table.

0x08. Trigger Window Register [Jump Back to Index]
Trigger Window - `WINDOW`		Trigger Window Control - R/W

Bits	Field	Function
0- 5	WinSize	Trigger window size (0.5ns steps)
6- 7	-	reserved=0
8-13	WinDelay	Trigger window delay (0.5ns steps)
14-15	-	reserved=0
Register resets to 0. Note: the Trigger Window register is for External Trigger input only.

0x0A. Delay Register [Jump Back to Index]
Delay - `DELAYS`		Stand-alone Mode Delays - R/W

Bits	Field	Function
0- 7	TrigDelay	L1A/Trigger/ECR/BCR pipeline delay (clock steps)
8-13	ClkDelay	Stand-alone clock delay (0.5ns steps)
14-15	-	reserved=0
Register resets to 0. Note: Changine trigger elay will flush the pipeline

0x0C. Status Register [Jump Back to Index]
Status - `STATUS`		General Status - R

Bits	Field	Function
0 0x0001	ExtBusy	Front-panel Busy Input (post-enable) (see Busy_Stat3 Reg)
1 0x0002	MExtBusyout	Masked ExtBusy Output (see Busy_Stat3 Reg)
2 0x0004	Busy	TIM stopping triggers internally (see Busy_Stat3 Reg)
3 0x0008	Busyout	Front-panel Busy Output (see Busy_Stat3 Reg)
4 0x0010	BurstActive	Burst is active (e.g. running: post-go, pre-done)
5 0x0020	SeqSrcAct	Sequencer Source Running
6 0x0040	SeqSinkAct	Sequencer Sink Running
7 0x0080	RodBusyout	Front-panel RodBusy Output (see Busy_Stat3 Reg)
8 0x0100	TTCClkOK	TTC system clock present (see Status3 Reg)
9 0x0200	SAClkOK	Stand-alone clock present (see Status3 Reg)
10 0x0400	RunMode	TTC system operation
11 0x0800	SaMode	Stand-alone operation
12 0x1000	-	reserved=0
13 0x2000	TIMOK	TTC clock is selected and good
14 0x4000	TestBusy	Test-Busy Triggered (see Busy_Stat3 Reg)
15 0x8000	LaserInterlock	Laser Interlock on (n/c on TIM3: pulled high)
As you can see, much of this is echoed in Status3 and Busy_Stat3 Registers. It is recommended to se the thse newer registers

0x0E. FIFO Status Register [Jump Back to Index]
FIFO Status - `FIFO`		FIFO Status - R

Bits	Field	Function
0- 5	IDcount	Event ID FIFO Count
6 0x0040	IDEF	Event ID Empty Flag
7 0x0080	IDFF	Event ID Full Flag
8-13	TTcount	Trigger Type FIFO Count
14 0x4000	TTEF	Trigger Type Empty Flag
15 0x8000	TTFF	Trigger Type Full Flag

0x10. Trigger ID Lo Register [Jump Back to Index]
Trigger ID Lo - `L1IDL`			Trigger Number LSW - R(/W)

Bits	Mode	Field	Function
0-15	R	L1IDlo	Last trigger number (bits 0-15)
Register resets to 0xFFFF. Read-only in RunMode

0x12. Trigger ID Hi Register [Jump Back to Index]
Trigger ID Hi - `L1IDH`			Trigger Number MSB/ ECR-ID - R(/W)

Bits	Mode	Field	Function
0- 7	R	L1IDhi	Last trigger number (bits 16-23)
8-15	R	ECRID	ECR counter
Register resets to 0x00FF. Read-only in RunMode

0x14. Trigger BCID Register [Jump Back to Index]
Trigger BCID - `BCID`			Trigger Bunch Crossing - R(/W)

Bits	Mode	Field	Function
0-11	R	BCID	Bunch Crossing number of last trigger
12-15	R/W	Offset	DEPRICATED: BCID offset (subtractive) (see BCIDOffset Reg)
Register resets to 0. Read-only in RunMode For extended BCID offset see BCID Offset Hi

0x16. Trigger Type ID Register [Jump Back to Index]
Trigger Type ID - `TTID`		Trigger Type - R(/W)

Bits	Field	Function
0- 7	TTID1	TTC Trigger Type
8-9	TTID2	TIM Trigger Type
10-15	-	reserved=0
Register resets to 0. In RunMode (7:0) are from TTCrq and read-only.

0x18. Run Enables Register [Jump Back to Index]
Run Enables - `RUN_ENABLE`		TTC and Other Enables - R/W

Bits	Field	Function
0 0x0001	EnTTCClk	Enable TTC clock
1 0x0002	EnL1A	Enable TTC L1Accept Trigger
2 0x0004	EnECR	Enable TTC ECReset
3 0x0008	EnBCR	Enable TTC BCReset
4 0x0010	EnCAL	Enable TTC Calibrate Strobe
5 0x0020	EnFER	Enable TTC FEReset
6 0x0040	EnSpare	Enable TTC Spare command
7 0x0080	EnRodBusy	Enable RodBusy into Busyout
8 0x0100	EnExtRodBusy	Enable external RodBusy input
9 0x0200	EnID	Enable trigger & bunch ID numbers
10 0x0400	EnTYPE	Enable trigger type
11 0x0800	-	reserved=0
12 0x1000	-	reserved=0
13 0x2000	-	reserved=0
14 0x4000	EnSaECR	Enable counter ECR
15 0x8000	EnSaBCR	Enable counter BCR
Register resets to 0.

0x1A. Sequencer Control Register [Jump Back to Index]
Sequencer Control - `SEQ_CTL`			Sequencer Control - R/W

Bits	Mode	Field	Function
0 0x0001	level	EnSeqTRIG	Enable L1Accept trigger
1 0x0002	level	EnSeqECR	Enable ECReset
2 0x0004	level	EnSeqBCR	Enable BCReset
3 0x0008	level	EnSeqCAL	Enable Calibrate strobe
4 0x0010	level	EnSeqID	Enable SerialID
5 0x0020	level	EnSeqTT	Enable SerialTT
6 0x0040	level	EnSeqFER	Enable FEReset
7 0x0080	level	EnSeqSpare	Enable Spare command
8 0x0100	-	-	reserved=0
9 0x0200	level	SeqReset	Reset Sequencer
10 0x0400	edge	SeqGo	Start Sequencer
11 0x0800	level	EnCyclic	Enable cyclic operation
12 0x1000	-	-	reserved=0
13 0x2000	level	SinkReset	Reset Sink
14 0x4000	edge	SinkGo	Start Sink (and Source)
15 0x8000	level	EnStartSink	Enable Sink trigger
Register resets to 0. Note: a sequencer control bit has one of two modes of operation: 1. level : command or enable is asserted while the bit is set (to 1) 2. edge : command is generated by setting the bit (from 0 to 1, ie the bit must be cleared to re-enable operation)

0x1C. Sequencer End Register [Jump Back to Index]
Sequencer End - `SEQ_END`		Sequencer End Count Value - R/W

Bits	Field	Function
0-13	EndAddr	End/Recycle address
14-15	-	reserved=0
Register resets to 0. Note: Counts from 0 - e.g. nClocks = (End+1)

0x1E. RODBusy Mask Register [Jump Back to Index]
RODBusy Mask - `RB_MASK`		ROD Mask - R/W

Bits	Field	Function
0-15	RODmask	RodBusy mask (16 slots: 5-12, 14-21)
Register resets to 0. Note: the ROD bits are in the order of ROD slot number, eg bit 0 is slot 5 in the ROD crate, bit 7 is slot 12, bit 8 is slot 14, etc.

0x20. RODBusy Status Register [Jump Back to Index]
RODBusy Status - `RB_STAT`		RODBusy Status - R

Bits	Field	Function
0-15	RodBusy	RodBusy status (16 slots: 5-12, 14-21)

0x22. RODBusy Latch Register [Jump Back to Index]
RODBusy Latch - `RB_LATCH`		RODBusy Latch - R/Z

Bits	Field	Function
0-15	RODlatch	RodBusy latch (16 slots: 5-12, 14-21)
Register resets to 0. Cleared by a WRITE. Note: the ROD bits are in the order of ROD slot number, eg bit 0 is slot 5 in the ROD crate.

0x24. RODBusy Monitor Register [Jump Back to Index]
RODBusy Monitor - `RB_MON`		RODBusy Monitor - R/Z

Bits	Field	Function
0-15	RODmonitor	RodBusy monitor (16 slots: 5-12, 14-21)
Register resets to 0. Cleared by a WRITE. Note: the ROD bits are in the order of ROD slot number, eg bit 0 is slot 5 in the ROD crate.

0x26. TTC Data Register [Jump Back to Index]
TTC Data - `TTC_DATA`		TTC Data Monitor - R/Z

Bits	Field	Function
0- 7	Dout	Long-format data
8-15	SubAddr	Sub-address
Register resets to 0. Cleared by a WRITE.

0x28. TTC Select Register [Jump Back to Index]
TTC Select - `TTC_SELECT`		TTC Data Monitor Select - R/W

Bits	Field	Function
0- 3	DQselect	Select long-format Data Qualifier
4-15	-	reserved=0
Register resets to 0.

0x2A. TTC BCID Register [Jump Back to Index]
TTC BCID - `TTC_BCID`		Last TTC BCID Received - R/Z

Bits	Field	Function
0-11	TTC_BCID	TTC bunch number
12-15	-	reserved=0
Register resets to 0. Cleared by a WRITE.

0x2C. TTCrx Control Register [Jump Back to Index]
TTCrx Control - `TTCRX_CTL`		TTCrx Control Register (I2C) - R/W

Bits	Field	Function
0- 7	Data	TTCrx data (read or write)
8-12	Pointer	TTCrx register number
13 0x2000	Read	I2C Read (not Write)
14 0x4000	Enable	T2: I2C clock enable/T3 R: Error Status, W: Abort
15 0x8000	Control	R: I2C Busy / W: I2C Go
Register resets to 0.

0x2E. TTC Status Register [Jump Back to Index]
TTC Status - `TTC_STATUS`		TTC Status - R

Bits	Field	Function
0 0x0001	BCntRes	BCReset
1 0x0002	EvCntRes	ECReset
2	Brcst(2)	FEReset bit - system message
3	Brcst(3)	Broadcast bit - system message
4	Brcst(4)	Broadcast bit - system message
5	Brcst(5)	Broadcast bit - system message
6	Brcst(6)	Calibrate bit - user message
7	Brcst(7)	Broadcast bit - user message
8 0x0100	L1Accept	Trigger
9 0x0200	BrcstStr1	Broadcast strobe - system message
10 0x0400	BrcstStr2	Broadcast strobe - user message
11 0x0800	DoutStr	Long-format data strobe
12 0x1000	DbErrStr	Double error or frame error occured
13 0x2000	SinErrStr	Single error occured
14 0x4000	TTCReady	TTCrx operating correctly (see Status3 Reg)
15 0x8000	-	reserved=0

0x30. TIM Output Latch Register [Jump Back to Index]
TIM Output Latch - `TIM_OUTPUT`		TIM Backplane Signals Output Latch - R/Z

Bits	Field	Function
0 0x0001	TTCout0	L1Accept trigger
1 0x0002	TTCout1	ECReset
2 0x0004	TTCout2	BCReset
3 0x0008	TTCout3	Calibrate strobe
4 0x0010	TTCout4	SerialID
5 0x0020	TTCout5	SerialTT
6 0x0040	TTCout6	FEReset
7 0x0080	TTCout7	Spare command
8-15	-	reserved=0
Register resets to 0. Cleared by a WRITE.

0x32. TIM ID Register [Jump Back to Index]
TIM ID - `TIM_ID`		Hardware and Firmware ID - R

Bits	Field	Function
0- 7	SerialNo	Serial number
8-15	Version	Version number

0x42. Enables3 Register [Jump Back to Index]
Enables3 - `ENABLES3`		TIM3 Specific Enables - R/W

Bits	Field	Function
0- 2	-	reserved=0
3 0x0008	-	reserved=0
4 0x0010	L1IDroECRen	Enable L1ID rollover to increment ECR-ID
5 0x0020	QpllControlEn	Untristate control lines to QPLL (on TTCrq mezzanine) (see QPLL_Ctl Reg)
6 0x0040	Random2En	Enable Randomiser 2 (results unreliable if used with EnRandom) (see Control Reg)
7 0x0080	TrigOsc2En	Enable Trigger Oscillator 2 (see Trig_Osc2l Reg)
8 0x0100	TrigSeqModeEn	Stand-alone trigs diverted to become SeqGo instead (useful for sending trigger sequences at random intervals) (see Seq_Ctl Reg)
9 0x0200	ShortFPSigsEn	Set front-panel L1A,ECR,BCR,CAL,FER & Spare signals pulse width to 25ns (from 40ns) (Prevents these LEDs working correctly on TIM-3E's)
10 0x0400	PreBusyBurstEn	Burst counts triggers prior to busy action. Useful for testing trig-in vs trigs-out relationships
11 0x0800	~~SaTtcL1aEn~~	~~OR TTC-L1A into SA trigger (i.e. can be delayed, has deadtime and generates busy)~~
12 0x1000	SaTtcTtidEn	TTC-TType replaces SA TTtype (but only when using SA-TTC-L1A above)
13 0x2000	~~SaTtcBcrEn~~	~~OR TTCrx BCR & ECR into SA signals (i.e. can be delayed in SA system)~~
14 0x4000	BCRDelayEn	Enable ~~TTC~~ SA BCR & ECR to be delayed by trigger delay value
15 0x8000	BCIDMaxEn	Enable BCID to rollover at 4095 (not 3564) for RunMode offset correction reasons
Register resets to 0.

0x46. Control Register [Jump Back to Index]
Control - `CONTROL`		General Control - R/W

Bits	Field	Function
0 0x0001	-	reserved=0
1 0x0002	-	reserved=0
2 0x0004	-	reserved=0
3 0x0008	FFTVEmerClr	Clear an FFTV emergency state (serious!)
4- 8	Rand2Freq	Average frequency of Randomiser 2 (see table below) (see Enables3 Reg)
9-15	Rand2ClkDiv	Randomiser 2 Clock divider for larger bunch spacing tests
Register resets to 0.

Random2 Frequency (Control<8:4>) Lookup Table
1F	1E	1D	1C	1B	1A	19	18
40 MHz	40 MHz	40 MHz	40 MHz	40 MHz	40 MHz	40 MHz	40 MHz
17	16	15	14	13	12	11	10
40 MHz	20 MHz	10 MHz	5 MHz	2.5 MHz	1.2 MHz	600 kHz	300 kHz
F	E	D	C	B	A	9	8
150 kHz	80 kHz	40 kHz	20 kHz	10 kHz	5 kHz	2.5 kHz	1.2 kHz
7	6	5	4	3	2	1	0
600 Hz	300 Hz	160 Hz	75 Hz	40 Hz	10 Hz	5 Hz	1 Hz

0x4A. Status3 Register [Jump Back to Index]
Status3 - `STATUS3`		TIM3 Specific Status bits - R

Bits	Field	Function
0 0x0001	TTCReady3	TTCrx operating correctly (see TTC_Status Reg)
1 0x0002	QpllPresent	TTCrq/QPLL chip present
2 0x0004	QpllError	QPLL Chip Error
3 0x0008	QpllLocked	QPLL Locked
4 0x0010	TtcClkOK3	TTC clock is present (see Status Reg)
5 0x0020	-	reserved=0
6 0x0040	SaClkOK3	SA clock is present (see Status Reg)
7 0x0080	TtcClkEnOK	TTC Clock Selected and Running ('TT' front-panel LED)
8 0x0100	ExtClkEnOK	Ext Clock Selected and Running
9 0x0200	IntClkEnOK	Internal Clock Selected and Running
10 0x0400	PllStable	Clock PLL(s) stable after switching clocks (asserted ~700ms after switch)
11 0x0800	-	reserved=0
12 0x1000	-	reserved=0
13 0x2000	-	reserved=0
14 0x4000	spare_in	Spare Input
15 0x8000	spare_link	Spare Link
See Clock Flow Diagram See Clock Select Diagram

0x4C. Status Change Latch Register [Jump Back to Index]
Status Change Latch - `STATUS_LCH`		Status Change Latch - R/Z

Bits	Field	Function
0-15	Status Change Latch	Watches Status Reg and logs 1s for bit changes (glitches too). Armed by a write.
Register resets to 0. Cleared by a WRITE. See Status Reg for bits. Should be cleared after reset/config

0x4E. Status3 Change Latch Register [Jump Back to Index]
Status3 Change Latch - `STAT3_LCH`		Status3 Change Latch - R/Z

Bits	Field	Function
0-15	Status3 Change Latch	Watches Status3 Reg and logs 1s for bit changes (glitches too). Armed by a write
Register resets to 0. Cleared by a WRITE. See Status3 Reg for bits. Should be cleared after reset/config

0x52. QPLL Control Register [Jump Back to Index]
QPLL Control - `QPLL_CTL`		QPLL Control - R/W

Bits	Field	Function
0- 3	QpllF0Select	QPLL f0 Select (bits 3:0)
4 0x0010	QpllAutorestart	QPLL Auto-restart/f0 sel bit 4
5 0x0020	nQpllReset	QPLL Reset/f0 Select bit 5
6 0x0040	QpllExtControl	QPLL External Control Enable
7 0x0080	QpllMode	QPLL Mode
8 0x0100	-	reserved=0
9 0x0200	-	reserved=0
10 0x0400	-	reserved=0
11 0x0800	-	reserved=0
12 0x1000	-	reserved=0
13 0x2000	-	reserved=0
14 0x4000	-	reserved=0
15 0x8000	-	reserved=0
Register resets to 0x00B0.

0x56. Busy Enable3 Register [Jump Back to Index]
Busy Enable3 - `BUSY_EN3`		Busy Enable3 - R/W

Bits	Field	Function
0 0x0001	enRBbusy	Enable RodBusy into Busy
1 0x0002	enXRBbusy	Enable External-RodBusy into Busy
2 0x0004	enVRBbusy	Enable VME-RodBusy into Busy
3 0x0008	enXBbusy	Enable External-Busy into Busy
4 0x0010	enVBbusy	Enable VME-Busy into Busy
5 0x0020	-	reserved=0
6 0x0040	-	reserved=0
7 0x0080	-	reserved=0
8 0x0100	enRBbusyout	Enable RodBusy into Busyout
9 0x0200	enXRBbusyout	Enable External-RodBusy into Busyout
10 0x0400	enVRBbusyout	Enable VME-RodBusy into Busyout
11 0x0800	enXBbusyout	Enable External-Busy into Busyout
12 0x1000	enVBbusyout	Enable VME-Busy into Busyout
13 0x2000	enBSTBbusyout	Enable Burst-Busy into Busyout
14 0x4000	enTSTBbusyout	Enable Test-Busy into Busyout
15 0x8000	enDTBbusyout	Enable Deadtime-Busy into Busyout
Register resets to 0x1000. See Busy Flow Diagram

0x5A. Busy Status3 Register [Jump Back to Index]
Busy Status3 - `BUSY_STAT3`		Busy Status3 - R

Bits	Field	Function
0 0x0001	RodBusy	RB: OR of all RodBusy backplane inputs (post masking)
1 0x0002	ExtRodBusy	XRB: External RodBusy (post-enable)
2 0x0004	vRodBusy3	VRB: VME-RodBusy
3 0x0008	ExtBusy3	XB: Front Panel Busy Input (post-enable)
4 0x0010	vBusy3	VB: VME-Busy
5 0x0020	BurstBusy3	BSTB: Burst Ready - awaiting Burst-Go/Burst Done
6 0x0040	TestBusy3	TSTB: Test-Busy Triggered
7 0x0080	DeadTimeBusy	DTB: Stand-Alone Signal Dead-Time
8 0x0100	ClkSwitchBusy	Timeout after clock-switch/reset to ensure downstream stable
9 0x0200	Busy3	TIM stopping triggers internally
10 0x0400	RodBusyout3	Front-panel RodBusy Output
11 0x0800	Busyout3	Front-panel Busy Output
12 0x1000	MExtBusyout3	Front-panel Masked ExtBusy Output
13 0x2000	FFTVEmergency	FFTV System In Emergency State, Triggers Stopped
14 0x4000	FFTVBusy	Fixed Frequency Trigger Veto Busy Asserted
15 0x8000	FFTVLinkStat	FFTV Disable Link Inserted
See Busy Flow Diagram

0x5E. Busy Status3 Change Latch Register [Jump Back to Index]
Busy Status3 Change Latch - `BSTAT3_LCH`		Catches changes in BSTAT3 since last reset/clear - R/Z

Bits	Field	Function
0-15	Busy Status3 Change Latch	Watches Busy Status3 Reg and logs 1s for bit changes (glitches too). Armed by a write
Register resets to 0. Cleared by a WRITE. See Busy Status3 Reg for bits. Should be cleared after reset/config

0x60. Overall Busy Count Lo Register [Jump Back to Index]
Overall Busy Count Lo - `BCOUNTL`		Busy Count (15:0) - Number of clocks RodBusy is asserted (as sent out of front panel) - R/Z

Bits	Field	Function
0-15	Overall Busy Count Lo
Register resets to 0. Cleared by a WRITE. A write to the LSW of the Overall Busy Count registers will reset all of them.

0x62. Overall Busy Count Hi Register [Jump Back to Index]
Overall Busy Count Hi - `BCOUNTH`		Busy Count (31:16) - Number of clocks RodBusy is asserted (as sent out of front panel) - R/Z

Bits	Field	Function
0-15	Overall Busy Count Hi
Register resets to 0. Cleared by a WRITE. A write to the LSW of the Overall Busy Count registers will reset all of them.

0x66. BCID Offset Extended Register [Jump Back to Index]
BCID Offset Extended - `BCIDOFFSET`		BCID Offset (11:0) - Covers full orbit - R/W

Bits	Field	Function
0-11	BCID Offset Extended	Offset subtracted from TTC-BCID (from TTCrx) for sending to ROD (see BCID Reg)
Register resets to 0. Note this supercedes 4 bit BCID offset in BCID Register. Bits (3:0) are common to both (i.e. current code will still work) NB: Setting offset >3563 is only supported when using BCIDMaxEn.

0x6A. FFTV Match Threshhold Register [Jump Back to Index]
FFTV Match Threshhold - `FV_MATCH`		FFTV Match Threshhold - R/W

Bits	Field	Function
0- 3	FFTV Match Threshhold	Number of Matching Periods needed to Generate Veto
4-15	-	reserved=0
Register resets to 10. Only values between 2 and 10, otherwise defaults to 10.

0x74. FFTV Count Lo Register [Jump Back to Index]
FFTV Count Lo - `FV_COUNTL`		Number of Clocks in FFTVeto Counter (15:0) - R/Z

Bits	Field	Function
0-15	FFTV Count Lo
Register resets to 0. Cleared by a WRITE. A write to the LSW of the FFTV Count registers will reset all of them.

0x76. FFTV Count Hi Register [Jump Back to Index]
FFTV Count Hi - `FV_COUNTH`		Number of Clocks in FFTVeto Counter (31:16) - R/Z

Bits	Field	Function
0-15	FFTV Count Hi
Register resets to 0. Cleared by a WRITE. A write to the LSW of the FFTV Count registers will reset all of them.

0x78. FFTV Count Ex Register [Jump Back to Index]
FFTV Count Ex - `FV_COUNTX`		Number of Clocks in FFTVeto Counter (47:32) - R/Z

Bits	Field	Function
0-15	FFTV Count Ex
Register resets to 0. Cleared by a WRITE. A write to the LSW of the FFTV Count registers will reset all of them.

0x7C. FFTV Trigger Count Lo Register [Jump Back to Index]
FFTV Trigger Count Lo - `FV_TCOUNTL`		Number of Triggers FFTVeto'd (15:0) - R/Z

Bits	Field	Function
0-15	FFTV Trigger Count Lo
Register resets to 0. Cleared by a WRITE. A write to the LSW of the FFTV Trigger Count registers will reset all of them.

0x7E. FFTV Trigger Count Hi Register [Jump Back to Index]
FFTV Trigger Count Hi - `FV_TCOUNTH`		Number of Triggers FFTVeto'd (31:16) - R/Z

Bits	Field	Function
0-15	FFTV Trigger Count Hi
Register resets to 0. Cleared by a WRITE. A write to the LSW of the FFTV Trigger Count registers will reset all of them.

0x80. Trigger Period FIFO Lo Register [Jump Back to Index]
Trigger Period FIFO Lo - `TP_FIFOL`		Trigger Period FIFO (15:0) - R/Z

Bits	Field	Function
0-15	Trigger Period FIFO Lo
Register resets to 0. Cleared by a WRITE. A write to the LSW of the Trigger Period FIFO registers will reset all of them.

0x82. Trigger Period FIFO Hi Register [Jump Back to Index]
Trigger Period FIFO Hi - `TP_FIFOH`		Trigger Period FIFO (31:16) - R/Z

Bits	Field	Function
0-15	Trigger Period FIFO Hi
Register resets to 0x4000. Cleared by a WRITE. A write to the LSW of the Trigger Period FIFO registers will reset all of them.

0x84. Veto ID Lo Register [Jump Back to Index]
Veto ID Lo - `FV_IDL`		Counts Number of times Veto is Asserted (15:0) - R/Z

Bits	Field	Function
0-15	Veto ID Lo
Register resets to 0. Cleared by a WRITE. A write to the LSW of the Veto ID registers will reset all of them.

0x86. Veto ID Hi Register [Jump Back to Index]
Veto ID Hi - `FV_IDH`		Counts Number of time Veto is Asserted (31:16) - R/Z

Bits	Field	Function
0-15	Veto ID Hi
Register resets to 0. Cleared by a WRITE. A write to the LSW of the Veto ID registers will reset all of them.

0x88. Trigger Osc2 Period Lo Register [Jump Back to Index]
Trigger Osc2 Period Lo - `TRIG_OSC2L`		Counter-based Trigger Oscillator (15:0) - R/W

Bits	Field	Function
0-15	Trigger Osc2 Period Lo
Register resets to 0. Enabled by TrigOsc2En

0x8A. Trigger Osc2 Period Hi Register [Jump Back to Index]
Trigger Osc2 Period Hi - `TRIG_OSC2H`		Counter-based Trigger Oscillator (31:16) - R/W

Bits	Field	Function
0-15	Trigger Osc2 Period Hi
Register resets to 0. Enabled by TrigOsc2En

0x8E. Burst Count Hi Register [Jump Back to Index]
Burst Count Hi - `BURST_HI`		Burst Counter (31:16) - R/W

Bits	Field	Function
0-15	Burst Count Hi
Register resets to 0. Note: Used in Conjuction with Burst Reg. Enable L1ID-rollover-to-ECRID (ENABLES3,4) to count 32 bit L1ID

0x94. F2 Timestamp Lo Register [Jump Back to Index]
F2 Timestamp Lo - `TSTAMPL`		F2 Timestamp (15:0) - R

Bits	Field	Function
0-15	F2 Timestamp Lo

0x96. F2 Timestamp Hi Register [Jump Back to Index]
F2 Timestamp Hi - `TSTAMPH`		F2 Timestamp (31:16) - R

Bits	Field	Function
0-15	F2 Timestamp Hi

0x9C. F2 Debug Control Register [Jump Back to Index]
F2 Debug Control - `DEBUG_CTL`		F2 Debug Control - R/W

Bits	Field	Function
0- 3	-	reserved=0
4 0x0010	-	reserved=0
5 0x0020	-	reserved=0
6 0x0040	-	reserved=0
7 0x0080	-	reserved=0
8 0x0100	CSBdisable	Disable Clk-Switch Busy
9 0x0200	SARBdisable	Disable SA-Mode setting RodBusy
10 0x0400	-	reserved=0
11 0x0800	-	reserved=0
12 0x1000	FVdisable	FFTV Veto Disable (needs link in place too)
13 0x2000	-	reserved
14 0x4000	-	reserved=0
15 0x8000	-	reserved=0
Register resets to 0.

0x9E. F2 Debug Status Register [Jump Back to Index]
F2 Debug Status - `DEBUG_STAT`		F2 Debug Status - R

Bits	Field	Function
0- 3	-	reserved=0
4 0x0010	-	reserved=0
5 0x0020	-	reserved=0
6 0x0040	-	reserved=0
7 0x0080	-	reserved=0
8 0x0100	-	reserved=0
9 0x0200	-	reserved=0
10 0x0400	-	reserved=0
11 0x0800	-	reserved=0
12 0x1000	-	reserved=0
13 0x2000	-	reserved=0
14 0x4000	-	reserved=0
15 0x8000	-	reserved=0

Sequencer RAM

Sequencer RAM Address Map

Address	Byte Field (D16 access only)
8000	First byte of Source data
8001	First byte of Sink data
...	...
FFFE	Last byte of Source data
FFFF	Last byte of Sink data

Notes:
1. The source and sink memories are each 16K bytes long, interleaved with the source being the least significant byte of each 16-bit word, giving 32K bytes (16K words) of sequencer memory in total. 2. The memories have no reset and have undefined values after a power-up cycle; to be safe they should be filled with zeros after each TIM RESET.

Sequencer RAM
VME Address: 8000-FFFE		R/W

bit	Field	Function
0	SourceTRIG	Source L1Accept trigger
1	SourceECR	Source ECReset
2	SourceBCR	Source BCReset
3	SourceCAL	Source Calibrate strobe
4	SourceID	Source SerialID
5	SourceTT	Source SerialTT
6	SourceFER	Source FEReset
7	SourceSpare	Source Spare command
8	SinkTRIG	Sink L1Accept trigger
9	SinkECR	Sink ECReset
10	SinkBCR	Sink BCReset
11	SinkCAL	Sink Calibrate strobe
12	SinkID	Sink SerialID
13	SinkTT	Sink SerialTT
14	SinkFER	Sink FEReset
15	SinkSpare	Sink Spare command

TIM Registers List

For Firmware Version 26

Contents

Address Map

IntTRIGfreq lookup table

IntFERfreq lookup table

Random2 Frequency (Control<8:4>) Lookup Table