PROCEDURE FOR BASIC ACCEPTANCE TESTING OF TIM-3B MODULES AT UCL =============================================================== ####DRAFT#### ********************************************************* **** SEVENTH DRAFT **** MP & MW - UCL, 15 AUGUST 2005 ********************************************************* NOTE : The PCB/COMPONENT/TEST PINS details in this note refer ====== to the TIM-3B ( PC3216M ) version diagrams dated 13-02-2004 **************************************************************** NOTE : For ***PHOTOS***, see http://www.hep.ucl.ac.uk/atlas/sct/tim/v3/TIM3C_Setup_Photos.pdf **************************************************************** A) FIRST check that there is NO SHORT between any of the six supply rails ( +5V, +3V3, -5V2, +12V, -12V, GND ) This is easily done by DVM using the FUSES FS1 = +3V3 (5A) (Diag.01) FS2 = +12V (5A) FS3 = -12V (5A) FS4 = +5V (10A) FS5 = -5V2 (10A) B) Check visually that both FPGAs and other SMD ICs are soldered well enough to your satisfaction - especially noting any bent or loose pins C) Hardwire program the low 8 bits of the SERIAL NUMBER Register : This is by using the 8x 0 Ohm resistors next to U75 ( Diag.07/U75 ) R97 1/2 = SERN(0) = LSB ***SEE PHOTO-7*** to R90 1/2 = SERN(7) = MSB All these links, as received from manufacture, have 0Ohm resistors between pads 1 and 2, thus setting all bits SERN<0-7> = GND = 0 Any bit which requires to be set HIGH = 1 must have resistor removed. This permits for any serial number #001 to #255 to be hard-wired. NOTE : Following modules already exist : TIM-0 #001, #002 ====== TIM-1 #103, #104 TIM-2A #205- #210 TIM-2B #211, #212 TIM-2C #213, #214 TIM-3A #320, #321 TIM-3B #322- #325 TIM-3C #326- #349 /cont: - 2 - D) Follow the set-up procedure described below : http://www.hep.ucl.ac.uk/atlas/sct/tim/rel/tim3C/TIM-3C_Setup.txt ***************************************************************** E) Plug the TIM module into any slot of the 9U-VME64x test crate in D.25, using 6U-VME64x extender ( for J1 & J2 only ) - if available - until signals on J3 need to be checked. F) Turn on the 9U-VME crate power and observe the green power-indicator LEDs on the front panel of the TIM module : -> The +5V,-5V,+12V,-12V green LEDs should be 'ON' ( Diag.01/DS1 -> The +3V green LED should be 'OFF' Diag.01/DS2 Diag.16/DS3 ) G) Check that the -5V2 supply is between -5V1/-5V2 w.r.t. GND at the fuse FS1 . ( Diag.1/FS1 ) -> If different, adjust the trim potentiometer R103 as required to achieve this value ( Diag.14/R103 ) H) Check the current consumption of the TIM module by stepping through the 9U-VME crate front panel display volt/current sequence using the "MODE SELECT" switch next to the display : -> No current should indicate over 12 A I) Program both PROMs and both FPGAs J) Start by checking the FPGA-1 / VME access : -> run U:\jbl\tubbies\po -> observe "VA" ( VME DTACK ) and "VE" ( VME ERROR ) LEDs on the front panel of the TIM. These should flash briefly as specified by the program ( Diag.16/DS4 ) -> STAND-ALONE MODE red LED indicator "SA" should be permanently lit ( Diag.16/DS5 ) -> STAND-ALONE CLOCK yellow LED indicator "SC" should be permanently lit ( Diag.16/DS6 ) K) Check the quality of the output clock using OSCILLOSCOPE at the TEST POINT PL117 ( Diag.12/U54 ) -> Compare this with the sample printout to check mark-to-space and general shape. -> Check average jitter to be =< 200 psec on the clock 2nd raising edge ( first after the trigger point ) /cont: - 3 - L) If this is satisfactory, "STAND-ALONE" operations should be checked next : 1) press "RESET" switch on the front panel and observe the red LED indicator "OR" ( OVERALL RESET ) flash once ( Diag.10/SW2 ) ( Diag.16/DS3 ) NOTE 8 : press "RESET" between each INDIVIDUALLY-NUMBERED step : ====================================================================== 2) press "TEST TRIGGER" switch and observe the green LED indicator "LA" ( LEVEL-1-ACCEPT ) flash once ( Diag.10/SW1 ) ( Diag.16/DS8 ) 3) Using U:\jbl\tubbies\po : a) Register 0 : ENINTTRIG ( address 00, write 2 ) -> check "LA" LED is lit -> check output on TEST POINT PL25, using OSCILLOSCOPE, to be 25nsec long pulse at fixed frequency ~600kHz ( Diag.15/U4 ) b) Register 3 : INTTRIGFREQ ( address 06, write 2 ) -> check output frequency reduced to ~300kHz c) Register 0 : ENEXTTRIG ( address 00, write 200 ) plus connect LEMO cable between NIMTRIGIN and NIMCLKOUT -> check check output on TEST POINT PL25,using OSCILLOSCOPE to be 25nsec long pulse with a minimum gap between subsequent triggers to be >= 3 clock periods ( Diag.15/U4 ) d) Register 0 : ENINTTRIG plus ENRANDOM ( address 00, write 12 ) -> check output on TEST POINT PL25, using OSCILLOSCOPE, to be 25nsec long pulse at varying frequency =<150kHz ( Diag.15/U4 ) e) Register 3 : INTTRIGFREQ ( address 06, write 2 ) -> check output random frequency reduced to =< 75kHz /cont: - 4 - f) check sequentially all internally-generated signals, using Register 0 and TEST POINTS as follows : ENTINTECR (4) TEST POINT PL16 ( Diag.15/U4 ) ENTINTBCR (8) PL2 ( Diag.15/U4 ) ENINTFER (20) PL31 ( Diag.15/U1 ) g) Use Register 3 to vary INTECR/BCR frequency h) Check INTBCR frequency to be ~11.24 kHz i) enable ENINTBUSY in Register 0 (80) and check at TEST POINT PL41 while running the above internally-generated signals ( Diag.15/U1 ) 4) Check externally-input signals, using NIM input connectors on the front panel, sequentially linked to NIMCLKOUT : j) use Register 0 and TEST POINTS as follows : ENEXTRTIG(200) TEST POINT PL25 ( Diag.15/U4 ) ENEXTECR (400) PL16 ( Diag.15/U1 ) ENEXTBCR (800) PL2 ( Diag.15/U4 ) ENEXTFER (2000) PL31 ( Diag.15/U1 ) ENEXTSPARE (4000) PL32 ( Diag.15/U1 ) k) ENEXTCAL (1000) PL7 ( Diag.15/U4 ) and PL25 for the automatically generated "CALTRIG" l) use ENEXTCAL to check the operation of the "Trigger Pipeline Delay" : - use Register 5 to vary the delay between "CAL" pulse on TEST POINT PL7 and the "CALTRIG" pulse on TEST POINT PL25 -> this should increment in steps of 1 clock period M) Check the operation of "EXTCLK" : 1) connect NIMEXTCLK input connector to the NIMCLKOUT output of a CLOAC module in same crate 2) use U:\jbl\tubbies\dipsy to initialise the CLOAC module 3) use U:\jbl\tubbies\po to operate the TIM module : a) Register 0 : ENEXTCLK ( address 00, write 100 ) -> Check the quality of the output clock using OSCILLOSCOPE at the TEST POINT PL117 ( Diag.12/U54 ) b) unplug the NIM cable and check that TIM switches to INTCLK automatically /cont: - 5 - N) Test BURST MODE : ***** /cont: - 6 - O) Test TRIG. WINDOW : 1) a) Register 0: ENEXTTRIG plus ENWINDOW ( address 00,write 240 ) plus connect LEMO cable between NIMTRIGIN and NIMCLKOUT -> check output on TEST POINT PL25/1, using OSCILLOSCOPE ( Diag.15/U4 ) b) check calibration of default switch settings : ( Diag.08/U61 ) SW9: Trig. Window Delay Setup(*): # 010000 ( 10 ) ( Diag.08/U63 ) SW10: Trig. Window Size Comp.(*) : # 001001 ( 9 ) (*) NOTE that the "Trigger Window" has been calibrated with respect to the clock "MCLK1" on Test Point PL117. With the above default setting of ROD SETUP delay, this "MCLK1" clock is about 13 nsec earlier then the "NIMCLKOUT" clock output on the front panel socket SK10. c) Register 4 : WINSIZE ( Diag.8 ) -> check TRIG.WINDOW pulse at pin 8 of U64 ( Diag.8/U64 ) d) Register 4 : WINDELAY -> check TRIG.WINDOW pulse at pin 8 of U64 ( Diag.8/U64 ) "TRIGGER WINDOW" CALIBRATION PROCEDURE : ---------------------------------------- The "Trigger Window" allows you to select only those external triggers with selected timing relationship with respect to selected clock. This is useful for random triggers ( eg. from cosmics ). Please note that this feature operates on EXTERNAL TRIGGERs only. - To calibrate this feature for any particular clock, pre-select the Trigger Window and the NIM/ECL external trigger ( Register 0, Bits 6 and 9 'on' = 240hex ). Decide to which clock and at which point of the clock chain you want to calibrate this feature - this could be outside the TIM-3 module. Hook-up one scope probe to this point. - To observe the Trigger Window pulse, hook-up the second scope probe to U64 pin 8 on the TIM-3 module ( signal "NTRIG_WIN" - see diag.08 ). - Set WINDOW SIZE = 2 ( Register 4 Bit 1 'on' = address 8, write 2). Set SW10 ( Trigger Window Size Compensation ) so there is only a sharp short -ve spike on U64 pin 8. This spike must disappear when Reg.4 = 0. - Set WINDOW SIZE = 10 ( Reg.4 Bit 4 'on' = address 8, write 10) and set SW9 ( Trigger Window Setup ) so that the -ve edge of the window pulse output is coincident with the +ve edge of the selected clock. The WINDOW SIZE is valid between 0 and ~28 in steps of 0.5 nsec. This window can then be scanned over the whole of the 25 nsec clock period by the WINDOW DELAY setting ( Reg 4, Bits 8-13 = address 8, write 100 - 3000 ). /cont: - 7 - -------------------------------------------------------------------------- From now on, this list is even more ***sketchy*** : most of the further testing could/should be done by stand-alone test software. --------------------------------------------------------------------------- P) Test VME-GENERATED COMMANDS R) Test TEST BUSY S) Test BURST MODE 1) INT/EXT. TRIGGER 2) INT. CAL ( ie. re-circulating automatically ) 3) EXT. CAL ( ie. requires input CAL repetitively ) T) Check STATUS REGISTER U) Check RUN MODE This version : MP-UCL, 15 Aug. 2005 Previous versions : 09 Jun. 2005 26 May 2005 01 Apr. 2005 25 Feb. 2005 11 Oct. 2004 05 Aug. 2004 17 Oct. 2003 21 Aug. 2003 29 Jul. 2003 25 Jul. 2003