TIM-3F MODULE SETTING-UP : ============================== MP & MW - UCL, 23 October 2008 ************************************************************************ NOTE 0: For ***PHOTOS***, see ======= http://www.hep.ucl.ac.uk/atlas/sct/tim/tim-muons.shtml ************************************************************************ NOTE 1: Default setup is indicated by '#' ======= FOR TESTS IN NON-STANDARD CRATES SOME SETTING MAY NEED TO BE DIFFERENT. THIS IS INDICATED BY '++' NOTE 2: IC numbers ( Uxx ) refer to the nearest IC receiving the ======= signal selected by the link/switch etc. NOTE 3: Diagram numbers refer to the TIM-3E version of circuit schematics ======= page with the relevant link/switch/etc-see PC3216M dated 17-05-2005 1) Set VME Base Address switches : ***SEE PHOTO-1*** ------------------------------- ( Diag.05 ) SW3 : sets A16 - A19 # default : SW3 = 0 SW4 : sets A20 - A23 SW4 = F SW5 : sets A24 - A27 SW5 = D SW6 : sets A28 - A31 SW6 = 0 ( this sets the A24-A28 = 13 ie. the ROD Crate TIM Slot Geographical Address GA(4-0)* = 10010 ) DEFAULT BASE ADDRESS FOR TIM IN ATLAS-SCT VME64ex CRATE IS 0x0D00 2) Set various Delay Switches : **SEE SPECIAL PHOTO IN THE URL ABOVE** ---------------------------- **THESE SETTINGS DIFFER FROM TIM-3C** ===================================== NOTE 4: Note that the LEAST SIGNIFICANT DELAY BIT "A0" is the top slide ======= of the DIL switch ( with the edge marked WHITE to the right ). The MOST SIGNIFICANT DELAY BIT "A5" is the bottom slide ( with the edge marked WHITE to the right ). The "ON" position ( 'ON' = 1 ) is with the relevant slide towards the switch edge marked WHITE. The "OFF" position ( 'OFF' = 0 ) is with the relevant slide towards the unmarked ( black ) edge. Ignore any other lever markings or numbers on actual switch bodies ( eg. switches are marked 1-6 instead of 0-5 ). ( Diag.07/U47 ) SW7: TIM Setup delay DL4 # 011111 ( 1f ) ( Diag.07/U46 ) SW8: ROD Setup delay DL2 # 010001 ( 11 ) ( Diag.08/U61 ) SW9: Trig. Window Setup (*): # 000000 ( 0 ) ( Diag.08/U62 ) SW10: Trig. Window Size Comp.(*) : # 000110 ( 6 ) (*) NOTE that the "Trigger Window" has been calibrated with respect to the clock "MCLK1" on Test Point PL117. With the above default setting of ROD SETUP delay, this "MCLK1" clock is about 10 nsec earlier then the "NIMCLKOUT" clock output on the front panel socket SK10. ( See below for calibrating to different clocks ). /cont: - 2 - "TRIGGER WINDOW" CALIBRATION PROCEDURE : ---------------------------------------- The "Trigger Window" allows you to select only those external triggers with selected timing relationship with respect to selected clock. This is useful for random triggers ( eg. from cosmics ). Please note that this feature operates on EXTERNAL TRIGGERs only. - To calibrate this feature for any particular clock, pre-select the Trigger Window and the NIM/ECL external trigger ( Register 0, Bits 6 and 9 'on' = 240hex ). Decide to which clock and at which point of the clock chain you want to calibrate this feature - this could be outside the TIM-3 module. Hook-up one scope probe to this point. - To observe the Trigger Window pulse, hook-up the second scope probe to U64 pin 8 on the TIM-3 module ( signal "NTRIG_WIN" - see diag.08 ). - Set WINDOW SIZE = 2 ( Register 4 Bit 1 'on' = address 8, write 2). Set SW10 ( Trigger Window Size Compensation ) so there is only a sharp short -ve spike on U64 pin 8. This spike must disappear when Reg.4 = 0. - Set WINDOW SIZE = 10 ( Reg.4 Bit 4 'on' = address 8, write 10) and set SW9 ( Trigger Window Setup ) so that the -ve edge of the window pulse output is coincident with the +ve edge of the selected clock. The WINDOW SIZE is valid between 0 and ~26 in steps of 0.5 nsec. This window can then be scanned over the whole of the 25 nsec clock period by the WINDOW DELAY setting ( Reg 4, Bits 8-13 = address 8, write 100 - 3000 ). 3) -5V2 Supply Potentiometer : ***SEE PHOTO 14*** --------------------------- Check that the -5V2 supply is between -5V1/-5V2 w.r.t. GND at the fuse FS1 ( Diag.1/FS1 ) -> If different, adjust the trim potentiometer R103 as required to achieve this value ( Diag.1/R103 ) /cont: - 3 - 4) 2-pin Links : ***SEE PHOTOS-3,4,6*** ------------- ( Diag.05/U86 ) PL164 in # bypasses VME interrupt IACK daisychain ***SEE PHOTO-3*** out enables VME interrupt IACK daisy-chain ( Diag.05 ) PL160 out # "B_SELECT" : spare VME Addressing link to U76 ( FPGA-1 ) pin P19 ( Diag.05 ) PL154 in ++ selects switch-set VME Base Address ( see par. 1 ) out # VME Base address set to VME GA(4-0)* = 10010 ( Diag.01/U83 ) PL158 in disables -5V2 DC converter out # enables -5V2 DC converter ( Diag.13/U85 ) PL167 in enables TIM_BUSY_OUT onto P3 b/plane out # disables TIM_BUSY_OUT output ( Diag.13/U85 ) PL168 in overrides P3 b/plane drivers disable by ROD_SENSE out # P3 b/plane drivers only enabled by correct ROD_SENSE ( Diag.13/U89 ) PL170 in # enables TIM-OK output onto P3 b/plane ***SEE PHOTO-4*** out++ disables TIM-OK output to P3 b/plane ( Diag.12/U107) PL176 in connects input clock onto the test point PL197/A out # isolates input clock from the test point PL197/A ( Diag.05/U72 ) SB3-SB7 VME Clocking Delay Line DL0 setup ==== THESE LINKS ARE ALREADY PROGRAMMED ON PCB - DO NOT CHANGE ==== ==================================================================== ( Diag.04/U72 ) PL139 } in JTAG chain individual by-pass links ( Diag.04/U76 ) PL141 } ( Diag.04/U59 ) PL119 } out # DO NOT INSERT ANY OF THESE LINKS !! ( Diag.04/U67 ) PL123 } =================================== ( Diag.06/U67 ) PL163 in # all LV input buffers enabled ***SEE PHOTO-3*** out will disable all LV Input buffers for JTAG Boundary-scan testing only ( Diag.02/U76 ) PL180 in # program mode pins M0,M1, M2 of FPGA-1 **SEE PHOTO-3** PL181 in # ( default is M0=M1=M2=GND ) PL182 in # ( Diag.03/U67 ) PL183 in # program mode pins M0,M1, M2 of FPGA-2 **SEE PHOTO-6** PL184 in # ( default is M0=M1=M2=GND ) PL185 in # ( Diag.03 ) PL202 out # "F2_SPARE_LINK" : spare link to U67 ( FPGA-2 ) pin N19 ( Diag.03 ) PL203 out # "Repetitive Trigger Veto" functional ***SEE PHOTO-6*** in ++ "Veto" can be by-passed IN Reg.9c NOTE : WE ASSUME THAT YOU WILL BE USING THIS 'VETO' FACILITY. ====== TO BY-PASS IT, YOU MUST SET REGISTER 9C BIT 12 TO '1' /cont: - 4 - 5) 3-pin Links : ***SEE PHOTOs-4,5,6*** ------------- ( Diag.14/U31 ) LK3 pins 1+2 # NIMTRIGINOUT = true (NIM -ve stand.) ***SEE PHOTO-5*** 2+3 NIMTRIGINOUT = inverted LK6 pins 1+2 # NIMBUSYOUT = true (NIM -ve standard) 2+3 NIMBUSYOUT = inverted LK2 pins 1+2 # NIMTRIGOUT = true (NIM -ve standard) 2+3 NIMTRIGOUT = inverted LK5 pins 1+2 # NIMCLKOUT = true (NIM -ve standard) 2+3 NIMCLKOUT = inverted ( Diag.14/U32 ) LK4 pins 1+2 # RODBUSYOUT = true (NIM -ve standard) 2+3 RODBUSYOUT = inverted ( Diag.14/SK14) LK1 pins 1+2 # RODBUSYOUT = TTL open/c, active low 2+3 RODBUSYOUT = NIM -ve standard ( Diag.14/SK13) LK91 pins 1+2 # NIMBUSYOUT = RODBUSYOUT ( NIM ) ***SEE PHOTO-5*** 2+3 NIMBUSYOUT = TIM Busy Out ( NIM ) ( Diag.15/U1 ) PL41 pins 1+2 ECLBUSYOUT = MEXTBUSYOUT ***SEE PHOTO-5*** 2+3 # ECLBUSYOUT = BUSYOUTB ( Diag.06/U60 ) PL122 pins 1+2 sets stand-alone, internal FER ***SEE PHOTO-6*** independent from ECR,& sets int.ECR=0 2+3 # sets stand-alone, internal FER = ECR ( Diag.13/U85 ) PL166 pins 1+2 # NTIMOUTEN is enabled only in the ***SEE PHOTO-4*** correct TIM slot ( by VME GA(4-0)* = 10010 ) 2+3++ NTIMOUTEN, which enables P3 b/plane outputs, is always enabled ( Diag.04/U55 ) PL118 pins 1+2 # selects standard JTAG loading ***SEE PHOTO-6*** 2+3 selects JTAGX for loading from VME 6) 4-pin Links : ***SEE PHOTO-5*** ------------- ( Diag.14/U17 ) LK7 pins 2+3 NIMEXTBUSYIN -> EXTRODBUSYIN 1+2 # NIMEXTBUSYIN -> NIMEXTBUSY & 3+4 # plus EXTRODBUSYIN = 0 /cont: - 5 - 7) NOTE 6: The following links are DIAGNOSTIC TEST POINTS ONLY, ======= with EVERY PIN "B" CONNECTED TO GND ==== DO NOT PUT ANY LINKS BETWEEN PINS "A" and "B" ! ==== ========================================================= ( Diag.02/U76 ) PL143 - PL162 FPGA-1 debug bus test points PL186 - PL201 FPGA-1 spare bus test points ( Diag.03/U67 ) PL124 - PL140 FPGA-2 debug bus test points ( Diag.12/U107 ) PL177, PL178, PL175 Input Clock test points ( Diag.15/U1+U4 ) PL2,7,16,25,30-32,50-52 TTC(x) test points 8) NOTE 7: The following TEST POINTS can be used to set-up ======= correct timing relationships ( Diag.02/U76 ) LK45 TIMCLK1L ( FPGA-1 ) LK46 VMECLK LK47 SIGCLK ( Diag.03/U67 ) LK48 TIMCLK2L ( FPGA-2 ) LK49 TTCCLK2L LK50 VMECLK ( Diag.04/U72 ) TP1 F1_CCLK ( PROM-1 ) ( Diag.04/U59 ) TP2 F2_CCLK ( PROM-2 ) ( Diag.11/U52 ) TP3 TIMCLK3L TP4 SPARECLK2 TP5 SPARECLK1 ( Diag.12/U54 ) PL117 MCLK1 ( BACKPLANE ) ( Diag.12/U98 ) PL172 TTCCLKB PL173 NTTCOUT(7) This version : MP-UCL, 23 Oct. 2008 Previous versions : 23 Oct. 2008 29 Sep. 2008 15 Sep. 2006