FPGA2: firmware version 12 (Timestamp: Thu Nov 10 14:59:43 2005)

These are the assignments for the debug pins located below FPGA2 (nearer
the center of the board - PL124-140). They first 8 also have LEDs (active low).

0 1 2 3 4 5 6 7 8 9 a b c d e f
. . . . . . . . . . . . . . . .  -- debug signal (0-15)
. . . . . . . . . . . . . . . .  -- gnd

* * * * * * * *                  -- LEDs
 

     0) clk_in (div 20M)  Clock input to FPGA2 (/20M for visibilty)
     1) clk    (div 20M)  Clock as used on FPGA2 (/20M for visibilty)
     2) rst_in*^          Reset signal into FPGA2 (from FPGA1)
     3) rst*^             Reset as used buy FPGA2
     4) tim_busy*^        TIM is stopping (non-TTC) Triggers
     5) alltrg_pre_fv*^   Trigger proir to being Fixed-Freq Vetoed
     6) ttc_l1a*^         L1A from TTCrx
     7) fftveto*          Fixed Frequency Veto Signal         
 (8:15) TTCbus(0:7)		  Backplane signals as sent from FPGA
                          	(prior to final FF only)

 TTCbus(0)   <= L1A/Trig;
 TTCbus(1)   <= ECR;
 TTCbus(2)   <= BCR;
 TTCbus(3)   <= CAL;
 TTCbus(4)   <= EXS;
 TTCbus(5)   <= TTS;
 TTCbus(6)   <= FER;
 TTCbus(7)   <= Spare;


(* inverted for leds)
(^ stretched for visibility)