Proton Calorimetry/Meetings/2020/08/05

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(Saad Shaikh)
 
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=== [[ELogs/SaadShaikh|Saad Shaikh]] ===
=== [[ELogs/SaadShaikh|Saad Shaikh]] ===
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*Working on FIFO interface between DDC232 data and UART transmitter.
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**Using Xilinx FIFO Generator IP but need to debug.
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*Then need to instantiate processor for DMA from FIFO.
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**[https://reference.digilentinc.com/learn/programmable-logic/tutorials/2020.1/getting-started-with-ipi Tutorial about Vivado IP integrator] should give details about processor instantiation and workflow with Vitis.
=== [[ELogs/RaffaellaRadogna|Raffaella Radogna]] ===
=== [[ELogs/RaffaellaRadogna|Raffaella Radogna]] ===

Latest revision as of 15:15, 10 August 2020

Contents

Minutes for UCL Proton Calorimetry Meetings, 5th August

Present

Simon Jolly, Saad Shaikh, Raffaella Radogna, Fern Pannell

Saad Shaikh

  • Working on FIFO interface between DDC232 data and UART transmitter.
    • Using Xilinx FIFO Generator IP but need to debug.
  • Then need to instantiate processor for DMA from FIFO.

Raffaella Radogna

  • Managed to simulate FPGA response for blinking LED tutorial
  • Now on the UART interface tutorial.
  • Started looking and running Saad's code
  • Had a meeting with the head of physics department at Sussex university
    • Sussex is happy to support fellowship applications for Royal society URF and also suggested to try STFC ERF
    • Need to understand with Ruben if UCL will support the URF application
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