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Helix Driver
2 Channel Prototype:
- VME wire-wrap board constructed.
- Contains registers that can be loaded via VME.
- Registers contain the HELIX setup data.
- Single VME cycle operation achieved by base address offset decoding in parallel with data transfer. Details here
- Setup data can be loaded into the registers and readback to check integrity.
- CLOCK, TRIGGER, NOT RESET, and TEST PULSE input from the MASTER.
- Output (LVDS to CAB) SERIAL DATA and LOAD pulse in addition to TRIGGER, RESET, TEST PULSE, and CLOCK.
- Mach5 CPLD implements VME interface and board logic.
- A16:D16 VME interface.
- LVDS (from MASTER) -> TTL
- TTL (board logic) -> LVDS.
- Also TTL -> ECL for use with existing test setup (in place of HP pattern generator.)
Status:
Working standalone, but untested with MASTER.
