ERROR (request reset) sequence
==============================

This is how we are implementing the ERROR (request reset) sequence
in the C&C. 

Definitions:

ERROR is an OR of the Error set by ADCM or CPU.
ADCM ERROR is  J2 bus Error signal  (latched in ADCM).
CPU  ERROR is VME command Error bit (latched in Master or Slave register).

Sequence:

* ERROR on
* wait for next trigger
* then BUSY on and hold  (the BUSY state is readable by VME register)
* if error recovery fails CPU issues Fatal Error to GFLT by VME command
* ERROR off
* issue notReset (to reset all Helix pipelines)
* issue BUSY off (to resume triggers)

Examples:

1. ADCM ERROR on then off.
2. CPU  ERROR on then off.
3. Suppose we want ERROR on from ADCM and ERROR off from CPU:
   * ADCM ERROR on
   * CPU  ERROR on
   * ADCM ERROR off (by VME command to ADCM or maybe
                     by RESET signal sent from C&C?)
   * CPU  ERROR off


John Lane   10 May 99

This file is   http://www.hep.ucl.ac.uk/~jbl/MVD/CnC_ErrSequence.txt