How Clock and Control sees an MVD DAQ run
=========================================

The following notes show the software actions for the Clock and Control.
The difference between GFLT mode and LOCAL mode runs is:

1. the Master control bit is either GFLT or LOCAL mode,
2. the clock and commands are Master generated for LOCAL mode.


Helix Interface run setup
-------------------------

* Receive SETUP command from MVD Run Control.
* Set each Helix Driver channel-delay registers (if any?).
* Set each Helix Driver TestPulse-mask register.
* Set each Helix Driver memory with Helix configuration data.
* Set each Helix Driver download-start bit.
* For each Helix Driver download-ended bit -- wait.
* Send SETUP completed to MVD Run Control.

Note: Helix notReset is asserted during the download period.


Slave run setup
---------------

* Receive SETUP command from MVD Run Control.
* Set each Slave control bit to Master mode.
* Send SETUP completed to MVD Run Control.


Master run setup
----------------

* Receive SETUP command from MVD Run Control.
* Set Master Slave-mask register.
* Set Master delay registers (if any?).
* Set Master control bit to GFLT or LOCAL mode.
* Send SETUP completed to MVD Run Control.

Note: does the BUSY signal matter during setup?


Master run active in LOCAL mode
-------------------------------

Note: before any triggers, a notReset command is issued to synchronize
      the Helix pipelines (in GFLT mode, this is generated from GFLT
      Initialize without any further software action on the Master).

      Does ADCM require a Reset or Initialize Accept from C+C ?

* Receive ACTIVATE command from MVD Run Control.
* Issue notReset VME command for Helix synchronization.
* Issue Trigger and Calibrate VME commands as necessary.
* Receive END or ABORT command from MVD Run Control.

Trigger   = Set required Readout Type in GFLT Control register.
            Set   Trigger bit in Master Command register.
            Clear Trigger bit in Master Command register.
            Wait for Accept bit to clear in Master State register.

Calibrate = Set required Readout Type in GFLT Control register.
            Set   Calibrate bit in Master Command register.
            Clear Calibrate bit in Master Command register.
            Wait for CalibBusy and Accept bits to clear
                                         in Master State register.

     Notes: 1. Calibrate command gives TestPulse followed by Trigger,
            2. we now think the Trigger and Calibrate VME commands
               will increment FLTN by hardware,
            3. the wait for the Accept bit guarantees no loss of trigger.

Note: external-signal-input and push-button triggers are also available.


John Lane   28 Apr 99

This file is   http://www.hep.ucl.ac.uk/~jbl/MVD/CnC_RunSequence.txt