Survey of SCT latency budget ============================ 22 Oct 99 (last budget change: 6 Jun 99; first version: 2 Dec 98) John Lane (UCL) email: jbl@hep.ucl.ac.uk Please see also http://www.hep.ucl.ac.uk/~jbl/SCT/SCT_latency.html Please let me know if anything should be changed. Summary ------- The latency is the time from the interaction until the L1A trigger signal is received by the front-end pipeline. We need to make sure that when the L1A arrives at the pipeline of ABC(D) the data is still there. The following table is a summary of latency budgets (the first column) up to the point of extracting data from the pipeline. The target for the total latency is 128 BC and we are working to reduce the total. The biggest uncertainty is the rack positions in USA15. BC CK Item Comment Source 56.1 CTP input Calorimeter Trigger (1402ns) L1 TDR p452 4 CTP Central Trigger Processor L1 TDR p452 17.8 reserved L1 Trigger unused contingency (445ns) Nick Ellis 77.9 BC so far: CTP output Nick Ellis 0.4 0 Fanout provisional item L1 TDR p442 1.6 0 8m cable nominal length L1 TDR p442 0.1 0 TTCvi interface module L1 TDR p442 0.1 0 .6m cable conservative L1 TDR p442 0.9 0 TTCvx transmitter module (cf TTC crate) Per Gallno 6.4 0 32m fibre conservative 40m (= 8+32) CTP to TTCrx Philippe Farthouat 3 TTCrx receiver chip Philippe Farthouat 90.4 BC so far: TTC output 2 1 TIM OK Martin Postranecky 0.2 0 Backplane OK Martin Postranecky 3 3 ROD OK Richard Jared 0.5 0 BOC card conservative Maurice Goodrick 2 1 BPM chip best estimate Roy Wastie 0 0 VCSEL opto-driver Tony Weidberg 19.4 0 97m fibre UNDER REVIEW (worst case ROD position) Tony Weidberg 0 0 Pin diode opto-receiver Tony Weidberg 1 0 DORIC conservative Tony Weidberg 7 7 ABC(D) conservative by 1 BC (includes CAFE) Alex Grillo 0 0 Detector time-of-flight and signal propagation Alex Grillo 6.5 reserved SCT contingency Alex Grillo ----- 132.0 BC total = pipeline length BC is latency budget in units of 25ns Bunch Crossing clock periods CK is discrete delay (flip-flop like) which is whole ClocK periods Level 1 Trigger latency budget ------------------------------ My understanding of the advertised 2.5us (100 BC) is (L1 TDR p452): BC ns 57.9 1447 CTP output: 60.1 BC uses 2.2 BC of L1 Trigger contingency 20.0 500 L1 Trigger contingency 3.1 78 TTC ) 16.0 400 80m fibre )= TTC latency budget 3.0 75 TTCrx ) ----- ---- 100.0 2500 L1 Trigger latency budget This defines the CTP output latency budget: BC ns 100.0 2500 L1A latency budget -22.1 -553 TTC latency budget ----- ---- 77.9 1947 CTP output latency budget ROD crate timing diagram to define latencies -------------------------------------------- A ROD crate is essentially a synchronous system in which propagation delays are irrelevant so long they are << 25 ns and setup and hold times are met. However, clock propagation delays should be accounted for on the backplane, and in the clock translators and buffers on BOC. The arrows below represent the period of latency for each component in a ROD crate and is demarcated by active clock edges while the L1A signal is asserted. Input and output (i/p & o/p) signals are at slot connector or chip. The encoded L1A signal, which is output from the ROD as a serial bit stream, is shown as an L1A signal for simplicity. Not to scale. Only relevant clock edges shown. TTCrx: -----> ---------- L1A o/p -- -- -- CLK o/p --^ TIM: <----- TIM -----> ---------- L1A o/p -- -- -- CLK o/p --^ ROD: ---> <--- Backplane ------------ L1A i/p ---- ---- -- -- CLK i/p --^ --^ BOC: <------- ROD -------> ---------- L1A i/p -- -- BPM: ---> <--- BOC ---------- L1A i/p -- -- -- CLK i/p --^ <----- BPM ----- Notes ----- o The ABC(D) pipeline length is 132 BC. o 40m is a conservative cable length from CTP fanout to ROD crate. The CTP racks are those in USA15 closest to the detector. o We may place the TTCvi and TTC crate near the ROD crates, although in the above table the L1 TDR value of 8m to TTCvi is used. o The short cable from TTCvi to TTC crate assumes neighbouring crates. o We may well use TTCvx modules instead of TTC crates because we only need a TTC fanout of about two. o Our fibre routing from the TTC crates is not optimal because, instead of going straight to the detector, we go away from the detector to the ROD crates and then back again. o The advertised 80m from detector to furthest crate in USA15 is for a limited number of fibres via a privileged route used by the trigger cables. o The 3 BC for the L1A serial bit stream is accounted for once only in the ABC(D) latency for command decoding. o The TIM latency includes the ROD setup time (it's associated with the last flip-flop on the TIM). o The L1A signal propagation time along the backplane depends on the distance to the ROD slot. o The clock arrives at the same time to all ROD slots. o The ROD latency includes the BPM chip setup time (it's associated with the last flip-flop on the ROD). o The BPM chip latency budget assumes the channel delay of clock and signal is set to zero. o The ABC(D) latency budget includes one clock period to allow for adjusting the phase of the clock with respect to the input signal. Email archive ------------- Email archive to support the latency budget table is at http://www.hep.ucl.ac.uk/~jbl/SCT/archive/SCT_latency_email.txt This file is http://www.hep.ucl.ac.uk/~jbl/SCT/SCT_latency.txt