TIM Implementation Model

November 22, 2000

Draft 0.2 by John Lane

Abstract

This document is a preliminary and incomplete draft of the TIM implementation model. Feedback is welcome.

Introduction

This document is a first attempt to describe the implementation model of the TIM, starting with the implementation of the requirements. It should be consistent with the interface specification documents [ref. TIM_interfaces] and should satisfy the requirements set out in the TIM requirements document [ref. TIM_requirements].

Implementation of the Requirements

Interface to ROD requirements

Output to ROD : sent by TTC bus from PLD6, event ID by PLD4a, PLD4b & PLD5
Front-end resets : from PLD2, PLD7 & PLD9
Busy from ROD : received by ROD-Busy lines to PLD8

Interface to BOC requirements

Clock distribution : TTCrx Clock40Des1 clock is sent to clock lines

Interface to TTC requirements

Input from TTC : received by TTCrx to PLD9
Latency of TTC commands : by TTCrx

Interface to CTP requirements

Busy to CTP : use standard Busy module
Busy from crate : by PLD8 (monitoring not implemented yet)

Interface to local trigger requirements

Command deadtime : by PLD2
Trigger latency : by PLD2
Trigger phase timing : PLD2 sends a prompt synchronized trigger output to the front panel

Interface to local processor requirements

VME interface : by PLD1
Configuration and monitoring : by registers in PLDs
Command execution : by PLD2 & PLD7
Interrupt generation : by PLD1 (not implemented yet)

Transmission of Clock and Control requirements

Clock source : by PLD2
Clock stability and jitter : TTCrx Clock40Des1 clock
Clock phase delay : by ROD Setup delay switch
Commands required : by PLD2, PLD7 & PLD9
Origin of commands : by PLD2, PLD3, PLD7 & PLD9
Latency of fast commands : by TTCrx
Queuing of event ID : FIFOs buffer up to 64 events

Additional requirements

Operating environment : design constraints

References

On the Web via:  ATLAS -> Inner Detector -> SCT -> Off Detector

TIM_requirements http://www.hep.ucl.ac.uk/~jbl/SCT/TIM_requirements.html
TIM_interfaces   http://www.hep.ucl.ac.uk/~jbl/SCT/TIM_interface_BOC.html
                 http://www.hep.ucl.ac.uk/~jbl/SCT/TIM_interface_ROD.html
                 http://www.hep.ucl.ac.uk/~jbl/SCT/TIM_interface_RCC.html

History:

0.1 26Jul00 JBL First draft
0.2 22Nov00 JBL Add References; update requirements list
    22Jun04 JBL Remove broken off-detector link

Last update: 22 June 2004 by John Lane (UCL) email: jbl@hep.ucl.ac.uk

http://www.hep.ucl.ac.uk/~jbl/SCT/TIM_model.html