CLOCK & COMMANND MASTER MODULE AND FAN-OUT MODULES FOR BEAM TEST 0 ================================================================== Draft Proposal -------------- MP - UCL, 25 March 1998 It has been found necessary to provide a module for the later stages of the ATLAS-STC FE Read Out System Tests and Beam Tests, in place of the eventual LHC-wide TTC System, which would allow the synchronisation of the required number of the MuSTARD and Oxford C+C modules to the same external Clock and Command signals. We propose to design and build a 6U-sized VME module to provide all the required signals ( as shown below ), capable of a stand-alone operation as well as of being synchronised to external sources ( eg. SEQSI or Test Beam electronics ). We also propose to design and build four separate 6U-sized C&C FANOUT cards, together capable of supporting the likely maximum of MuSTARD and Oxford C+C VME cards, needed for testing up to 60 FE modules. 1) Input & Output Signals : -------------------------------- A) Internal Hardware-generated signals are as follows : ---------------------------------------------------- - 40.08 MHz clock ( 50% M/S ratio,+/- 0.5nsec ) - "Level 1 Trigger" - single - repetitive with selectable variable average rate <150 kHz - repetitive with randomly spaced triggers - "Soft Reset" - repetitive at variable frequency < 50 Hz - "BC Reset" - repetitive about every 88.924 usec ( LHC beam crossing rate ) All these signals can be enabled/disabled via VME. B) The following commands can be issued via the VME : -------------------------------------------------- - "Level 1 Trigger" - "Soft Reset" - "BC Reset" - "Issue Calibration Pulse" - "Busy" ( see below ) C) The following external inputs will be provided : ------------------------------------------------ - Clock ( capable of accepting up to 45 MHz clock of varying M/S ratio ) - "Level 1 Trigger" - "Soft Reset" - "BC Reset" - "Issue Calibration Pulse" - "Busy" ( see below ) All these inputs can be enabled/disabled via VME. They will be provided in NIM standard ( plus diff. ECL for the clock ), apart from the "Busy" which is only differential ECL standard. /cont.: - 2 - D) The outputs provided are as follows : ------------------------------------- - Clock - Command Line ( see below ) - "Busy" ( see below ) The "Busy" output can be enabled/disabled via VME. They will be provided as differential ECL and NIM standards. 2) Proposed functionality : ---------------------------------- A) Any of the external or VME-generated Command signals received will be synchronised to whatever clock has been enabled via the VME. B) The external "Level 1 Trigger" input can be selected to be gated through a 'window' of variable width ( 1 - 25 nsec in 1nsec steps ), with its position/delay also variable ( 1 - 25 nsec in 1 nsec steps ), w/respect to the selected clock. All controlled via the VME. C) The "Level 1 Trigger" Command output can be delayed by a variable delay ( 0 -> 143 clks in 1 clk steps ), w/respect to the input command. Controlled via VME. D) The "Issue Calibration Pulse" command will be followed, after a variable delay [ 27 + ( 0 -> 143 )] clks, w/respect to the input command, by a "Level 1 Trigger" command. Controlled via VME. E) The "Busy" output will be the logical 'OR' of : a) "Busy" input ( itself the 'OR' of all the "Busy" inputs from all the MuSTARD modules ), b) the VME-generated "Busy" command, c) the internally generated "Busy" ( see below ) Any of these 3 sources can be enabled/disabled via VME, as can be the output signal. 3) Some other details of signals etc. : -------------------------------------------- A) The internal "Busy" lasts for the number of clock periods required by the various commands, and prevents any of these commands being accepted while it is asserted. - "Level 1 Trigger" 3 clocks - "Soft Reset" 7 clocks - "BC Reset" 7 clocks - "Issue Calibration Pulse" [ 27 + ( 0 -> 143 ) +3 ] clocks /cont.: - 3 - B) The command line will provide the following control commands strings, as specified by the current ABC(D) document: Field 1: 2: 3: 4: 5: ---------------------------------------------------------------------------- "Level 1 Trigger" 110 - - - - (3 clks) "Soft Reset" 101 0100 - - - (7 " ) "BC Reset" 101 0010 - - - (7 " ) "Isuue Calibr. Pulse" 101 0111 0000 1100 aaaaaa 110 000 (27 ") Note : a) fields 2 & 4 will be programmable from VME ------ to accommodate any further changes b) "aaaaaa" is a 6-bit chip address, MSB first 4) Front Panel input connectors : -------------------------------------- Clock NIM 1x Lemo Diff. ECL pair 1x Lemo ( 2-pin ) "Level 1 Trigger" NIM 1x Lemo "Soft Reset" NIM 1x Lemo "BC Reset" NIM 1x Lemo "Issue Calibration Pulse" NIM 1x Lemo "Busy" 4x 3 diff. ECL pairs on 4x 10-pin IDCs ( see below ) 5) Front Panel output connectors : ---------------------------------------- Clock 4x 1 diff. ECL pairs on 4x 10-pin IDCs NIM 1x Lemo Command Line 4x 1 diff. ECL pairs on 4x 10-pin IDCs NIM 1x Lemo "Busy" NIM 1x Lemo 6) Separate C&C FAN OUT cards : ------------------------------------ As shown in par. 5) and 6) above, the single C&C MASTER MODULE could support only 4 modules ( MuSTARD or Oxford C+C ). To provide the necessary fan out, we propose to build four simple C&C FANOUT cards. Each C&C FANOUT card will have seven output connectors ( 10-pin IDCs ) to support 3x MuSTARD units ( ie. 18x FE Modules ) and 4x Oxford C+C units ( ie. 16x FE Modules ), plus a single input ( 10-pin IDC ) linking it to the C&C MASTER MODULE. All 4x C&C FANOUT cards could thus support the possible maximum of 60x FE Modules. The C&C FANOUT cards will not be accessible to the VME, using connections to the backplane to provide only the required Vcc, Vee and GND supplies. All inputs and outputs are differential ECL.