SOME NOTES ON DESIGN AND FUNCTIONALITY OF THE --------------------------------------------- "CLOAC" ( C+C MASTER ) VME MODULE for the ATLAS-SCT System & Beam Tests ----------------------------------------------------------------------- D.A.Hayes, J.B.Lane, M.Postranecky University College London Version 1.3 15 November 2000 The "CLOAC" ( CLOck And Control ) MASTER Module has been designed and built for the later stages of the ATLAS-STC FE System Tests and Beam Tests, as a stand-in for the eventual LHC-wide TTC System, to allow the synchronisation of the required number of the "MuSTARD" and/or "Oxford C+C" modules to the same Clock and Command signals. As well as the master 40.08 MHz clock, available on the CLOCKOUT output, the "CLOAC MASTER" Module generates the ABC-specified command strings for the fast commands : "Level 1 Trigger", with its programmable delay, "Soft Reset" and "BC Reset" are broadcast to all the modules via the DATAOUT output. Also supported is the "Calibration Pulse" sequence, which includes automatic "Cal. trigger" after a programmable delay. Other slow commands can also be issued, up to 64-bit length only, but note that these are also broadcast to all DATAOUT outputs simultaneously. The various modes of operation are described below in detail. The "CLOAC MASTER" module is capable of a stand-alone operation as well as of being synchronised to external sources ( eg. "SEQSI" or Test Beam electronics ). Each "CLOAC MASTER" module can support up to four individual external modules ( any combination of "MuSTARD", "SLOG", and/or "Oxford C+C" modules, and/or "CLOAC FANOUT" cards ). We have also designed and built four separate 6U-sized "CLOAC FANOUT" cards, each capable of supporting up to three "MuSTARD" and up to four "Oxford C+C" modules. ABBREVIATIONS USED : BCRST : BC ( Beam Crossing ) Reset ==================== BURST : 'Burst' of a pre-set number of Triggers CAL : Calibration Test Pulse DLY : Delay EN : Enable EXT : External ( Input from NIM or IDC socket ) INT : Internal ( Hardware generated ) LD : Load OARST : Overall On-board Electronics Reset RP : Repetitive SLOCOM: Slow Command SRST : Soft Reset TRIG : Level 1 Trigger V : VME-generated command WIN : Window for External Input Trigger 1) Each "CLOAC MASTER" 6U-VME module has the following inputs and outputs : ======================================================================== A) Internal Hardware-generated signals are as follows : ---------------------------------------------------- 40.08 MHz clock ( 50% M/S ratio, +/- 5% ) Level 1 Trigger - single - repetitive with selectable frequency between 50 Hz - 600 kHz - repetitive with randomly spaced triggers with selectable average frequency between 12.5 Hz - 150 kHz Soft Reset - repetitive at selectable frequency between 0.005 Hz - 60 Hz BC Reset - repetitive about every 88.924 usec ( LHC beam crossing rate of 11.2456 kHz ) All these signals can be enabled/disabled via VME B) The following commands can be issued via the VME : -------------------------------------------------- Level 1 Trigger = VSINGLETRIG Soft Reset = VSRST BC Reset = VBCRST Calibration Pulse = VCAL Busy = VBUSY Overall Reset = VOARST Select "burst" mode = VBURST Slow Command = VSLOCOM C) The following external inputs are provided : -------------------------------------------- Clock ( ECL ) = ECL EXT CLK IN Clock ( NIM ) = NIM EXT CLK IN Level 1 Trigger = NIM EXT TRIG IN Soft Reset = NIM EXT SRST IN BC Reset = NIM EXT BCRST IN Calibration Pulse = NIM EXT CAL IN Busy Return 1 = EXTBUSY 1 Busy Return 2 = EXTBUSY 2 Busy Return 3 = EXTBUSY 3 Busy Return 4 = EXTBUSY 4 All these inputs can be enabled/disabled via VME These inputs are in NIM standard, plus differential ECL for the clock, apart from the "Busy" which is differential ECL standard only D) The outputs provided are as follows : ------------------------------------- Clock = CLKOUT Command String = DATAOUT Busy = BUSYOUT They are provided as both differential ECL and NIM standards, apart from "Busy", which is NIM only 2) FUNCTIONALITY : =============== A) All the "EXTernal" inputs are 'single' pulses ( not command strings ) B) Any of the external or VME-generated Command signals received are synchronised to the clock which has been enabled in Register 1 NOTE : For all commands, either the internal ENINTCLK ====== ( Register 0, Bit 0 ), or the external ENEXTCLK ( Register 0, Bit 6 ) must be asserted - the latter with a suitable external clock being input This is assumed in the descriptions below ----------------------------------------- C) When two or more commands arrive at the same time ( within about 5 nsec ), the priority selection will be as follows : - BC Reset - Soft Reset - Trigger - Calibrate NOTE : - Any "Soft Reset" or "BC Reset" commands received will ====== clear any "Triggers" still in the delay pipeline - Any "Calibrate" command received will clear any "Triggers" still in the delay pipeline D) To guarantee that all the VME-generated commands are executed at any time, all the internally and externally-generated commands should be disabled This ensures that the VME-generated command is not lost due to conflict with commands from any other source - as described in par. 2 C) above E) The timing of the DATAOUT w/respect to the CLKOUT leading ( raising ) edge, at the output sockets of this module, provides a minimum 5nsec SETUP time and a minimum 5nsec HOLD time NOTE : The 6-bit DIL-5 switch SW7 can be used for the ====== adjustments of the phase delay between the DATAOUT and CLKOUT leading ( +ve ) edge [ adjustment range +/- 15nsec in steps of 0.5 nsec ] [ at the "standard" setting ( = bit 6 = "ON" ), DATAOUT changes at about the trailing ( -ve ) CLKOUT clock edge ] NOTE : on the DIL-5, the switch lever marked "1" ====== ( between pins 1 and 12 of the DIL package ) is connected to the LSB of the 6-bit programmable delay line NOTE : Setting any switch lever to "ON" sets the relevant ====== bit to "0" Setting any switch lever to "OFF" sets that bit to "1" F) The "CLOAC MASTER" Module must be initialised by loading various registers, described in par.6 below, every time the "CLOAC" has been powered on. A sample setup program, written in C, is included in par. 11 G) The external "Level 1 Trigger" input can be selected to be gated through a 'window' of programmable width ( 1 - 25 nsec in 1 nsec steps, in Register 4, Bits 0 - 4 ), with its position/delay also programmable ( 1 - 25 nsec in 1 nsec steps, in Register 4, Bits 8 - 12 ) w/respect to the selected clock NOTE : This feature has not been fully implemented. ====== If you require it , please contact us first H) The "Level 1 Trigger" Command output can be delayed by a programmable delay ( Register 5, Bits 0 - 7 ), of [ 0 -> 143 ] clks in 1 clk steps, w/respect to the input command I) To issue a single trigger, assert VSINGLETRIG ( Register 1, Bit 0 ), and follow by reseting the VSINGLETRIG back to "0" J) Issuing the "Calibration Pulse" command VCAL will also automatically generate a single "Cal. Trigger" after the calibration sequence has ended This "Cal. Trigger" trigger can also be delayed, as described in the par. H) above, by the programmable delay ( Register 5, Bits 0 - 7 ), of [ 27 + ( 0 -> 143 ) ] clks, in steps of 1 clk, w/respect to the input command K) To enable internally generated repetitive triggers at selected frequency, select the required frequency from the table below ( see par.10 = APPENDIX A ) and set it to Register 3, Bits 0 - 4 Then set the ENINTPRTRIG ( Register 0, Bit 1 ) "high" L) To enable internally generated random triggers at selected average frequency, select the required average frequency from the table below ( see par.10 = APPENDIX B ) and set it to Register 3, Bits 0 - 4 Then set both the ENINTPRTRIG and ENRANDOMISER "high" ( Register 0, Bits 1 + 2 ) M) To enable internally generated repetitive SOFT RESETS at selected frequency, select the required frequency from the table below ( see par.10 = APPENDIX C ) and set it to Register 3, Bits 8 - 12 Then set the ENINTSRST ( Register 0, Bit 3 ) "high" N) To enable internally generated repetitive BC RESETS at about 11.2456 kHz, set the ENINTBCRST ( Register 0, Bit 4 ) "high" O) The VBURST function allows for issuing of a 'burst' of "Level 1 Triggers" ( from any internal or external sources ) and of "Calibration Pulses", with their automatic "cal. triggers". The number of triggers must be first pre-loaded into the Register 2 ( 16 bits, ie. 0 - 64k selectable ), using the following proceedure : a) Set VBURST ( Register 1, Bit 6 ) to "1" b) Write the required number of triggers ( 16 bits ) into Register 2 ( Bits 0 - 15 ) c) Load this number by command LDVBURST while keeping VBURST set ( Register 1, Bits 6 & 15 together ) and either : =========== d) Generate the triggers by either enabling the ENINTPRTRIG ( Register 0, Bit 1 ), with or without the ENRANDOMISER ( Register 0, Bit 1 + 2), or by allowing a sufficient number of External Triggers to reach the "CLOAC" burst counter by enabling the ENEXTTRIG ( Register 0, Bit 7 ) e) Repeat sequence a) & c) for repeated bursts of the same number of triggers or : ==== f) Generate CALIBRATION pulses, with their automatic "cal. triggers", by asserting the VCAL command while keeping the VBURST set ( Register 1, Bits 3 & 6 together) g) Repeat sequence a) & c) & f) for repeated bursts of the same number of "cal.triggers" P) "CLOAC" also has a basic provision for broadcasting any required "slow commands" to all the front ends from the "CLOAC MASTER", via the "CLOAC FANOUT" VME modules. The maximum length of any such "slow command" is 64 bits. The "slow command" string must first be pre-loaded into the Register 2, in four 16-bit words, using the following procedure : a) Write the first 16-bit word of the "slow command" to Register 2 ( 16 bits ) b) Load this by using the LDSLOCOM ( Register 1, Bit 13 ) c) Set LDSLOCOM back to "0" d) Repeat a) -> c) for the second, third and fourth 16-bit words of the "slow command" NOTE : All 64 bits must be written to, even if only "0"s are ====== loaded e) The above sequence can be aborted & internal counter reset by issuing the RSTSLOCNT ( Register 1, Bit 14 ) f) To issue the pre-loaded "slow command", assert the VSLOCOM ( Register 1, Bit 4 ) g) Set the VSLOCOM back to "0" NOTE : The whole of the a) -> g) procedure must be repeated ====== for every "slow command" NOTE : This "slow command" string will be broadcats to all ====== DATAOUT outputs of this "CLOAC" module, and hence to all modules directly connected to it 3) DEFINITIONS OF BUSYs : ====================== A) BUSYOUT output is the logical "OR" of the following signals : a) INTBUSY b) EXTBUSY c) VBUSY Any of these 3 sources can be enabled/disabled via VME The current state of the BUSYOUT signal on the NIM BUSY OUT output socket J10 is mirrored at the BUSY STATE Register 6 as Bit 6 B) INTBUSY : --------- a) INTBUSY is a continuously, internally-generated Busy signal, which prevents conflict between two or more commands received, from whatever source, at all times b) INTBUSY disables external inputs, internal generation or commands from VME during its period c) INTBUSY period is as follows : Trigger : 3 clocks Soft reset : 7 -"- BC Reset : 7 -"- Calibrate : [ 27 + ( 0 -> 143 ) + 3 ] clocks d) When one or more commands arrive during any INTBUSY period, they will be ignored e) When ENINTBUSY bit is asserted, it allows the INTBUSY signal through to the NIM BUSY OUT output socket J10 f) The current state of the INTBUSY is available at the BUSY STATE Register 6 as Bit 5 C) EXTBUSYs : ---------- a) When any ENEXTBUSY bit is asserted, it allows that EXTBUSY input signal, from IDC sockets J12 - J15, through to the NIM BUSY OUT output socket J10 b) When any ENEXTBUSY bit is asserted, that EXTBUSY signal will disable the internal generation of repetitive triggers ( ENINTRPTRIG ) and/or random frequency triggers ( ENRANDOMISER ), when enabled, during the time it remains asserted c) EXTBUSY signals have no effect on the receipt or operation of any EXTernal commands within the "CLOAC MASTER" Module d) EXTBUSY signals have no effect on the operation of any VME-generated commands on this module e) The current state of all the "OR-ed" enabled EXTBUSY inputs is available at the BUSY STATE Register 6 as Bit 4 D) VBUSY : ------- a) When VBUSY bit is asserted, the VBUSY signal goes through to the NIM BUSY OUT output socket J10 b) When VBUSY bit is asserted, it disables the internal generation of repetitive triggers ( ENINTRPTRIG ) and/or random frequency triggers ( ENRANDOMISER ), when enabled, during the time it remains asserted E) BURSTEND : ---------- a) When VBURST command is asserted ( Register 1, Bit 6 ), the BURSTEND busy ( Register 6, Bit 7 ) will be set "high" b) When the actual 'burst' of "Level 1 Triggers" or "Calibration Pulses" is being issued on the DATAOUT outputs, this BURSTEND busy will be set "low" for the duration of the 'burst' c) When the 'burst' has ended, the BURSTEND busy will be set "high" again until VBURST command is de-asserted 4) VME interface : =============== A) The "CLOAC MASTER" is a 6U, single width, A24/D16 slave VME module, with the base address A16 - A23 selectable by the 8-bit DIL-7 switch SW9 NOTE : on the DIL-7, the switch lever marked "1" ====== ( between pins 1 and 16 of the DIL package ) is connected to the address A16 NOTE : Setting any switch lever to "ON" sets the relevant ====== bit to "0" Setting any switch lever to "OFF" sets that bit to "1" B) Address Line A0 is always assumed to be ZERO, ie. no byte transfers - D16 transfers only No block transfers are allowed for C) Address lines A8 - A15 are not decoded or used on this module ( ie. the address space wraps around ) 5) POWER SUPPLY REQUIREMENTS : =========================== A) "CLOAC MASTER" requires +5V0 positive supply at 10 Amps and -5v2 negative supply at 5 Amps B) VME power connector JAUX is not soldered onto this module but supplied loose. If this module is used in CERN-standard VME crates which support the JAUX connector it is recommended that the -5V2 ( Vee ) supply is drawn via this connector ( use links PL1 and PL2 as shown below ) +5V ( Vcc ) supply : J1/32a, 32b, 32c ==================== J2/1b, 13b, 32b -5V2 ( Vee ) supply : one or more of the following backplane pins ===================== must be selected by inserting jumpers over link pins on PCB : J2/4c PL3 JAUX/ 9a+b+c PL1 J2/7a PL4 JAUX/10a+b+c PL2 J2/13a PL5 J2/19a PL6 J2/19c PL7 GND : J1/9a, 9c, 11a, 15a, 17a, 19a, 20b, 23b ===== J2/2b, 12b, 22b, 31b JAUX/1b, 2b, 3b, 3c, 4b, 5b, 6b 6) REGISTERS : =========== The "CLOAC MASTER" Module must be initialised by loading various registers every time the "CLOAC" has been powered on. A sample setup program, written in C, is included in par. 11 A) Register 0 : INPUTS / OUTPUTS ENABLE ======================================= Base Address + 00 VME read/write access --------------------------------------------- Bit 0 ENINTCLK enables internal CLOCK as master clock 1 ENINTRPTRIG enables internal repetitive TRIGGER at frequency selected in Register 3 2 ENRANDOMISER when set together with above Bit 2, enables repetitive, random TRIGGER, at randomly varying intervals, with average frequency selected in Register 3 3 ENINTSRST enables internal repetitive SOFT RESET at frequency selected in Register 3 4 ENINTBCRST enables internal repetitive BEAM CROSSING RESET every 88.924 usec = 11.2456 kHz 5 ENINTBUSY enables internally generated BUSY onto the NIM BUSY OUT output socket J10 6 ENEXTCLK enables external CLOCK input from NIM EXT CLK IN socket J7 and ECL EXT CLK IN socket J11 NOTE : only one input to be used at any time ====== - inputs are purely "OR-ed" 7 ENEXTTRIG enables external TRIGGER input from NIM EXT TRIG IN socket J3 8 ENEXTSRST enables external SOFT RESET input from NIM EXT SRST IN socket J4 9 ENEXTBCRST enables external BEAM CROSSING RESET input from NIM EXT BCRST IN socket J5 10 ENEXTCAL enables external CALIBRATE command input from NIM EXT CAL IN socket J6 11 ENEXTBUSY 1 } enables external EXTBUSY { J12 12 ENEXTBUSY 2 } returns from these IDC sockets { J13 13 ENEXTBUSY 3 } onto the NIM BUSY OUT { J14 14 ENEXTBUSY 4 } output socket J10 { J15 15 ENTRIGWIN enables external trigger input window selected in register 4 NOTE : 'Both', 'Either' or 'Neither' of "INT" or "EXT" enables ====== can be set for all commands ( apart from the CLK where 'Both' will result in internal clock being selected ) B) Register 1 : VME COMMANDS ============================ Base Address + 02 VME read/write access --------------------------------------------- Bit 0 VSINGLETRIG * writing "1" gives a single TRIGGER 1 VSRST * -"- SRST 2 VBCRST * -"- BCRST 3 VCAL * -"- CALIBRATE 4 VSLOCOM * -"- SLOW COMMAND 5 VOARST * -"- OARST 6 VBURST writing "1" enables the 'burst' mode 7 VBUSY BUSY input ( "1"= asserted, "0"= not asserted ) to the overall "OR-ed" BUSYOUT output on J10 8 LDTRIG * } { TRIGGER 9 LDSRST * } loads { SRST 10 LDBCRST * } COMMAND STRING { BCRST 11 LDCAL1 * } as set in Register 2 { CAL1 12 LDCAL2 * } { CAL2 13 LDSLOCOM * } { SLOCOM 14 RSTSLOCNT * resets internal SLOCOM register word counter 15 LDVBURST * } { BURST NOTE : * For each single command, write "1", followed by "0" ====== to clear the command C) Register 2 : COMMAND STRINGS =============================== Base Address + 04 VME write only access --------------------------------------------- The command strings contains the serial protocol for the ABC chip commands. Eg : Level 1 Trigger is the bit packet "110", and the first bit is ==== the LSB ( bit 0 ) of the string register, therefore we want to load the value of 3 "aaaaaa" is the 6-bit chip address TRIG = 3 bits ( Field 1 ) ( 110 = 0x0003 ) SRST = 7 bits ( Field 1 + 2 ) ( 101 0100 = 0x0015 ) BCRST = 7 bits ( Field 1 + 2 ) ( 101 0010 = 0x0025 ) CAL1 = 15 bits ( Field 1 + 2 + 3 ) ( 101 0111 0000 1100 = 0x1875 ) CAL2 = 12 bits ( Field 4 + 5 ) ( aaaaaa 110 000 = eg. 0x00c0 ) SLOCOM = 64 bits ( in 4 words of 16 bits ), each loaded sequentially by the LDSLOCOM | 'FAST' COMMAND STRINGS |'SLOW' COMMAND | BURST | | | STRING | COUNT | ---------|-------|------|-------|-------|--------|---|---|---|---|-------| | TRIG | SRST | BCRST | CAL1 | CAL2 | 1 | 2 | 3 | 4 | | ---------|-------|------|-------|-------|--------|---|---|---|---|-------| Bit 0 | 1 | 1 | 1 | 1 | a (MSB)| | | | | (LSB) | 1 1 0 0 0 a 2 0 1 1 1 a 3 - 0 0 0 a 4 - 1 0 0 a 5 - 0 1 1 a (LSB) 6 - 0 0 1 1 7 - - - 0 1 8 - - - 0 0 9 - - - 0 0 10 - - - 0 0 11 - - - 1 0 12 - - - 1 - 13 - - - 0 - 14 - - - 0 - 15 | - | - | - | - | - | | | | | (MSB) | ---------|-------|------|-------|-------|--------|---|---|---|---|-------| D) Register 3 : REPETITIVE FREQUENCY SELECT =========================================== Base Address + 06 VME read/write access --------------------------------------------- Bits 0 - 4 : EITHER Select INTRPTRIG FREQUENCY ------ ( 50 Hz to 600 kHz, selected from a table below - see Par.10, APPENDIX A ) OR Select INTVARTRIG ( Random Trigger ) at -- AVERAGE FREQUENCY ( 12.5 Hz to 150 kHz, selected from a table below - see Par.10, APPENDIX B ) Bits 8 - 12 : Select INTSRST FREQUENCY ( 0.005 Hz to 60 Hz, selected from a table below - see Par.10, APPENDIX C ) E) Register 4 : TRIGGER INPUT WINDOW SIZE AND DELAY SELECT ========================================================== Base Address + 08 VME read/write access --------------------------------------------- Bit 0 TRIGWINSIZE 0 ( LSB ) Selects window size between 1 1 0 -> 31 nsec in steps of 1 nsec 2 2 3 3 4 4 ( MSB ) 5 - 6 - 7 - 8 TRIGWINDLY 0 ( LSB ) Selects window delay between 9 1 0 -> 31 nsec in steps of 1 nsec 10 2 11 3 12 4 ( MSB ) 13 - 14 - 15 - F) Register 5 : TRIGGER DELAY SELECT ==================================== Base Address + 0A VME read/write access --------------------------------------------- Bit 0 TRIGDLY 0 ( LSB ) Selects TRIG delay between 1 1 0 -> 143 clock cycles 2 2 ( in steps of 1 clock ) 3 3 4 4 5 5 6 6 7 7 ( MSB ) G) Register 6 : BUSY STATE ========================== Base Address + 0C VME read only access -------------------------------------------- Bit 0 EXTBUSY 1 } { J12 1 EXTBUSY 2 } State of the EXTBUSY { J13 2 EXTBUSY 3 } inputs from sockets { J14 3 EXTBUSY 4 } { J15 4 EXTBUSY OUT "OR" of the four masked EXTBUSY inputs ( as set in Register 0 ) 5 INTBUSY state of the internally generated BUSY 6 BUSYOUT state of the overall "OR-ed" BUSYOUT at the NIM BUSY OUT output socket J10 7 BURSTEND "High" while VBURST enabled, goes "low" while the actual 'burst' of triggers is being output, re-asserts to "high" when the 'burst' finishes 7) CONNECTORS : ============ A) 10-pin IDC connectors : ------------------------------- NOTE : Pin 1 being the one with the "arrow" marker ====== ( whichever way up/down the connector is ) J12 FANOUTA ( on the front panel - upper ) ------------------------------------------------------ Pin 1 BUSYIN1(*) Pin 2 NBUSYIN1(*) Pin 3 - Pin 4 - Pin 5 - Pin 6 - Pin 7 CLKOUT1 Pin 8 NCLKOUT1 Pin 9 DATAOUT1 Pin 10 NDATAOUT1 J13 FANOUTB ( on the front panel - lower ) ------------------------------------------------------ Pin 1 BUSYIN2(*) Pin 2 NBUSYIN2(*) Pin 3 - Pin 4 - Pin 5 - Pin 6 - Pin 7 CLKOUT2 Pin 8 NCLKOUT2 Pin 9 DATAOUT2 Pin 10 NDATAOUT2 J14 FANOUTC ( on the PCB behind the front panel - upper ) ------------------------------------------------------------- Pin 1 BUSYIN3(*) Pin 2 NBUSYIN3(*) Pin 3 - Pin 4 - Pin 5 - Pin 6 - Pin 7 CLKOUT3 Pin 8 NCLKOUT3 Pin 9 DATAOUT3 Pin 10 NDATAOUT3 J15 FANOUTD ( on the PCB behind the front panel - lower ) ------------------------------------------------------------- Pin 1 BUSYIN4(*) Pin 2 NBUSYIN4(*) Pin 3 - Pin 4 - Pin 5 - Pin 6 - Pin 7 CLKOUT4 Pin 8 NCLKOUT4 Pin 9 DATAOUT4 Pin 10 NDATAOUT4 The 10-pin IDC connectors used for outputs of the CLKOUT and DATAOUT lines assume the same signal polarity as those on "MuSTARD" and "OXFORD C+C" VME modules All signals are differential ECL NOTE : (*) The BUSY inputs are received from MuSTARD ====== modules B) 10-pin IDC connector : ------------------------------ NOTE : Pin 1 being the one with the "arrow" marker ====== J16 JTAG INTERFACE ( on the PCB ) -------------------------------------- Pin 1 TCK Pin 2 GND Pin 3 TMS Pin 4 GND Pin 5 TDI Pin 6 Vcc Pin 7 TDO Pin 8 GND Pin 9 - Pin 10 - C) LEMO EPG.302 2-pin female : ----------------------------------- J11 ECLKIN ( on the front panel ) ------------------------------------------------------ Pin 1 ECLEXTCLKIN Pin 2 NECLEXTCLKIN D) LEMO EPC.00-size : ( all on the front panel ) ---------------------------------------------------------- J3 TRIN NIM EXT TRIG IN input J4 SRIN NIM EXT SRST IN input J5 BCRIN NIM EXT BCRST IN input J6 CALIN NIM EXT CAL IN input J7 CLKIN NIM EXT CLK IN input J8 CLKO NIM CLK OUT output J9 DATO NIM DATA OUT output J10 BUSO NIM BUSY OUT output D) VME BACPLANE CONNECTORS : ------------------------- VME backplane connectors J1 and J2 are assembled on this module VME power connector JAUX is not soldered onto this module but supplied loose. If this module is used in CERN-standard VME crates which support the JAUX connector it is recommended that the -5V2 ( Vee ) supply is drawn via this connector ( use links PL1 and PL2 as shown below ) 8) SWITCHES : ========== A) PUSH BUTTON switches on the front panel : ----------------------------------------- SW1 TRIG generates test trigger SW2 RST generates overall reset B) DIL LEVER SWITCHES on the PCB : ------------------------------- NOTE : on all the DIL switches, the switch lever marked "1" ====== ( next to pin 1 of the DIL package ) is connected to the LSB of the relevant word NOTE : Setting any switch lever to "ON" sets the relevant ====== bit to "0". Setting any switch lever to "OFF" sets that bit to "1" NOTE : The 6-bit DIL-5 switch SW7 can be used for the ====== adjustments of the phase delay between the DATAOUT and CLKOUT leading ( +ve ) edge [ adjustment range +/- 15nsec in steps of 0.5 nsec ] [ at the "standard" setting ( = bit 6 = "ON" ), DATAOUT changes at about the trailing ( -ve ) CLKOUT clock edge ] "standard" setting : ==================== SW3 6-bit DIL-1 sets CLK1 delay Bit 5 = "ON" SW4 6-bit DIL-2 sets CLK2 delay Bits 3+4+5 = "ON" SW5 6-bit DIL-3 sets CLK3 delay Bits 3+4+5 = "ON" SW6 6-bit DIL-4 sets CLK4 delay Bits 3+4+5 = "ON" SW7 6-bit DIL-5 sets CLK5 delay Bit 6 = "ON" SW8 8-bit DIL-6 sets trig.window compensation delays All bits = "ON" SW9 8-bit DIL-7 sets VME Base Address 9) LED INDICATORS : ================ There are 8 diagnostic LED indicators on this board, arranged in four pairs : DS1/34 Ye DTACK VME "DTACK" return DS1/12 Rd EXTB Masked and "OR-ed" EXTBUSY ( Reg. 6, Bit 4 ) DS2/34 Rd BUSO BUSYOUT line ( Reg. 6, Bit 6 ) DS2/12 Rd INTB INTBUSY line ( Reg. 6, Bit 5 ) DS3/34 Ye VERR VME "Error" Line DS3/12 Rd TRIG "Trigger" sequence output to DATAOUT DS4/34 Gr VEE -5V2 supply DS4/12 Gr VCC +5V supply LEDs DS1 - DS3 will flash "on" for about 60 msec for any single pulse, but will stay "on" if the relevant signal remains asserted 10) APPENDIX : ========== A) REPETITIVE TRIGGER FREQUENCY SELECT Table : ------------------------------------------- | Register 3 Bits : Trigger | ----------------- Frequency :| 0 1 2 3 4 -----------|--------------------------------------- 600 kHz | 0 0 0 0 0 300 0 1 0 0 0 200 1 1 0 0 0 150 0 0 1 0 0 120 1 0 1 0 0 100 0 1 1 0 0 50 kHz 1 1 1 0 0 60 kHz 0 0 0 1 0 30 0 1 0 1 0 20 1 1 0 1 0 15 0 0 1 1 0 12 1 0 1 1 0 10 0 1 1 1 0 5 kHz 1 1 1 1 0 6.0 kHz 0 0 0 0 1 3.0 0 1 0 0 1 2.0 1 1 0 0 1 1.5 0 0 1 0 1 1.2 1 0 1 0 1 1.0 0 1 1 0 1 0.5 kHz 1 1 1 0 1 0.60 kHz 0 0 0 1 1 0.30 0 1 0 1 1 0.20 1 1 0 1 1 0.15 0 0 1 1 1 0.12 1 0 1 1 1 0.10 0 1 1 1 1 0.05 kHz 1 1 1 1 1 B) RANDOM TRIGGER AVERAGE FREQUENCY SELECT Table : ----------------------------------------------- | Register 3 Bits : Trigger | ----------------- Frequency :| 0 1 2 3 4 -----------|--------------------------------------- 150 kHz | 0 0 0 0 0 75 0 1 0 0 0 50 1 1 0 0 0 37.5 0 0 1 0 0 30 1 0 1 0 0 25 0 1 1 0 0 12.5 kHz 1 1 1 0 0 15kHz 0 0 0 1 0 7.5 0 1 0 1 0 5 1 1 0 1 0 3.75 0 0 1 1 0 3 1 0 1 1 0 2.5 0 1 1 1 0 1.25 kHz 1 1 1 1 0 1.5 kHz 0 0 0 0 1 0.75 0 1 0 0 1 0.5 1 1 0 0 1 0.375 0 0 1 0 1 0.3 1 0 1 0 1 0.25 0 1 1 0 1 0.125 kHz 1 1 1 0 1 0.15 kHz 0 0 0 1 1 0.075 0 1 0 1 1 0.05 1 1 0 1 1 0.0375 0 0 1 1 1 0.03 1 0 1 1 1 0.025 0 1 1 1 1 0.00125 kHz 1 1 1 1 1 C) REPETITIVE SOFT RESET FREQUENCY SELECT Table : ------------------------------------------- | Register 3 Bits : SRST | ----------------- Frequency :| 8 9 10 11 12 -----------|---------------------------------------- 60 Hz | 0 0 0 0 0 30 0 1 0 0 0 20 1 1 0 0 0 15 0 0 1 0 0 12 1 0 1 0 0 10 0 1 1 0 0 5 Hz 1 1 1 0 0 6.0 Hz 0 0 0 1 0 3.0 0 1 0 1 0 2.0 1 1 0 1 0 1.5 0 0 1 1 0 1.2 1 0 1 1 0 1.0 0 1 1 1 0 0.5 Hz 1 1 1 1 0 0.60 Hz 0 0 0 0 1 0.30 0 1 0 0 1 0.20 1 1 0 0 1 0.15 0 0 1 0 1 0.12 1 0 1 0 1 0.10 0 1 1 0 1 0.05 Hz 1 1 1 0 1 0.06 Hz 0 0 0 1 1 0.03 0 1 0 1 1 0.02 1 1 0 1 1 0.015 0 0 1 1 1 0.012 1 0 1 1 1 0.010 0 1 1 1 1 0.005 Hz 1 1 1 1 1 11) SAMPLE SETUP PROGRAM : ====================== /* ---------------------------------------------------------------------------- * Dipsy board setup for the ATLAS SCT "CLOAC" ~jbl/vme/source/dipsy.c * * Author : J.B.Lane, UCL August 1998 JBL@hep.ucl.ac.uk * ---------------------------------------------------------------------------- * 22.Oct.98 Overall Reset and load a Slow Command added jbl * ---------------------------------------------------------------------------- */ #include int dipsy (void) ; volatile unsigned short *enable_register ; volatile unsigned short *command_register ; volatile unsigned short *string_register ; volatile unsigned short *frequency_register ; volatile unsigned short *window_register ; volatile unsigned short *delay_register ; volatile unsigned short *state_register ; /* The command strings contain the serial protocol for the ABC chip * commands. Eg Level 1 Trigger is the bit packet 110, and the first * bit is the LSB (bit 0) of the string register, therefore we want * to load a value of 3. aaaaaa is the 6 bit chip address. */ enum command_string { TRIG = 0x0003 /* 110 */ , SRST = 0x0015 /* 101 0100 */ , BCRST = 0x0025 /* 101 0010 */ , CAL1 = 0x1875 /* 101 0111 0000 1100 */ , CAL2 = 0x00c0 /* aaaaaa 110 000 */ , SLO1 = 0xe675 /* 101 0111 0011 0011 1 */ , SLO2 = 0xaaaa /* 0101 0101 0101 0101 */ , SLO3 = 0x5555 /* 1010 1010 1010 1010 */ , SLO4 = 0xeaaa /* 0101 0101 0101 0111 */ } ; enum command_load { LDTRIG = 0x0100 /* load Trigger string */ , LDSRST = 0x0200 /* load Soft Reset string */ , LDBCRST = 0x0400 /* load Bunch Crossing Reset string */ , LDCAL1 = 0x0800 /* load Issue Calibration Pulse string */ , LDCAL2 = 0x1000 /* load ditto part 2 */ } ; enum command_slow { VOARST = 0x0020, /* VME Overall Reset command */ LDSLOWCOM = 0x2000, /* load Slow Command 16-bit string */ RSTSLOWCOUNT = 0x4000 /* reset internal counter to load first 16 bits of Slow Command */ } ; int memtest (volatile unsigned int *memory_ptr) { enable_register = (unsigned short *) memory_ptr ; command_register = enable_register + 1 ; string_register = enable_register + 2 ; frequency_register = enable_register + 3 ; window_register = enable_register + 4 ; delay_register = enable_register + 5 ; state_register = enable_register + 6 ; if (memory_ptr == NULL) { printf ("Error mapping memory at address %p\n", memory_ptr) ; } else { dipsy () ; } return 0 ; } int dipsy () { /* Load the command strings and an arbitrary 64-bit slow command. * * Enable the internal clock before loading the serial command strings * and zero the command register before each load command: * these are required for correct loading of the command strings. */ *command_register = 0 ; *command_register = VOARST ; *command_register = 0 ; *enable_register = 1 ; /* ENINTCLK */ *frequency_register = 0 ; *window_register = 0 ; *delay_register = 0 ; *command_register = 0 ; *string_register = TRIG ; *command_register = LDTRIG ; *command_register = 0 ; *string_register = SRST ; *command_register = LDSRST ; *command_register = 0 ; *string_register = BCRST ; *command_register = LDBCRST ; *command_register = 0 ; *string_register = CAL1 ; *command_register = LDCAL1 ; *command_register = 0 ; *string_register = CAL2 ; *command_register = LDCAL2 ; *command_register = 0 ; *command_register = RSTSLOWCOUNT ; *command_register = 0 ; *string_register = SLO1 ; *command_register = LDSLOWCOM ; *command_register = 0 ; *string_register = SLO2 ; *command_register = LDSLOWCOM ; *command_register = 0 ; *string_register = SLO3 ; *command_register = LDSLOWCOM ; *command_register = 0 ; *string_register = SLO4 ; *command_register = LDSLOWCOM ; *command_register = 0 ; *string_register = 0 ; return 0 ; } 12) PLD1, PLD2, PLD3 : ================== Sample AMD "WinMachPro files, "pld.src", "pld.pi" and "pld.doc" ( pinout tables only ), used for programming the three MACH5 PLD devices on this version of "CLOAC", are attached to this note This version : MP-UCL, 15 Nov. 2000 Previous versions : 23 Nov. 1998 02 Nov. 1998 06 Sep. 1998 \--=-// ( o o ) -------------------------------------------------oOOO---(_)---OOOo---- | Martin Postranecky Tel: [00-44]-(0)171-419 3453 | | UNIVERSITY COLLEGE LONDON [00-44]-(0)171-387 7050 | |DEPT.OF PHYSICS AND ASTRONOMY Fax: [00-44]-(0)171-380 7145 | | High Energy Physics Group E-Mail: mp@hep.ucl.ac.uk | |Gower Street, LONDON, WC1E 6BT http://www.hep.ucl.ac.uk/ | ----------------------------------------------------------------------