BOC-ROD-TIM REVIEW (JULY 31 TO AUG. 1, 2000) SCT AND PIXEL OFF-DETECTOR WORKSHOP (AUG. 2, 2000) Place: LBNL Bldg.: 2, Conf. Rm.: 100B August 1, 2000, 15:30 to 15:50hrs TIM SCHEMATICS AND LAYOUT ------------------------- Martin Postranecky, UCL-PHYSICS-HEPP, London This paper takes a look at the TIM module as a system, describes the overall design, discusses some aspects of the electronics hardware of the TIM and the reasons behind the choice. Presentation Contents : ----------------------- - TIM Schematics representation - Components used - PLDs vs. Discrete - +5V vs. +3V - ECL vs. PECL - Power requirements - Reset - External Inputs & Outputs - Front Panel Layout & LEDs - Front Panel Interfaces - Backplane Interfaces - TIM Clocks - Stand Alone & Machine clock - Clocks Flow Schematics - Clocks Delays - TTC Fast Commands Flow - TIM PCB Layout - Overall Layout - PCB layers - PECL Clocks /cont: - 2 - TIM-SCH-01 : TIM Overall Schematics ====================================== http://www.hep.ucl.ac.uk/~mp/ROD_Review_TIM-SCH-01.pdf The first slide shows, again, the TIM FUNCTIONAL MODEL. It shows clearly the main blocks of TIM : - TTC INTERFACE with its TTCrx ASIC, producing all the timing, trigger and command signals received from the FLT while in the RUN MODE - STAND-ALONE generator of the same signals in the SA MODE. - STAND-ALONE SEQUENCER which allows long command sequences to be down-loaded from the host in the SA MODE - THE EVENT FIFOS AND SERIALISERS to allow IDs of multiple triggers to be stored and output sequentially - BACKPLANE MAPPING logic /cont: - 3 - TIM-SCH-02 : TIM Schematics 1 - STAND ALONE ============================================== http://www.hep.ucl.ac.uk/~mp/ROD_Review_TIM-SCH-02.pdf This slide shows the schematic representation of the circuitry of the STAND-ALONE generator, together with the suite of NIM and ECL inputs and outputs. Please note that the COLOUR chosen for this and the next two slides indicates REGISTERS ( GREEN ), logic on PLDs ( BLUE ), DISCRETE COMPONENTS ( WHITE ) and ECL/NIM BUFFERS ( ORANGE ). There is an 80MHz X-tal oscillator producing an internal 40MHz clock. Either this, or an externally generated 40MHz clock can be selected to provide the STAND-ALONE clock. The fast commands ( trigger and resets ) can be generated internally, either repetitively at a single selected frequency ( 50Hz - 600kHz ), with trigger also available as a random trigger with selected average frequency - or by VME commands from the host by writing to the COMMAND register. All the TTC-type commands, plus the 40MHz clock, can also be input from external sources in either NIM or ECL standard, using front panel connectors ( described later ). All the STAND-ALONE commands are synchronised to the selected clock and send to the BACKPLANE MAPPING logic to produce the TTC(0-7) output signals. In addition, the trigger command can be delayed by a fully programmable delay of up to 143 clock periods to accommodate the FE data pipeline length. There is a further capability of providing a "burst" of a fully-programmable ( between 0-16k ) number of either external or internal triggers or calibration triggers. The selection of any/all of the above externally input or internally generated signals is controlled by an VME accessed ENABLES register, allowing for a full flexibility. /cont: - 4 - TIM-SCH-03 : TIM Schematics 2 - RUN & INTERFACES =================================================== http://www.hep.ucl.ac.uk/~mp/ROD_Review_TIM-SCH-03.pdf This slide shows the BACKPLANE MAPPING, together with the backplane outputs synchronising drivers, the backplane PECL clock drivers, the two large FIFOs and serialisers for trigger L1ID, BCID and TTID data, plus the TTCrx receiver and interface. As you can see, three sets of signals from three sources - STAND-ALONE, TTC and SEQUENCER - are received by the MAPPING module. TIM-SCH-04 : TIM Schematics 3 - ID AND SEQUENCER / SINK ========================================================== http://www.hep.ucl.ac.uk/~mp/ROD_Review_TIM-SCH-04.pdf The final segments of the TIM are shown on this slide. The L1ID counter and register allows any FLT number to be down-loaded from the host interface in STAND-ALONE mode prior to issuing triggers. The FLTN counter will increment with each subsequent trigger, loading the new number into the FLTN register. In the RUN mode, this register is loaded from the TTC. Similarly, the BCID counter and register provides the suitably offset BCN for every trigger, in both STAND-ALONE and RUN modes. The BCNTIN register stores the BCN received from the TTC during run. Finally, the TTID is stored in in the TTYPE register. The SEQUENCER RAM can be loaded from the host with up to 32k long sequence of commands to allow for various tests of the system. There is an matching SINK RAM which allows us to store up to 32k of commands being issued by the TIM to RODs. Again, this will be invaluable in testing the hardware and timing. Finally, the basic ROD BUSY system receives ROD BUSY signals from all RODs in the crate and provides a masked-OR output to the FLT in either NIM or TTL standard ( selectable by a link ). It is intended to incorporate the active BUSY MODULE FPGA on TIM, if/when this is made available by CERN. /cont: - 5 - TIM-SCH-05 : TIM Components - Discrete vs. PLDs ================================================== http://www.hep.ucl.ac.uk/~mp/ROD_Review_TIM-SCH-05.pdf This slide shows the implementation of the various logic components in the electronics hardware. As a general policy, and to allow for the greatest possible flexibility of design, all of the logic circuitry has been incorporated on PLDs ( BLUE ). The only discrete components are those providing buffering for all inputs and all outputs ( ORANGE ), plus assorted active Delay Lines, Oscillators, RAMs and FIFOs ( WHITE ). To further add to the circuit flexibility, most PLDs are connected to four 8-bit wide "spare I/O" buses, plus assorted two 8-bit wide "spare" buses between individual PLDs. The selection of suitable PLDs has proved to be much more complicated than originally expected. Having specified the devices, on basis of the envisaged number of macro-cells, I/O pins and speed required, back in late 1999, we then discovered that there was a world shortage of these particular devices, with deliveries being quoted as 26 to 52 weeks! Similarly, the choice between +5v and +3V supply proved to be slightly academic, with none of the fast speed devices listed by manufacturers being actually available till the "end of 2000". Thus, to be sure of having any hardware available this year, we were forced to adopt a slightly more conservative approach than we may have chosen otherwise. Not shown on this slide is the distribution of the O/A RESET. We decided to provide a comprehensive reset of all devices on TIM, clearing all latches, registers, etc. on SWITCH-ON. The O/A RESET pulse can also be generated by the host via the COMMAND register, or by a front panel switch. It is therefore necessary to set-up the TIM module every time the O/A RESET has been used. /cont: - 6 - TIM-SCH-06 : Front Panel Interfaces & LEDs ============================================= http://www.hep.ucl.ac.uk/~mp/ROD_Review_TIM-SCH-06.pdf This slide show the standards adopted for the inputs and outputs of external clocks and commands. The NIM inputs and outputs are provided with LEMO 00 connectors, and ECL CLOCKS are input and output on two-pin LEMO 0B connectors. The complete set of six TTC(0-5) type commands, together with BUSY and CLOCK, is output on one half of dual 16-pin IDC connector as 8x differential ECL pairs. Same external commands can also be input on the second half of this IDC dual connector. This allows one TIM to operate as a master & drive another TIM slave. At least four TIM slaves can be driven by one TIM master using a daisy-chain ribbon cable and removing the ECL differential termination on the first three modules. Few words about the reasons for adopting the ECL and NIM standards for external inputs and outputs, requiring the additional -5V2 supply. As you may know, the CERN VMEbus Steering Committee recommended, in their paper "RECOMMENDED PRACTICES FOR THE USE OF VMEBUS IN PHYSICS APPLICATION", that differential ECL is the preferred method for front panel connectivity, and NIM for single-ended coaxial connections. It is also the case, that, for historical reasons, most of the off-the-shelf equipment available in CERN for eg. system tests uses NIM and differential ECL. For those reasons, and to make TIM as widely usable as possible, we have decided to retain the ECL and NIM standards as currently used by all the CLOAC modules. This required the provision of -5V2 supply. We have provided VXI-standard -5V2 power inputs on P2/J2 and JAUX connectors for use in CERN-standard VME crates, and additionally there is an on-board DC-DC converter providing -5V from +/-12V supplies. All the -5V2 input pins are selectable by individual links, allowing for full isolation from the backplane. The DC-DC converter is can also be disable by a single link. Thus the total -5V2 supplied circuitry, which is only used for tests with externally generated clock and commands, can be disabled. TIM-SCH-07 : Front Panel Layout ================================== http://www.hep.ucl.ac.uk/~mp/ROD_Review_TIM-SCH-07.pdf This sketch shows the layout of the front panel. As you can see, there is a set of 20x diagnostic LEDs and further 16x LEDs indicating the ROD BUSY states. Apart from that, the front panel is fairly full of connectors for external inputs and outputs. The TTC optical cable plugs directly into the TTC opto-receiver/pre-amplifier mounted on the daughter PCB directly behind the front panel. /cont: - 7 - TIM-SCH-08 : Backplane Interfaces ==================================== http://www.hep.ucl.ac.uk/~mp/ROD_Review_TIM-SCH-08.pd This slide shows the standards adopted for the backplane interface. The 40MHz clock is distributed to all BOC cards as 16 individual differential PECL pairs via the J3 backplane. The devices chosen for this task are the MOTOROLA MC100E111JC 1:9 PECL DIFFERENTIAL CLOCK DRIVERs, which guarantee channel-to-channel skew to be below 50 ps. Each line of the differential pair has a 270R load resistor at the transmitter, and is terminated by 100R between the differential pair at the BOC receiver end. The eight active-low TTC(0-7) outputs are bussed to RODs on two separate backplane buses, each for 8x RODs. The devices chosen, PHILIPS N74ABT574D, are Advanced BiCMOS Bus Interface drivers, which guarantees VOL of below 0.55V while sinking 64mA, and VOH of above 2V while sourcing 32mA. With TIM is slot 13 in the middle of the crate, the TTC(0-7)A bus is terminated on the backplane in slot 21, and the TTC(0-7)B bus in slot 5. Finally, the 16x ROD BUSY signals are received from individual RODs by PHILIPS N74LVT16244B LV Bus receivers. The active-low ROD BUSY lines are pulled up to +3V3 on the TIM, thus indicating empty ROD slots as NOT BUSY. /cont: - 8 - TIM-SCH-09 : TIM Clocks Flow & Delays ======================================== http://www.hep.ucl.ac.uk/~mp/ROD_Review_TIM-SCH-09.pdf This slide show the clock system of the TIM. In SA MODE, an 80MHz on-board crystal clock generator provides the required 40MHz INTERNAL CLOCK. There is a provision for accepting 40MHz EXTERNAL CLOCK in either NIM or differential ECL standard. Required clocks can be selected in the ENABLES register. When in the RUN MODE, the TTC supplies the machine clock via the TTCrx ASIC. There is a number of delay lines on TIM, allowing for independent adjustments of ROD SETUP ( for TTC outputs timing ), TTC SETUP ( of TTC clock delay ) and TIM SETUP ( of internal timings ). All these delay lines are set by DIL switches as 6-bits in 0.5 nsec steps, giving more than adequate coverage over the 25nsec clock. There is an additional delay adjustments available for the STAND-ALONE clock, set by the CLOCK DELAY register as 6-bits of 0.5nsec steps, which can be used to scan. There are four additional delay lines, used to provide a TRIGGER WINDOW width and delay, which can be used with to reject random triggers. /cont: - 9 - TIM-SCH-10 : TTC Fast Commands Flow ====================================== http://www.hep.ucl.ac.uk/~mp/ROD_Review_TIM-SCH-10.pdf This slide shows the paths taken by the FAST COMMANDS in both RUN MODE and all types of the SA MODE. The MAPPING module is used to select the appropriate source for the backplane TTC(0-7) outputs. TIM-SCH-11 : TIM PCB layout ============================== http://www.hep.ucl.ac.uk/~mp/ROD_Review_TIM-SCH-11.pdf And finally, the last slide shows the layout of the first TIM-0 prototype. The 9U board is a 10-layer PCB, with 6 track layers, two ground planes and 2 power planes - one +5V/Vcc and the other combined -5V2/Vee and +3V3 plane. The +/-12V used to generate the on-board -5V are input on two of the track planes. The most critical tracks are the differential PECL from the clock drivers to the P3 connector. They have been produced as 100R differential impedance equal length tracks. REFERENCES : 1) TIM LEB99 PAPER ============ --------------- http://www.hep.ucl.ac.uk/~mp/TIM+CLOAC_paper1.pdf 2) COMPLETE TIM-0 CIRCUIT SCHEMATICS AND PCB LAYOUTS ------------------------------------------------- http://www.hep.ucl.ac.uk/~mp/ ROD_Review_TIM0_all_diags-F_25-07-00.ps.zip This version : MP-UCL, 28 Jul. 2000 Previous versions : 27 Jul. 2000