SOME NOTES ON DESIGN AND FUNCTIONALITY OF THE --------------------------------------------- ZEUS-MVD C&C MASTER WIRE-WRAP PROTOTYPE FOR SUMMER 98 TEST ========================================================== Martin Postranecky, UCL, 27 July 1998 ------------------------------------- The main functions of the C&C MASTER WIRE-WRAP PROTOTYPE are 1) to generate the master 96nsec ( 10.4167 MHz ) square waveform clock and distribute it to the ADC Module as "RCLK1" and to the HELIX INTERFACE MODULE as "RCLK2" 2) to receive TRIGGER commands via VME register and to distribute them to the ADC Module as "ACCPT1" and to the HELIX INTERFACE MODULE as "TRIG2" 3) to receive CALIBRATE commands via VME register and to distribute them to the HELIX INTERFACE MODULE as "FCSTP", followed automatically by a suitably delayed CALIBRATION TRIGGER [ distributed as in par. 2) above ] 4) to receive from the ADC the "ERROR" ( = RESET REQUEST. ) and "BUSY" signals and decode them to produce the "BUSY", "ERROR" and "RESET" returns to VME register and "NOTRESET" to the HELIX INTERFACE MODULE A single Read/Write "COMMAND Register 0" is provided at the [ Base Address + 00 ] VME address to receive the commands as listed above A single Read-Only "STATE Register 1" is provided at the [ Base Address + 02 ] VME address for continuous access to output signals ( see below for details ) /cont: - 2 - FOR THE FOLLOWING NOTES, PLEASE REFER TO THESE DIAGRAMS : --------------------------------------------------------- ( if not included, please see www address : http://www.hep.ucl.ac.uk/zeus/mvd/candc.html#MASTERBOX and follow the "Prototype System" links ) * C&C MASTER WIRE-WRAP PROTOTYPE overall schematics diagram * State diagram for C&C MASTER WIRE-WRAP PROTOTYPE * Registers for C&C MASTER WIRE-WRAP PROTOTYPE 1) a) the C&C MASTER WIRE-WRAP PROTOTYPE is a wire wrap ( ie. double width ), 6U, VME card, with : J1 & J2 connectors, JAUX not used A24/D16 VME base address A16 - A23 selectable by DIL switch SW6 no block transfers +5V/5A and -5V2/2A supplies required ( see below for details ) b) it connects to the ADC via a single, front-edge, 10-pin IDC connector J11, with all signals being differential ECL pairs ( see below for details ) c) it connects to the HELIX INTERFACE MODULE via another single, front-edge, 10-pin IDC connector J12, with all signals again being differential ECL pairs ( see below for details ) NOTE : These output signals on J12 can be changed to LVDS ------ by replacing the TTL-ECL buffer U18 ( MC10124 ) by the drop-in TTL-LVDS adaptor hybrid, available from RAL d) there is a third, separate front-edge 10-pin IDC connector J13, which allows for "EXTTRIGGER" to be input, and which provides outputs of the "RCLK3" clock, "O/ALLBUSY" and "ACCPT3" , with all signals as differential ECL pairs e) finally, there is a single NIM output of the "RCLK3" clock on LEMO size 00 coax connector J14 f) the phases ( delays ) of all three clocks "RCLK1", RCLK2" and "RCLK3" are individually adjustable using three 6-bit-DIL switches SW1, SW2 and SW3, and the programmable Delay Lines DL1, DL2 and DL3 [ adjustment range is 0-63 nsec, with further ~63 nsec being available ( for a single output clock only ) by wiring-in the unused Delay Line 4 - but see the circuit diagram first ! ] [ standard setting = all signals ( apart from "FCSTP" ) change on the falling ( -ve ) edge of the relevant RCLK clock ] /cont: - 3 - g) the DIL switch SW5 and Delay Line DL5 allows for the adjustments of the phase delay between the "FCSTP" output to the HELIX INTERFACE MODULE and the "RCLK2" raising ( +ve ) edge [ adjustment range +/- 25nsec in steps of 1 nsec ] [ standard setting = "FCSTP" changes on the raising ( +ve ) "RCLK2" clock edge ] h) the DIL switch SW7 / bits 1-4 set the delay between the "FCSTP" signal and the automatic CALIBRATION TRIGGER signal following it [ adjustable between about 4.0 - 5.5 usec in steps of 1 clock period ] i) the DIL switch SW4 and Delay Line DL4 is not used [ but see par. f above ] j) the DIL switch SW6 sets the VME base address bits A16 - A23 k) on all the DIL switches, the switch lever marked "1" ( between pins 1 and 16 of the DIL package ) is connected to the LSB of the relevant word NOTE : Setting any switch lever to "ON" sets the relevant bit to "0" ====== Setting any switch lever to "OFF" sets that bit to "1" m) any TRIGGER command will generate "ACCPT1" and "ACCPT3" signals of about 10 usec duration ( this can be altered by re-programming the PLD-2 chip ), and "TRIG2" signal to the HELIX INTERFACE MODULE of 1 clock period duration [ but see par. n) and p) below ] n) if a second TRIGGER command arrives within this 10 usec period, it will be ignored o) for test purposes, a single ACCEPT can be generated by pressing switch SW8 p) by setting the "ENVAR_TRIG" bit in the command register to "1", the "ACCPT1" and "ACCPT3" outputs will mirror the duration of the trigger command received ( from either the command register, or from the "EXTTRIG" input on J13, or from test trigger switch SW8 ) NOTE : All these three trigger inputs are simply "OR-ed" ------ together q) the simple "state diagram" of the C&C MASTER shows the handling of the "BUSY" and "ERROR" ( RESET REQUEST ) signals ( received from ADC and/or from command register ) by the C&C MASTER WIRE-WRAP PROTOTYPE /cont: - 4 - r) the "BUSY_OUT" output is the "OR" of this on-board generated busy [ as described in par. q) above ], the "CALIBRATE_BUSY" signal [ as described in par. t) below ], and of the "BUSY" input signals from ADC and/or command register s) the "CALIBRATE" command generates a single "FCSTP" pulse, lasting for 1 clock period, which is sent to the HELIX INTERFACE MODULE. This is automatically followed by the CALIBRATION TRIGGER about 4.5 usec later [ but see par. h) above ] t) the "CALIBRATE_BUSY" output is asserted for the period between the start of the "FCSTP" pulse ( as sent to HELIX INTERFACE MODULE ) and the start of the automatic CALIBRATION TRIGGER following it u) all TRIGGER inputs are disabled while the "BUSY_OUT" or "CALIBRATE_OUT" outputs are asserted v) there is no priority hierarchy between "TRIGGER" and "CALIBRATE" commands, and they must not be issued at the same time. w) SWITCH-ON RESET is generated automatically when the +5V supply is restored. This lasts about 1 clock period and produces an over-all on-board RST reset pulse, together with a "NOTRESET" pulse sent to the HELIX INTERFACE MODULE. Same over-all reset and "NOTRESET" are also generated by the V_RST command, and/or by pressing switch SW9 NOTE : this generation of "NOTRESET" pulse from the on-board over-all ====== RST reset can be disabled by setting the DIL switch SW7 bit 8 to "ON" ( ie. "low" ) x) this over-all on-board RST reset pulse clears the command register, and resets/clears all commands previously set on this C&C MASTER WIRE-WRAP PROTOTYPE y) there are 10 diagnostic LED indicators on this board, arranged in five pairs : DS1/bottom gr +5V supply DS1/top gr -5V2 supply DS2 ye VME "DTACK" output DS2 ye VME "ERROR" input DS3 rd BUSY input DS3 rd ERROR input DS4 gr BUSY_OUT output DS4 gr ACCPT1 output DS5/bottom gr NOT_RESET output DS5/top gr CALIBRATE_BUSY output LEDs DS2 - DS5 will flash "on" for about 100 msec for any single pulse, but will stay "on" if the relevant signal remains asserted /cont: - 5 - 2) REGISTERS : =========== A) VME Address : [ Base address + 00 ] VME Commands ( VME read/write access ) ----------------------------------------- Bit 0 ( LSB ) V_TRIGGER # * generates "ACCPT1", "TRIG2", "ACCPT3" 1 V_ERROR + same function as "ERROR" from ADC 2 V_BUSY + same function as "BUSY" from ADC 3 VOT_RESET + generates "NOTRESET" sent to HELIX 4 V_CALIBRATE * generates a single "FCSTP" pulse 5 - 6 ENVAR_TRIG # + 7 V_RST * generates over-all on-board reset plus "NOTRESET" sent to HELIX NOTE : * these commands generate a SINGLE command by writing "1" to ------ the appropriate bit, and must be returned to "0" following each single command # see description in par. m) and p) above + These commands are asserted by writing "1" to the appropriate bit, and will remain asserted until "0" is written to that bit B) VME Address : [ Base Address + 02 ] Outputs ( VME read-only access ) ---------------------------------------- Bit 0 (LSB) ACCEPT mirrors "ACCPT1" 1 ERROR "OR-ed" and latched "ERROR" inputs 2 BUSY_OUT "OR-ed" and latched "BUSY" inputs 3 OT_RESET +ve going version of "NOTRESET" 4 CALIBRATE_BUSY [ see par. t) above ] 5 - 6 - 7 - /cont: - 6 - DESCRIPTION OF CONNECTORS : =========================== 1) FRONT-EDGE 10-pin IDC CONNECTORS : ---------------------------------- ( Pin 1 being the one with the "arrow" marker, whichever way up/down the connector is ) All signals are differential ECL pairs a) J11 to/from ADC : --------------------- Pin 1 BUSY in Pin 2 NBUSY in ( from ADC ) Pin 3 ERROR in Pin 4 NERROR in Pin 5 - Pin 6 - Pin 7 RCLK1 out Pin 8 NRCLK1 out ( to ADC ) Pin 9 ACCPT1 out Pin 10 NACCPT1 out b) J12 to HELIX INTERFACE MODULE : ----------------------------------- Pin 1 NOTRESET out Pin 2 NNOTRESET out Pin 3 FCSTP out Pin 4 NFCSTP out Pin 5 - Pin 6 - Pin 7 RCLK2 out Pin 8 NRCLK2 out Pin 9 TRIG2 out Pin 10 NTRIG2 out c) J13 EXTERNAL INPUTS / OUTPUTS : ----------------------------------- Pin 1 EXTBUSY out Pin 2 NEXTBUSY out Pin 3 EXTTRIG in Pin 4 NEXTTRIG in Pin 5 - Pin 6 - Pin 7 RCLK3 out Pin 8 NRCLK3 out Pin 9 ACCPT3 out Pin 10 NACCPT3 out 2) J14 LEMO 00-size coax : --------------------------- NIM "RCLK3" output /cont: - 7 - 3) VME BACKPLANE CONNECTORS : -------------------------- - J1 & J2 connectors - A24/D16 VME - base address A16 - A23 selectable by DIL switch SW6 - no block transfers +5V supply : J1/32a, 32b, 32c J2/1b, 13b, 32b -5V2 supply : one or more of the following pins : J2/4c, 7a, 13a, 19a, 19c ( selectable by jumpers on board ) GND : J1/9a, 9c, 11a, 15a, 17a, 19a, 20b, 23b J2/2b, 12b, 22b, 31b This version, MP-UCL : 27 Jul. 1998