BRIEF DESCRIPTION OF ZEUS-MVD C&C MASTER MODULE =============================================== D.A. Hayes, J.B. Lane, M. Postranecky, M. Warren University College London Version 1.4 DAH+JBL+MP+MW, 09 May 2001 Version 1.3 DAH+JBL+MP-UCL, 02 March 2000 Version 1.2 DAH+JBL+MP-UCL, 28 February 2000 Version 1.1 DAH+JBL+MP-UCL, 24 February 2000 Version 1.0 DAH+JBL+MP-UCL, 18 February 2000 Version 0.3 JBL+MP-UCL, 11 February 2000 Version 0.2 MP-UCL, 10 February 2000 Version 0.1 MP-UCL, 09 February 2000 This note should be read together the description of the C&C SLAVE, and also with the C&C MASTER schematics, register and state diagrams available from the following address : http://www.hep.ucl.ac.uk/zeus/mvd/candc.html#MASTERBOX The main functions of the C&C MASTER are to receive the standard GFLT information and pass them onto the C&C SLAVES, decode the trigger information to produce and send the "TRIG IN" and "FCS TP" signals to the HELIX INTERFACE MODULE, together with correctly timed 96 nsec "H_CLK", and to handle the "ERROR ( RESET REQ. )", "FATAL ERROR" and "BUSY" signals from the ADCs ( via the C&C SLAVES ) to produce "BUSY" and "FATAL ERROR" returns to the GFLT and "NOT RESET" to the HELIX INTERFACE MODULE. It allows a continuous VME read access to registers with all the relevant signals being received from the ADCs ( via the C&C SLAVES ) and sent back to the GFLT. Additionally, the C&C MASTER is able to operate in a stand-alone mode for test purposes, generating its own 96 nsec clock and able to accept all the relevant GFLT-type information and commands from the host via the VME. 1) Functional description of the C&C MASTER : ========================================== A) When first switched on, the C&C MASTER is reset to the "LOCAL MODE". To set it to the "GFLT MODE", Bit 0 of the MASTER COMMAND Register 3 should be set to "1". It is important to remember that the GFLT clock must be running prior to this ! The TEST STATE Register 5 may then be cleared by writing "0" to it via the VME. The C&C MASTER is then ready to be setup as required for a run. The C&C MASTER can operate either on its own, or as a system with up to maximum of five C+C SLAVES in either "GFLT" or "LOCAL" modes. But it is important to note that the C+C MASTER has no active communication with the special ADC crate J2 backplane other then via the C&C SLAVES. B) When set to the "GFLT MODE", the C&C MASTER receives the standard GFLT information on two IDC connectors J13 and J14. It latches this information into two GFLT NUMBER and GFLT CONTROL Registers 0 and 1, using the GFLT 96NSCK clock, which is input via the IDC connector J12 to a PLL smd IC. The GFLT clock is first delayed by an 8-bit delay DL1, set in 0.5 nsec steps by DIL switch SW3 to minimize the phase delay between the input and output of the PLL. This master clock is then further delayed by another 8-bit delay DL3, programmable in 0.5 nsec from FINE HCLK DELAY Register 9, catering for moving the H_CLK ( and A_CLK ) with respect to the machine clock. The H_CLK is then sent directly to the HELIX INTERFACE MODULE via IDC connectors J6A&B, and thence to the HELIX DRIVER modules. The same clock is also used to output the commands to the HELIX INTERFACE MODULE on the same connectors. The A_CLK, which is sent to the C&C SLAVES via five IDC connectors J7, J8A&B and J9A&B, and thence to the individual ADC modules, is further delayed by 8-bit delay DL2. This can be set in 0.5 nsec steps by DIL switch SW4 to compensate for the global phase delay between the A_CLK and H_CLK due to the different cable lengths. This clock is also used to output the GFLT data and commands to the ADC modules via the C&C SLAVES. There is a third clock, which is used for synchronising the CALIBRATION and TEST PULSEs sent to the HELIX INTERFACE MODULE as FCS TP. This can be delayed by the 8-bit delay DL4, which is programmable in 0.5 nsec steps from CALIB.TRIGGER DELAY Register 8. This allows for stepping of the FCS TP with respect to the H_CLK and TRIG_IN also being sent to the HELIX INTERFACE MODULE on the connectors J6A&B. The coarse delay between the TESTEN command and the following FCS TP is set in steps of 1 clk in the 16-bit TEST PULSE DELAY Register A. The coarse delay between the CALIBRATION command and the following TRIG_IN is set in steps of 1 clk in the first 6 bits of the CALIB.TRIGGER DELAY Register 8. C) The C&C MASTER decodes the information in GFLT CONTROL Register 1 to provide the correct type of TRIGGER, as described in the GFLT DESIGN DOCUMENT ( ZEUS Note 88-098, version 5.1 ) The value of TTYPE0 - 2, which should generate the TEST PULSE, must be pre-set on the switch SW9 to between 0 - 7. If link LK4 is inserted, the INIT. TRIGGER will generate a NOT RESET sent to the HELIX INTERFACE MODULE. This NOT RESET is ended by the next BCN0 received from the GFLT. The ACCEPT is sent to the C&C SLAVEs via the five IDC connectors and thence to the ADC modules as A_ACCEPT. This remains asserted until the ACCEPT is validated or ABORTed. TRIGGER is also sent to the HELIX INTERFACE MODULE as TRIG IN, which is asserted for 1 clock period. At the same time, the GFLT information, stored in the GFLT NUMBER and GFLT CONTROL Registers 0 and 1, is also sent to the ADC modules via the C&C SLAVEs as three consecutive words of 8 bits each, MDB(0)-(7), together with two control bits DA0 & 1, on the same five connectors J7, J8A&B and J9A&B : During the first clock cycle with A_ACCEPT asserted ( two control bits DA0 & 1 = 00 ) : "READOUT TYPE" word is sent During the second clock cycle with A_ACCEPT asserted ( two control bits DA0 & 1 = 01 ) : "FLTN" word is sent During the third clock cycle with A_ACCEPT asserted ( two control bits DA0 & 1 = 10 ) : "GBCN" word is sent When the control bits DA0 & 1 = 11 the data is invalid D) In the opposite direction, signals received by the C&C SLAVEs from the ADC modules are sent back, via the same ribbon cables and IDC connectors J7, J8A&B and J9A&B, to the C&C MASTER. There is a provision for a maximum of five C&C SLAVEs, A-E ( though only three are envisaged to be used normally ). The signals being sent back - BUSY, FATAL ERROR and ERROR ( RESET REQUEST ), are latched into the SLAVES STATE Register 6 in three groups of 5 bits each. SLAVE MASK Register 7 allows any of these signals to be masked off before being "OR-ed" to provide the MIXED BUSY, MIXED F_ERROR and MIXED ERROR (R/R) lines. When the C&C MASTER receives any non-masked ERROR (R/R), it asserts BUSY on the receipt of the next ACCEPT. This BUSY is held while the ERROR (R/R) is asserted. When it is de-asserted, the C&C MASTER generates a NOT_RESET command, lasting 1 clk period, and sends it to the HELIX INTERFACE MODULE. It then de-asserts the BUSY line. The MIXED ERROR (R/R) is output also on the front panel LEMO-00 connector J5 as a negative-going TTL signal, to be used as an "INTERRUPT" if required. The BUSY OUT, as sent back to the GFLT, is the "OR" of the above described BUSY, the MIXED BUSY from unmasked C&C SLAVEs, the internally- generated INT_BUSY which is asserted for 16 clk periods after each valid ACCEPT is received, the CAL_BUSY, the TESTBUSY when enabled, and the VME-generated VBUSY when set ( see below ). In the "GFLT MODE", this BUSY OUT mirrors exactly the M_BUSY ( Bit 3 of MASTER STATE Register 4 ). NOTE : In the "GFLT MODE", the BUSY OUT is asserted upon receipt ====== of the next ACCEPT. The BUSY OUT is always asserted when in the "LOCAL MODE". If the ENTESTBUSY ( Bit 14 of the MASTER COMMAND Register 3 ) is set, a TRIGGER will generate TESTBUSY as Bit 15 of the MASTER STATE Register 4. This is also "OR-ed" into the BUSY OUT to GFLT. It is cleared by asserting the CLRTESTBUSY ( Bit 15 of the MASTER COMMAND Register 3 ). The MIXED F_ERROR is "OR-ed" with the VME-generated VF_ERROR ( see below ) and the resulting F_ERROR OUT is stored in the COMPONENT CONTROL Register 2, together with the BUSY OUT and T_ERROR OUT ( see below ), and sent back to the GFLT via the IDC connector J11. Three other registers, the MASTER COMMAND Register 3, MASTER STATE Register 4 and the TEST STATE Register 5 can all be read in the "GFLT MODE", but would normally be used only for test purposes. But note that the Bit 12 of the MASTER STATE Register 4, LASTTRIGABORT, is set by an ACCEPT being ABORTed. It remains asserted until the arrival of the next ACCEPT, to indicate that the previous ACCEPT was aborted. E) When set to the "LOCAL MODE", the C&C MASTER operates with internal X-TAL clock, and will not accept any commands from the GFLT. The GFLT NUMBER Register 0 and the GFLT CONTROL Register 1 can be written to by the host via the VME interface. Thus both the FLTN and the GBCN numbers can be set to any required value ( valid GBCN between 0 and 219 ) in GFLT NUMBER Register 0. They will be validated by the next TRIGGER and can be then read back from the Register 0. The local 'FLTN' will be incremented by 1 on every subsequent TRIGGER ( including ABORTed triggers ), while the local 'GBCN' will be incremented to the value given by the local clock counter. If the READOUT TYPE etc. values in GFLT CONTROL Register 1 are set to their correct values, the selected TRIGGER will be generated upon asserting the ACCEPT bit. ( The INIT. TRIGGER generated NOT RESET will be reset by the local 'BCN0' from the local 'GBCN' counter ) Alternatively, the various commands available in the MASTER COMMAND Register 3 also allow the full operation of the C&C MASTER and/or the C&C SLAVES, as described above for the "GFLT MODE". Valid TRIGGER command can be generated by either setting the Bit 8 of the MASTER COMMAND Register 3 to produce a VTRIGGER, or by an external EXT_TRIG input ( as differential ECL ) on connector J10. For test purposes, a single TRIGGER can also be generated by pressing switch SW1. Note that these TRIGGER commands will normally generate A_ACCEPT of about 10 usec duration ( this could be altered by re-programming the PLD-4 chip ), and TRIG IN signal to the HELIX INTERFACE MODULE of 1 clk period duration. But if the ENVAR.TRIG ( Bit 7 in the MASTER COMMAND Register 3 ) is asserted, the A_ACCEPT will mirror the duration of the trigger command received from either the MASTER COMMAND Register 3, or from the EXT_TRIG input on connector J10, or from TRIGGER switch SW1. ( All these three trigger inputs are simply "OR-ed" together ) If the ENTESTBUSY ( Bit 14 of the MASTER COMMAND Register 3 ) is set, a TRIGGER will generate TESTBUSY as Bit 15 of the MASTER STATE Register 4. It is cleared by asserting the CLRTESTBUSY ( Bit 15 of the MASTER COMMAND Register 3 ). The actual C&C MASTER busy indicator, the M_BUSY ( Bit 3 of MASTER STATE Register 4 ) is the "OR" of the BUSY, the MIXED BUSY from unmasked C&C SLAVEs, the internally-generated INT_BUSY which is asserted for 16 clk periods after each valid ACCEPT is received, the CAL_BUSY, the TESTBUSY when enabled, and the VME-generated VBUSY when set. NOTE : The M_BUSY is asserted upon receipt of the next ACCEPT. ====== The VCALIBRATE command ( Bit 9 of the MASTER COMMAND Register 3 ) generates a single FCSTP pulse, lasting for 1 clock period, which is sent to the HELIX INTERFACE MODULE. This is automatically followed by the CALIBRATION TRIGGER after a delay set in CALIB.TRIGGER DELAY Register 8. The CAL_BUSY is asserted for the period between the start of the FCSTP sent to HELIX INTERFACE MODULE and the start of the automatic CAL.TRIGGER following it. All other TRIGGER inputs are disabled while the CAL_BUSY is asserted. SWITCH-ON RESET is generated automatically when the +5V supply is restored. This lasts about 1 clock period and produces an over-all on-board reset pulse ( together with a NOT_RESET pulse sent to the HELIX INTERFACE MODULE if link LK10 is inserted ). Same over-all reset is also generated by the VMOA RESET ( Bit 1 of the MASTER COMMAND Register 3 ) and/or by pressing switch SW2. NOTE : This over-all reset clears all the registers and sets ====== the C&C MASTER to the "LOCAL MODE". 2) The C&C MASTER has the following inputs and outputs : ===================================================== A) EXTERNAL INPUTS AND OUTPUTS ON THE FRONT PANEL : ------------------------------------------------ a) TTL signals : ( Normally HIGH, active LOW ) ------------- - CONNECTOR J4 ( Lemo 00 ) NEXT_ERRORIN INPUT external T_ERROR - CONNECTOR J5 ( Lemo 00 ) NERROROUTB OUTPUT ( totem-pole output ) masked and "OR-ed" ERROR(R/R) from all C&C SLAVE modules ( to be used as "INTERRUPT" ) b) Outputs to HELIX INTERFACE MODULE : --------------------------------- All ECL or LVDS differential pairs NOTE : Default is LVDS ------ To provide ECL replace the U6 and U19 by two MC10H124 TTL->ECL converter ICs and insert the two RN7 and RN11 8x390R ( 9-pin ) pull-down resistor networks - CONNECTOR J6/A ( 10-way IDC ) pin A1 NOT_RESET A2 NNOT_RESET A3 FCS TP A4 NFCS TP A5 - A6 - A7 CLK_5 A8 NCLK_5 A9 TRIG_IN A10 NTRIG_IN - CONNECTOR J6/B ( 10-way IDC ) pins B1-B10 same as above J6/A c) Connections to/from C&C SLAVE modules : --------------------------------------- All ECL differential pairs - CONNECTOR J7 ( 34-way IDC ) pin 1 BUSY 2 NBUSY 3 ERROR(R/R) 4 NERROR(R/R) 5 F_ERROR 6 NF_ERROR 7 A_ABORT 8 NA_ABORT 9 A_ACCEPT 10 NA_ACCEPT 11 A_RESET 12 NA_RESET 13 MDB(0) 14 NMDB(0) 15 MDB(1) 16 NMDB(1) 17 MDB(2) 18 NMDB(2) 19 MDB(3) 20 NMDB(3) 21 MDB(4) 22 NMDB(4) 23 MDB(5) 24 NMDB(5) 25 MDB(6) 26 NMDB(6) 27 MDB(7) 28 NMDB(7) 29 DA(0) 30 NDA(0) 31 DA(1) 32 NDA(1) 33 CLK_4 34 NCLK_4 - CONNECTOR J8/A ( 34-way IDC ) pins A1-A34 same as above J7 - CONNECTOR J8/B ( 34-way IDC ) pins B1-B34 same as above J7 - CONNECTOR J9/A ( 34-way IDC ) pins A1-A34 same as above J7 - CONNECTOR J9/B ( 34-way IDC ) pins B1-B34 same as above J7 d) standard GFLT connections : --------------------------- as described in the GFLT DESIGN DOCUMENT ( ZEUS Note 88-098, version 5.1 ) All ECL differential pairs - CONNECTOR J11 ( 34-way IDC ) : COMPONENT CONTROL CABLE PO.1 OUTPUTS TO GFLT pin 7 BUSY ( see BUSY OUT below ) 8 NBUSY 9 FERR ( see F_ERROR OUT below ) 10 NFERR 11 TERR ( see T_ERROR OUT below ) 12 NTERR 33 TMARK ( set to CLK4 = A_CLK ) 34 NTMARK - CONNECTOR J12 ( 34-way IDC ) : GFLT CLOCK CABLE PO.5 INPUTS FROM GFLT pin 9 CLOCK ( "96NSCK" ) 10 NCLOCK 11 BCN0 ( not used ) 12 NBCN0 13 PEMPTYB ( not used ) 14 NPEMPTYB 15 EEMPTYB ( not used ) 16 NEEMPTYB - CONNECTOR J13 ( 34-way IDC ) : GFLT CONTROL CABLE PO.4 INPUTS FROM GFLT pin 3 TESTEN 4 NTESTEN 5 TTYPE0 6 NTTYPE0 7 TTYPE1 8 NTTYPE1 9 TTYPE2 10 NTTYPE2 11 ROSYS0 12 NROSYS0 13 ROSYS1 14 NROSYS1 15 ROAMB0 16 NROAMB0 17 ROAMB1 18 NROAMB1 19 ROUSR0 20 NROUSR0 21 ROUSR1 22 NROUSR1 23 ROUSR2 24 NROUSR2 25 ABRTFLG 26 NABRTFLG 27 ACCPTFLG 28 NACCPTFLG - CONNECTOR J14 ( 34-way IDC ) : GFLT NUMBER CABLE PO.5 INPUTS FROM GFLT pin 1 FLTN0 2 NFLTN0 3 FLTN1 4 NFLTN1 5 FLTN2 6 NFLTN2 7 FLTN3 8 NFLTN3 9 FLTN4 10 NFLTN4 11 FLTN5 12 NFLTN5 13 FLTN6 14 NFLTN6 15 FLTN7 16 NFLTN7 17 GBCN0 18 NGBCN0 19 GBCN1 20 NGBCN1 21 GBCN2 22 NGBCN2 23 GBCN3 24 NGBCN3 25 GBCN4 26 NGBCN4 27 GBCN5 28 NGBCN5 29 GBCN6 30 NGBCN6 31 GBCN7 32 NGBCN7 e) Other ECL Differential Test Inputs/Outputs : -------------------------------------------- - CONNECTOR J10 ( 10-way IDC ) pin 1 CLKOUT OUTPUT A_CLK 2 NCLKOUT 3 EXT_TRIG INPUT to produce TRIGGER 4 NEXT_TRIG 5 BUSYB OUTPUT 6 NBUSYB 7 EXT_ERROR INPUT to produce T_ERROR OUT 8 NEXT_ERROR 9 ERROROUT OUTPUT } mixed & masked 10 NERROROUT } ERROR (R/R)="INTERRUPT" B) OTHER CONNECTORS : ------------------ a) VME Backplane Connectors : -------------------------- - CONNECTOR J1 ( standard 3x32-pin DIN41612 PCB connector ) Standard VME connections - CONNECTOR J2 ( standard 3x32-pin DIN41612 PCB connector ) A B C 1 -5V2 VME +5V -5V2 2 -5V2 VME GND -5V2 3 -5V2 (VME) - -5V2 4 VME A24 5 VME A25 6 VME A26 7 VME A27 8 VME A28 9 VME A29 10 VME A30 11 VME A31 12 VME GND NBP_EMPTY 13 GND VME +5V GND 14 GND (VME) GND 15 GND (VME) GND 16 (VME) 17 (VME) NBP_BUSY 18 (VME) NBP_F_ERROR 19 (VME) NBP_ERROR 20 (VME) NBP_RESET 21 (VME) BP_ABORT 22 VME GND BP_ACCEPT 23 (VME) - .. .. 31 VME GND 32 VME +5V NOTE : some VXI-standard -5V2 pins can be connected ====== by links on PCB for test use in non-ADC crate ONLY - see circuit diagram - CONNECTOR J3 not used - CONNECTOR JAUX not used NOTE : CERN-standard GND and -5V2 pins can be connected ====== by links on PCB for test use in non-ADC crate ONLY - see circuit diagram b) J-TAG interface to PLDs : ------------------------- - CONNECTOR J15 ( 10-way IDC header on PCB ) standard JTAG-ISP-PORT connections for programming on-board PLDs 3) The C&C MASTER can generate the following signals : =================================================== A) INTERNAL HARDWARE-GENERATED SIGNALS : ------------------------------------- 10.4165 MHz CLOCK ( 50 % m/s ratio, +/- 5% ) B) FRONT PANEL SWITCH-GENERATED SIGNALS : -------------------------------------- - SWITCH SW1 Push to generate a single TRIGGER - SWITCH SW2 Push to generate a single OVERALL RESET C) VME REGISTERS-GENERATED SIGNALS : --------------------------------- see below for the complete list of registers 4) Registers on the C&C MASTER : ============================= The C&C MASTER can operate in either "LOCAL" or "GFLT" modes In "LOCAL MODE", several registers have WRITE access from the host via VME interface, while all have READ access via VME In "GFLT MODE", some registers have WRITE access from the GFLT, some have WRITE access from the host via VME interface, while all have READ access via VME A) Register 0 : GFLT NUMBER ============================= Base Address + 00 VME WRITE in "LOCAL MODE" ----------------- GFLT WRITE in "GFLT MODE" Bits 0-7: FLTN 0-7 In "LOCAL MODE", the host can write in the FLTN of the next ACCEPT via the VME interface It can be read back by the host after the first ACCEPT has been issued The FLTN will increment by 1 on every subsequent ACCEPT ( including ABORTed triggers ) Bits 8-15: GBCN 0-7 In "LOCAL MODE", the host can write in the GBCN of the next clock via the VME interface It is then incremented by the stand-alone clock until the first ACCEPT, when its value for that ACCEPT can be read back by the host The register value will increment to the value of GBCN, based on stand-alone clock, of every subsequent ACCEPT Valid GBCN is in the range 0-219 B) Register 1 : GFLT CONTROL ============================== Base Address + 02 VME WRITE in "LOCAL MODE" ----------------- GFLT WRITE in "GFLT MODE" Bit 0 - 1 TESTEN In "LOCAL MODE", the host can write in the 2 TTYPE0 values of this register and read them back 3 TTYPE1 immediately 4 TTYPE2 5 ROSYS0 NOTE : 1) The value of TTYPE0-2 required 6 ROSYS1 ====== for TEST PULSE generation must 7 ROAMB0 be set on switch SW9 8 ROAMB1 ( see below for more details ) 9 ROUSR0 10 ROUSR1 2) The Register bits 5-11 must be 11 ROUSR2 set to correct value to produce 12 ABORT a trigger when setting ACCEPT 13 ACCEPT 14 - 15 - C) Register 2 : COMPONENT CONTROL =================================== Base Address + 04 VME READ ONLY ----------------- Bit 0 - - - 3 BUSY OUT # } 4 F_ERROR OUT # } state of returns to GFLT 5 T_ERROR OUT # } - - 9 BP_EMPTY } 10 BP_BUSY } 11 BP_F_ERROR } 12 BP_ERROR } state of the special J2 backplane signals 13 BP_RESET } in the ADC crate the C&C MASTER is situated 14 BP_ABORT } ( "1" = asserted ) 15 BP_ACCEPT } NOTE : # BUSY OUT is the "OR" of the following signals : ====== INT_BUSY, which will be asserted for 16 clks = 1.5 usec after each valid ACCEPT TESTBUSY when enabled, VBUSY, CAL_BUSY, "OR-ed" masked BUSY(A)-(E) returns and the BUSY generated upon receipt of ERROR (R/R) The BUSY OUT to GFLT is asserted upon receipt of the next ACCEPT in "GFLT MODE". It is always asserted when in the "LOCAL MODE" F_ERROR OUT is the "OR" of all masked F_ERROR(A)-(E) returns from C&C SLAVEs and of the VF_ERROR T_ERROR OUT is selected by link PL4 to be either value of VT_ERROR, "OR-ed" with two externally- -input signals : NEXT_ERROR IN ( TTL ) and EXT_ERROR ( differential ECL), or set permanently low = GND ( see below for more details ) D) Register 3 : MASTER COMMAND ================================ Base Address + 06 VME WRITE/READ ----------------- Bit 0 GFLT/LOCAL MODE "LOCAL MODE"="0" ( default ), "GFLT MODE"="1" 1 VMOA RESET * writing "1" gives a single OVERALL RESET 2 - 3 VBUSY BUSY "1" = asserted 4 VF_ERROR F_ERROR -"- 5 VT_ERROR T_ERROR -"- 6 VERROR ( R/R ) ERROR (R/R ) -"- 7 ENVAR.TRIG writing "1" enables A_ACCEPT to mirror Bit 8 8 VTRIGGER * writing "1" gives a single A_ACCEPT, lasting ~10 usec ( unless bit 7 is asserted ) and a single TRIG IN lasting 1 clk period 9 VCALIBRATE * writing "1" gives a single FCS TP pulse, followed by a single CAL.TRIGGER after a delay set in Register 8 10 VH_RESET H_RESET "1" = NOT_RESET asserted 11 VA_RESET A_RESET "1" = "ADC RESET" asserted 12 - 13 - 14 ENTESTBUSY writing "1" enables TESTBUSY 15 CLRTESTBUSY * writing "1" clears TESTBUSY NOTE : * For each single command, write "1", followed ====== by "0" to clear the command E) Register 4 : MASTER STATE ============================== Base Address + 08 VME READ ONLY ----------------- Bit 0 LOCAL MODE set when C&C MASTER is set to "LOCAL MODE" 1 GFLT MODE set when C&C MASTER is set to "GFLT MODE" 2 - 3 M_BUSY # the actual C&C MASTER busy indicator 4 A_CLK ON set while clock sent to C&C SLAVEs is running 5 H_CLK ON set while clock sent to HELIX INTERFACE MODULE is running 6 ERROR (R/R) OUT set while the "OR-ed" and masked ERROR (R/R) ( used as "INTERRUPT" ), received from any C&C SLAVEs, is asserted 7 - 8 TRIG IN set while TRIG IN is sent to HELIX INTERFACE 9 FCS TP set while FCS TP is sent to HELIX INTERFACE 10 H_RESET set while H_RESET is sent to HELIX INTERFACE 11 A_RESET set while A_RESET is sent to C&C SLAVEs 12 LASTTRIGABORT set when the previous ACCEPT was aborted 13 A_ACCEPT set while A_ACCEPT is sent to C&C SLAVEs 14 CALIB.BUSY set while CALIBRATION sequence is running 15 TESTBUSY set while TESTBUSY is asserted NOTE : # M_BUSY is the "OR" of the following signals : ====== INT_BUSY, which will be asserted for 16 clks = 1.5 usec after each valid ACCEPT TESTBUSY when enabled, VBUSY, CAL_BUSY, "OR-ed" masked BUSY(A)-(E) returns and the BUSY generated upon receipt of ERROR (R/R). It is asserted upon receipt of the next ACCEPT. F) Register 5 : TEST STATE ============================ Base Address + 0A VME READ ONLY ----------------- RESET BY VME WRITE Bit 0 - - - 4 A_CLK FAULT set by failure of A_CLK sent to C&C SLAVEs 5 H_CLK FAULT set by failure of H_CLK sent to HELIX INTERFACE 6 PLL FAULT set by the PLL losing lock ( BUT SEE NOTE 2 ) 7 - -------------- 8 TRIG IN set by TRIGGER sent to HELIX INTERFACE 9 FCS TP set by FCS TP sent to HELIX INTERFACE 10 H_RESET set by H_RESET sent to HELIX INTERFACE 11 A_RESET set by A_RESET sent to C&C SLAVEs 12 A_ABORT set by A_ABORT sent to C&C SLAVEs 13 A_ACCEPT set by A_ACCEPT sent to C&C SLAVEs 14 - 15 - NOTE : 1) All bits will remain set until reset ====== by writing "0" to this Register 5 2) PLL FAULT set does not necessarily mean the phase-lock has been lost. Due to the PLL IC used, the PLL FAULT may get set even if the part is locked. Therefore this indicator should be used for evaluation or passive monitoring only ! G) Register 6 : SLAVES STATE ============================== Base Address + 0C VME READ ONLY ----------------- Bits 0- 4 : BUSY(A)-(E) BUSY from the 5x C&C SLAVEs (A)-(E) Bits 5- 9 : ERROR(R/R)(A)-(E) ERROR(R/R)from the 5x C&C SLAVEs (A)-(E) Bits 10-14 : F_ERROR(A)-(E) F_ERROR from the 5x C&C SLAVEs (A)-(E) H) Register 7 : SLAVE MASK ============================= Base Address + 0E VME WRITE/READ ----------------- Bits 0- 4 : BUSYMASK(A)-(E) mask for the 5x BUSY(A)-(E) inputs Bits 5- 9 : ERRMASK(A)-(E) mask for the 5x ERROR(R/R)(A)-(E) inputs Bits 10-14 : F_ERRMASK(A)-(E) mask for the 5x F_ERROR(A)-(E) inputs I) Register 8 : CALIBRATION TRIGGER COARSE & FINE DELAY ========================================================= TEST PULSE FINE DELAY ===================== Base Address + 10 VME WRITE/READ ----------------- Bits 0- 5 : COARSE DELAY (0)-(5) program coarse delay between the "CAL" pulse ( FCS TP ) and the following "CAL.TRIGGER" ( TRIG IN ) ( in steps of 1 clock pulse = 96nsec, 6 bits, Register bit 0 = LSB ) Bits 6- 7 : - Bits 8-15 : FINE DELAY (0)-(7) program fine phase delay between the FCS TP and the H_CLK ( for both TEST and CALIBRATION ) ( in steps of 0.5 nsec, 8 bits, Register bit 8 = LSB ) NOTE : When all bits 8-15 are set ====== to "0", there is a minimum inherent delay of about 14 nsec J) Register 9 : H_CLOCK FINE DELAY ==================================== Base Address + 12 VME WRITE/READ ----------------- Bits 0- 7 : FINE H_CLK DELAY (0)-(7) program fine delay between the H_CLK sent to the HELIX INTERFACE ( and also the A_CLK, sent to the ADC modules via the C&C SLAVEs ) w/respect to the GFLT clock ( in steps of 0.5 nsec, 8 bits, Register bit 0 = LSB ) NOTE : When all bits 0-7 are set ====== to "0", there is a minimum inherent delay of about 14 nsec K) Register A : TEST PULSE COARSE DELAY ========================================= Base Address + 14 VME WRITE/READ ----------------- Bits 0-15 : COARSE TEST PULSE DELAY(0)-(15) program coarse delay between the TESTEN command and the following "CAL" ( FCS TP ) ( in steps of 1 clock = 96nsec, 16 bits, Register bit 0 = LSB ) 5) The C&C MASTER has following switches : ======================================= A) ON THE FRONT PANEL : -------------------- SW1 Push to generate a single TRIGGER SW2 Push to generate a single OVERALL RESET B) 8-BIT DIL SWITCHES ON PCB : --------------------------- NOTE : setting any switch lever to "ON" sets ====== the relevant bit to "0" SW3 set to minimize the phase delay between the incoming GFLT clock "96NSCK" on U8/pin 5 and the output PLL-ed "CLK1" on link LK1 ( = U58/pin 2 ) 8 bits, 0.5nsec DEFAULT : 1-6, 8 = "ON" --------- 7 = "OFF" NOTE : When all bits 1-8 are set to "0", there ====== is a minimum inherent delay of about 14 nsec SW4 set the global phase delay of the A_CLK being sent to all the ADC modules via the C&C SLAVEs synchronously w/respect to the H_CLK sent to the HELIX INTERFACE MODULE 8 bits, 0.5nsec DEFAULT : This value will have to be obtained --------- empirically when the complete system of detector, cables and electronics is installed NOTE : When all bits 1-8 are set to "0", there ====== is a minimum inherent delay of about 14 nsec C) ROTARY SWITCHES : ----------------- a) set VME base address ( 4-bits, 0 - F each ): ---------------------- SW5 A28 - A31 SW6 A24 - A27 SW7 A20 - A23 SW8 A16 - A19 b) set TEST TRIGGER "TRIG.TYPE" bits TTYPE0-2 : -------------------------------------------- SW9 ( 3 bits used, valid values 0 - 7 ) 6) The C&C MASTER has following links : ==================================== a) links on signal lines : ----------------------- PL1 insert to enable OA_RESET to PLL for testing DEFAULT : do not use --------- PL2 insert to disable the PLL for testing DEFAULT : do not use --------- PL3 = LINK10 insert to select VME A24 mode remove to select VME A32 mode DEFAULT : insert --------- PL4 = LINK14 insert over pins 1+2 to select an active TERR for feedback to GFLT insert over pins 2+3 to select a permanent TERR = GND DEFAULT : insert over pins 2+3 --------- PL11 insert to connect NBP_ERROR signal from J2/pin 19C DEFAULT : insert --------- LK4 = LINK 13 insert to enable INIT_RESET to generate NOT_RESET DEFAULT : insert --------- LK6 = LINK 12 insert to enable NOT_RESET to generate A_RESET as well DEFAULT : do not use --------- LK10= LINK 11 insert to enable OA_RESET to generate NOT_RESET DEFAULT : do not use --------- b) links on power supply lines : ----------------------------- PL5 } insert to use -5V2 supply pins on JAUX PL6 } DEFAULT : do not use --------- PL7 } insert to connect GND to J2/pin 13C PL8 } J2/pin 13A DEFAULT : insert --------- ( in ADC crate ONLY ) PL9 } insert to connect -5V2 to J2/pin 19A PL10 } DEFAULT : do not use --------- 7) Diagnostic LED indicators : =========================== -5V * DS1 * +5V Gn --- Gn VME ACK : ACK * DS2 * VER : VME error Ye --- Ye H_CLK on : HCK * DS3 * ACL : A_CLK on Gn --- Gn PLL fault : PLE * DS4 * ORS : OA_RESET Rd --- Rd A_ABORT : ABT * DS5 * ACP : A_ACCEPT Rd --- Rd H_RESET : HRS * DS6 * CAL : FCS TP Ye --- Ye F_ERROR OUT : FER * DS7 * BUS : BUSY OUT Rd --- Rd ERROR OUT : INT * DS8 * ABS : MIXED BUSY Rd --- Rd SLAVE A ERROR : ER1 * DS9 * BS1 : Slave A BUSY Gn --- Gn Slave B ERROR : ER2 * DS10 * BS2 : Slave B BUSY Gn ---- Gn Slave C ERROR : ER3 * DS11 * BS3 : Slave C BUSY Gn ---- Gn Slave D ERROR : ER4 * DS12 * BS4 : Slave D BUSY Gn ---- Gn Slave E ERROR : ER5 * DS13 * BS5 : Slave E BUSY Gn ---- Gn 8) Default setting-up of the C&C MASTER ( for use in the ADC crate ONLY): ====================================================================== SW3 bits 1-6 + 8 = "ON" bit 7 = "OFF" SW4 bits 1-8 = "ON" SW5 0 SW6 0 SW7 F SW8 F PL3 insert PL4 insert over pins 2+3 PL7 insert PL8 insert PL11 insert LK4 insert 9) VME Interface : =============== C&C MASTER is a double-width, 9Ux340mm VME slave module It can be used in either A24/D16 or A32/D16 mode, selected by link PL3 Base address A16 - A23 and A24 - A31 is selectable by switches SW5-8 Address line A0 is always assumed to be ZERO, ie. no byte transfers 10) C&C MASTER requires +5V0 positive supply at 8 Amps and -5V2 negative supply at 4 Amps 11) Appendices : A) PLD1 - PLD4 : Description and code ============ B) Example of a Set-up programme for the C&C MASTER and C&C SLAVEs system