BRIEF DESCRIPTION OF ZEUS-MVD C&C SLAVE MODULE =============================================== D.A. Hayes, J.B. Lane, M. Postranecky University College London Version 1.1 DAH+JBL+MP-UCL, 24 February 2000 Version 1.0 DAH+JBL+MP-UCL, 18 February 2000 Version 0.2 JBL+MP-UCL, 16 February 2000 Version 0.1 MP-UCL, 15 February 2000 This note should be read together the description of the C&C MASTER, and also with the C&C SLAVE schematics and register diagrams available from the following address : http://www.hep.ucl.ac.uk/zeus/mvd/candc.html#MASTERBOX The C&C SLAVE receives the GFLT signals from the C&C MASTER and distributes them to all the ADCs within its crate via the User Defined Pins of the VME P2 connector as TTL bus, receiving back the "BUSY" and the two "ERROR" lines as wire-OR from the ADCs. It distributes the suitably timed 96nsec "A_CLK" synchronously to all the ADCs within its crate, via a specially wired-in set of 16 twisted pairs of identical length, to front-panel connectors. The C&C SLAVE also allows a continuous VME read access to a register with the three ADC-produced signals. Additionally, the C&C SLAVEs can operate with the C&C MASTER as a stand- -alone system ( ie. without the GFLT ) for test purposes, receiving the three ADC-produced-type signals from the host via the VME. Note it is necessary for the C&C SLAVE to receive the A_CLK ( as ECL differential pair CLK4 ) from the C&C MASTER. 1) Functional description of the C&C SLAVE : ========================================= The C&C SLAVEs receive the GFLT clock via the C&C MASTER as a suitably delayed A_CLK via one ribbon cable and one IDC connector J22 for each C&C SLAVE. The ACCEPT and ABORT are received by the C&C SLAVEs via the same IDC connector J22 from the C&C MASTER and passed to all the ADC modules as A_ACCEPT and A_ABORT via the dedicated J2 backplane pins. At the same time, the GFLT information, received from the C&C MASTER on the same IDC connector J22 and stored in the GFLT NUMBER and GFLT CONTROL Registers 0 and 1, is also sent to the ADC modules as three consecutive words of 8 bits each, MDB(0)-(7), together with two control bits A0SELECTB & A1SELECTB, on the dedicated pins of the backplane J2 : During the first clock cycle with A_ACCEPT asserted ( two control bits A0 & 1 = 00 ) : "READOUT TYPE" word is sent During the second clock cycle with A_ACCEPT asserted ( two control bits A0 & 1 = 01 ) : "FLTN" word is sent During the third clock cycle with A_ACCEPT asserted ( two control bits A0 & 1 = 10 ) : "GBCN" word is sent When the control bits A0 & 1 = 11 the data is invalid If the ENTESTBUSY ( Bit 14 of the SLAVE COMMAND Register 3 ) is set, the TRIGGER will generate TESTBUSY as Bit 15 of the SLAVE STATE Register 4. This is also "OR-ed" into the BUSY output to C&C MASTER. It is cleared by asserting the CLRTESTBUSY ( Bit 15 of the SLAVE COMMAND Register 3 ). Bit 12 of the SLAVE STATE Register 4, LASTTRIGABORT, is set by an ACCEPT being ABORTed. It remains asserted until the arrival of the next ACCEPT, to indicate that the previous ACCEPT was aborted. In the opposite direction, signals received as "wire-OR" from all the ADC modules by the C&C SLAVE are stored in the ADCs STATE Register 2, and sent back, via the same ribbon cable and IDC connector J22, to the C&C MASTER. These signals are BUSY, FATAL ERROR and ERROR ( RESET REQUEST ). The BUSY is an "OR" of the above described BUSYs from all ADC modules in the ADC crate as "wire-OR", of the TESTBUSY when enabled, and of the VBUSY when set by the host via the VME ( see below ). The F_ERROR is an "OR" of the F_ERRORs received from all ADC modules in the ADC crate as "wire-OR", and of the VF_ERROR from the host via the VME. The ERROR (R/R) is an "OR" of the ERROR (R/R)s received from all ADC modules in the ADC crate, and of the VERROR (R/R) from the host via the VME. This ERROR (R/R) is output also on the front panel LEMO-00 connector J5 as a negative-going TTL signal, and could be used as a local "INTERRUPT" if required. A SWITCH-ON RESET is generated automatically when the +5V supply is restored. This lasts about 1 clock period and produces an over-all on-board reset pulse. Same over-all reset is also generated by the VSOA RESET ( Bit 1 of the SLAVE COMMAND Register 3 ) and/or by pressing switch SW1. NOTE : This over-all reset clears all the registers ====== 2) The C&C SLAVE has the following inputs and outputs : ===================================================== A) EXTERNAL INPUTS AND OUTPUTS ON THE FRONT PANEL : ------------------------------------------------ a) TTL signals ( totem-pole outputs ) : ------------------------------------ - CONNECTOR J4 ( Lemo 00 ) TTLCLKOUTC OUTPUT TTL version of the ECL A_CLK - CONNECTOR J5 ( Lemo 00 ) NERROROUTB OUTPUT ( active LOW ) ERROR(R/R) from all ADC modules ( could be used as "INTERRUPT") b) Synchronised A_CLK outputs to individual ADC modules : ------------------------------------------------------ All ECL differential pairs - CONNECTORS J6 - J21 16x OUTPUTS ( 16x LEMO sockets, part LEMO.EPG.OB.302.HLN ) pin 1 ECLCLKOUTB pin 2 NECLCLKOUTB c) Connections to/from C&C MASTER module : --------------------------------------- All ECL differential pairs - CONNECTOR J22 ( 34-way IDC ) pin 1 BUSY 2 NBUSY 3 ERROR(R/R) 4 NERROR(R/R) 5 F_ERROR 6 NF_ERROR 7 A_ABORT 8 NA_ABORT 9 A_ACCEPT 10 NA_ACCEPT 11 A_RESET 12 NA_RESET 13 MDB(0) 14 NMDB(0) 15 MDB(1) 16 NMDB(1) 17 MDB(2) 18 NMDB(2) 19 MDB(3) 20 NMDB(3) 21 MDB(4) 22 NMDB(4) 23 MDB(5) 24 NMDB(5) 25 MDB(6) 26 NMDB(6) 27 MDB(7) 28 NMDB(7) 29 DA(0) 30 NDA(0) 31 DA(1) 32 NDA(1) 33 CLK_4 34 NCLK_4 B) OTHER CONNECTORS : ------------------ a) VME Backplane Connectors : -------------------------- - CONNECTOR J1 ( standard 3x32-pin DIN41612 PCB connector ) Standard VME connections - CONNECTOR J2 ( standard 3x32-pin DIN41612 PCB connector ) A B C 1 -5V2 VME +5V -5V2 2 -5V2 VME GND -5V2 3 -5V2 (VME) - -5V2 4 VME A24 5 VME A25 6 VME A26 7 VME A27 8 VME A28 9 VME A29 10 VME A30 11 VME A31 12 VME GND Z0 NBP_EMPTY 13 GND VME +5V GND 14 GND (VME) GND 15 GND (VME) GND 16 (VME) Z1 TTLCLKOUTB 17 (VME) Z2 NBP_BUSY 18 (VME) Z3 NBP_F_ERROR 19 (VME) Z4 NBP_ERROR 20 (VME) Z5 NBP_RESET 21 (VME) Z6 BP_ABORT 22 VME GND Z7 BP_ACCEPT 23 (VME) Z8 A1SELECTB 24 (VME) Z9 A0SELECTB 25 (VME) Z10 MDBOUTB(7) 26 (VME) Z11 MDBOUTB(6) 27 (VME) Z12 MDBOUTB(5) 28 (VME) Z13 MDBOUTB(4) 29 (VME) Z14 MDBOUTB(3) 30 (VME) Z15 MDBOUTB(2) 31 VME GND Z16 MDBOUTB(1) 32 VME +5V Z17 MDBOUTB(0) NOTE 1 : Z0 - Z17 is a private bus. ======== It is terminated at the cards and not at the backplane ( backside at slot 3 and slot 20 ) Z0 - Z17 is a TTL bus ADC internal: Z0: EMPTY ( negative ) ------------- ( can be used for DAQ-interrupt board as the source of SLT interrupt ) ADC -> C&C : Z2: BUSY ( negative ) ------------ Z3: FATAL ERROR ( negative ) Z4: ERROR ( RESET REQUEST )( negative ) C&C -> ADC : Z1: TTL Clock ( totem-pole output ) ------------ to indicate the timing to latch Z6-Z17 Z5: RESET ( negative ) ( Open collector output ) Note that ADC can also drive this line Z6: ABORT flag ( totem-pole output ) Z7: ACCEPT flag ( totem-pole output ) Z8: A1 } Address for D0-D7 data Z9: A0 } ( totem-pole output ) Z10-Z17: Trigger data D7-D0 ( totem-pole outputs ) NOTE 2 : some VXI-standard -5V2 pins can be connected ======== by links on PCB for test use in non-ADC crate - see circuit diagram - CONNECTOR J3 not used - CONNECTOR JAUX not used NOTE : CERN-standard GND and -5V2 pins can be connected ====== by links on PCB for test use in non-ADC crate - see circuit diagram b) J-TAG interface to PLDs : ------------------------- - CONNECTOR J23 ( 10-way IDC header on PCB ) standard JTAG-ISP-PORT connections for both on-board PLDs 3) The C&C SLAVE can generate the following signals : ================================================== A) FRONT PANEL SWITCH-GENERATED SIGNALS : -------------------------------------- - SWITCH SW1 Push to generate a single OVERALL RESET B) VME REGISTERS-GENERATED SIGNALS : --------------------------------- see below for the complete list of registers 4) Registers on the C&C SLAVE : ============================ A) Register 0 : GFLT NUMBER ============================= Base Address + 00 VME READ ONLY ----------------- Bits 0-7: FLTN 0-7 Stores FLTN received from the C&C MASTER for each ACCEPT Bits 8-15: GBCN 0-7 Stores GBCN received from the C&C MASTER for each ACCEPT B) Register 1 : GFLT CONTROL ============================== Base Address + 02 VME READ ONLY ----------------- Bit 0 - - - 5 ROSYS0 } 6 ROSYS1 } 7 ROAMB0 } 8 ROAMB1 } Stores READOUT TYPE received from 9 ROUSR0 } C&C MASTER for each ACCEPT 10 ROUSR1 } 11 ROUSR2 } 12 ABORT 13 ACCEPT 14 - 15 - C) Register 2 : ADCs STATE ============================ Base Address + 04 VME READ ONLY ----------------- Bit 0 - - - 3 BUSY # } 4 F_ERROR # } value of returns to C&C MASTER 5 - 6 ERROR (R/R) # } 7 - - - 9 BP_EMPTY } 10 BP_BUSY } 11 BP_F_ERROR } 12 BP_ERROR } value of the J2 backplane signals 13 BP_RESET } in the crate the C&C SLAVE is situated 14 BP_ABORT } ( "1" = asserted ) 15 BP_ACCEPT } NOTE : # BUSY is an "OR" of the following signals : ====== BUSYs received from all ADC modules in the ADC crate as "wire-OR", TESTBUSY when enabled, and the VBUSY F_ERROR is an "OR" of the following signals : F_ERRORs received from all ADC modules in the ADC crate as "wire-OR", and the VF_ERROR ERROR (R/R) is an "OR" of the following signals : ERROR (R/R)s received from all ADC modules in the ADC crate as "wire-OR", and the VERROR (R/R) D) Register 3 : SLAVE COMMAND =============================== Base Address + 06 VME WRITE/READ ----------------- Bit 0 - 1 VSOA RESET * writing "1" gives a single OVERALL RESET 2 - 3 VBUSY BUSY "1" = asserted 4 VF_ERROR F_ERROR -"- 5 - 6 VERROR (R/R) ERROR (R/R) -"- 7 - - - 14 ENTESTBUSY writing "1" enables TESTBUSY 15 CLRTESTBUSY * writing "1" clears TESTBUSY NOTE : * For each single command, write "1", followed ====== by "0" to clear the command E) Register 4 : SLAVE STATE ============================= Base Address + 08 VME READ ONLY ----------------- Bit 0 - - - 4 A_CLK ON set while clock sent to ADC modules is running - - 11 A_RESET set while A_RESET is sent to ADC modules 12 LASTTRIGABORT set when the previous ACCEPT was aborted - - 15 TESTBUSY set while TESTBUSY is asserted 5) The C&C SLAVE has following switches : ====================================== A) ON THE FRONT PANEL : -------------------- SW1 Push to generate a single OVERALL RESET B) 8-bit DIL ON PCB : ------------------ NOTE : setting any switch lever to "ON" sets ====== the relevant bit to "0" SW2 set the correct phase delay between the output A_CLK on the backplane pin J2/ and the ECL sockets J6 - J21 on the front panel and the other TTL signals on the ADC crate backplane J2 8 bits, 0.5nsec DEFAULT : 1,2,3,5,7 = "ON" --------- 4,6,8 = "OFF" NOTE : When all bits 1-8 are set to "0", there ====== is a minimum inherent delay of about 14 nsec C) ROTARY SWITCH : --------------- a) set VME base address ( 4-bits, 0 - F ): ---------------------- SW6 A28 - A31 SW5 A24 - A27 SW4 A20 - A23 SW3 A16 - A19 6) The C&C SLAVE has following links : =================================== a) links on signal lines : ----------------------- PL1 = LINK10 insert to select VME A24 mode remove to select VME A32 mode DEFAULT : insert --------- PL8 insert to connect NBP_ERROR signal from J2/pin 19C DEFAULT : insert --------- b) links on power supply lines : ----------------------------- PL2 } insert to use -5V2 supply pins on JAUX PL3 } DEFAULT : do not use --------- PL4 } insert to connect GND to J2/pin 13C PL5 } J2/pin 13A DEFAULT : insert --------- ( in ADC crate ONLY ) PL6 } insert to connect -5V2 to J2/pin 19A PL7 } DEFAULT : do not use --------- 7) Diagnostic LED indicators : =========================== -5V * DS1 * +5V Gn --- Gn VME ACK : ACK * DS2 * VER : VME error Ye --- Ye ADC A_RESET : ARS * DS3 * ORS : OA_RESET Rd --- Rd ADC A_ABORT : ABT * DS4 * ACP : ADC A_ACCEPT Rd --- Rd ADC A_BUSYB : ABY * DS5 * ACK : ADC A_CLK on Gn --- Rd ADC F_ERRORB : AFE * DS6 * AER : ADC A_ERRORB Gn --- Gn 8) Default setting-up of the C&C SLAVE ( for use in the ADC crate ONLY ): ====================================================================== SW2 bits 1,2,3,5,7 = "ON" bits 4,6,8 = "OFF" SW6 0 SW5 0 SW4 F SW3 0 PL1 insert PL4 insert PL5 insert PL8 insert 9) VME Interface : =============== C&C SLAVE is a single-width, 9Ux340mm VME slave module It can be used in either A24/D16 or A32/D16 mode, selected by link PL1 Base address A16 - A23 and A24 - A31 is selectable by switches SW3-6 Address line A0 is always assumed to be ZERO, ie. no byte transfers 10) C&C SLAVE requires +5V0 positive supply at 5 Amps and -5V2 negative supply at 2 Amps 11) Appendices : A) PLD1 - PLD2 : Description and code ============ B) Example of a Set-up programme for the C&C MASTER and C&C SLAVEs system