==============================================================================
TRIGGER REGISTERS for the CERC (VME I/F)
==============================================================================

Updates:
 12/10/04 - This document created (from cerc_registers_rs232.txt):
 07/11/04 - Moved registers around to fit BE/BETrig split
            Room is being made for additional inputs
 11/11/04 - Removed Reg 4 - FE Enables - use BE version now
          - Added Squirt en on desig 29. any read sets squirt mode
            until the fifo is empty.
 18/11/04 - Added BE-Reg Section with new BE-Trig-Enables register (BE-15)
          - Added FE enables, trig-in en and trig-loop-en to be-trig-en reg (BE-15)
          - Renamed Reg. 11 to Control Register (was Trigger Control)
          - Added fanout_en bit to control register (11)
 26/11/04 - Moved fanout-en to BeTrg reg-4
          - Updated LEDs
          - Added all debug registers
          Changes summary: see reg 4, 11, 24,25,26,27, FIFO, LEDs, BETrg
 13/12/04 - Renamed Reg 4 to General Enables, fixed typo bit1=>bit0
          - added reg 4: en-busy-timeout - bit(1)
          - added reg 16: Busy Timeout
 14/01/05 - Added coincedence logic - 	reg 19, 20 and enable bits in reg 1
  			 - Added pribusy catch register (reg 18)
  			 - Added input invert register (reg 17)
 20/01/05 - FIFO bits changed
 04/04/05 - Updated FIFO description
 25/05/05 - Added the (bizarrely missing) Squirt Register
  



==============================================================================

------------------------------------------------------------------------------
Designator - Register Mapping:
------------------------------------------------------------------------------
  0.  <unused/reserved>
  1.  Trigger Enables
  2.  Status
  3.  Catch
  4.  General Enables
  5.  Trigger Counter
  6.  Trigger Osc Period
  7.  <Trigger Burst Control - not implemented yet>
  8.  Pre-Busy Trigger Counter
  9.  Firmware Version ID
 10.  Firmware Synthesis Date
 11.  Trigger Control
 12.  Commands
 13.  FIFO
 14.  FIFO Status
 15.  QDR Test Control
 16.  Busy Timeout
*17.  Trigger Input Invert
*18.  Pribusy Catch
*19.  Coincedence AND0 Enables
*20.  Coincedence AND1 Enables 
*21.  <Coincedence AND2 Enables>   
*22.  <Coincedence AND3 Enables> 
*23.  <ExtBeamModeANDOR>
 24.  BE Spy Reg 1
 25.  BE Spy Reg 2
 26.  Test Mode Readout Len
 27.  Signals Catch
*28.  Sequencer Control
*29.  FIFO Squirt Read
 30.  RAM Data
 31.  RAM Address

------------------------------------------------------------------------------
Register Description:
------------------------------------------------------------------------------

 0. <unused/reserved>

 1. Trigger Enables - reg_trig_en
     0: Ext0_en
     1: Ext1_en
    ...
    15: Ext15_en
    
    16:
    17:
    18:
    19:
    20: 
*   21: <reserved - trig_raw>
*   22: <reserved - trig_cmd>
*   23: <reserved - trig_extall> 
    24: trig_osc_en - Enables Triggers from internal osc. (see Reg 6)
*	 25: cand0_en
*	 26: cand1_en
*	 27: <cand2_en>
*	 28: <cand3_en>
*   29: <cor_en>
*   30: <extbeammode0_en>
*   31: <extbeammode1_en>


 2. Trigger Status - reg_trig_stat
    Shows the level of a signal
     0: trig_ext0_i_stat - Status of External Trigger 0 at input
     1: trig_ext1_i_stat - Status of External Trigger 1 at input
	 ...
    15: trig_ext15_i_stat - Status of External Trigger 1 at input

    16:
    17:
    18:
    19:
    20: 
*   21: trig_raw
*   22: trig_cmd
*   23: trig_ext_all 
    24: trig_osc_stat - Status of osc trigger - (not very useful!)
*   25: cand0
*   26: cand1
*	 27: <cand2>
*	 28: <cand3>
*	 29: <cor>
*   30: <extbeammode0>
*   31: <extbeammode1>

*removed  8: trig_ext0_stat - Status of External Trigger 0 post enable
*removed  9: trig_ext1_stat - Status of External Trigger 1 post enable
*removed 16: trig_raw_stat - Status of Combined Trigger pre-busy logic
*removed 17: trigger_stat  - Status of Combined Trigger as sent to FE





 3. Input Catch - reg_input_catch
    Registers a 1 if an input has been high at anytime since the last reset.
    Reset by writing 0
     0: trig_ext0_i_catch - External Trigger 0 at input
     1: trig_ext1_i_catch - External Trigger 1 at input
	 ...
    15: trig_ext15_i_catch - External Trigger 1 at input

    16:
    17:
    18:
    19:
    20: 
    21: trig_raw
*   22: trig_cmd
*   23: trig_ext_all
    24: trig_osc_catch - Oscillator trigger
*   25: cand0
*	 26: cand1
*	 27: <cand2>
*	 28: <cand3>
*	 29: <cor>
*   30: <extbeammode0>
*   31: <extbeammode1>

*removed  8: trig_ext0_catch - External Trigger 0 post enable
*removed  9: trig_ext1_catch - External Trigger 1 post enable
*removed 16: trig_raw_catch - Combined Trigger pre-busy logic
*removed 17: trigger_catch  - Combined Trigger as sent to FE


 4. General Enables
     0: fanout_en - Enable Fanout - i.e. Crate Trigger for now
     1: busy_timeout_en - Enable Busy-timeout counter (resets counter)


*    8: Coinc enable
*	  9: <Coinc ModeInt Select : 0: cand0, 1: cand1>
*	 10: <Coinc ModeExt Enable : 0: ModeInt, 1: select mode from input>
	 28: 
	 29: 
	 30:
	 31:


 5. Trigger Counter
    - (31:0): Counts number of triggers sent to FE since last reset.
              Reset by write.


 6. Trigger Osc Period - reg_trig_osc_period
    - (31:0) - Sets time between Oscillator Triggers (trig_osc) in 25ns
      steps.
    Osc is reset by a write to register


 7. <Trigger Burst Control - not implemented yet>


 8. Pre-Busy Trigger Counter
    - (31:0): Counts number of triggers sent to FE since last reset.
              Reset by write.


 9. Firmware Version ID - reg_version
    - ( 7: 0): minor version
    - (15: 8): major verion
    - (23:16): 0x09 (Trig target ID)
    - (31:24): 0x12 (BE module ID)


10. Firmware Synthesis Date
    - Date/Time Synthesised, in seconds since the epoc (1/1/71)
      Use normal C routines to decode


11. Control - reg_control
    Control/Status register.
     0: busy_trig  - set when a trigger is received, cleared by writing a zero.
     1: busy_force - writing a 1 ensurea busy stays set,
        (but if busy is clear before setting this, it will generate a trigger)


12. bit 0: Send a BE-Trig Trigger - i.e. crate trigger.
           Set to zero before trying to clear the busy
    bit 1: Reset the trigger module (self clearing)


13. Read FIFO data


14. Read FIFO status


15. bit 0 = QDR_ADDR_19
    bit 1 = QDR_ADDR_20


16. Busy Timeout - reg_busy_timeout
    - (31:0) - Sets time between Trigger and busy auto clear in 25ns steps.
    Enabled by reg 4 bit 1 (busy_timeout_en)
    Timeout counter cleared by write (or a trigger).
    

*17.  Trigger Input Invert
	   Inverts input triggers and the cands
	   

*18.  Pribusy Catch
      Catches all sigs until the busy - cleared by a write

*19.  Coincedence AND0 Enables
      (15: 0) - Input enables 
      (31:16) - Input Inverts
      
*20.  Coincedence AND1 Enables 



*21.  <Coincedence AND2 Enables>   
*22.  <Coincedence AND3 Enables> 
*23.  <ExtBeamModeANDOR>


24.  BE Spy Reg 1

 (   31)  en_qdr_data_to_vme    -- be_rdout_cntl(1)
 (   30)  en_qdr_data_to_slink  -- be_rdout_cntl(0)
 (   29)  sw_trigger
 (28:25)  mode_reg              -- mode reg (3:0)
 (   24)  en_fe_data_capture    -- be_run_cntl(1)
 (   23)  en_trigger            -- be_run_cntl(0)
 (22:21)  qdr_test_data_en      -- test reg (3:2)
 (   20)  throttle_en           -- test reg (1)
 (   19)  apv_frame_en          -- test reg (0)
 (18:16)  sel_trig_source       -- trigger select
 (15: 8)  FE_enable_reg         -- fe enable reg
 ( 7: 0)  FE_frame_sync_en      -- fe enable reg (same as above)



25.  BE Spy Reg 2
 (31:12) <unused = 0>
 (11:0)  fed_id_reg


26.  Test Mode Readout Len
 Sets the readlength in test_mode:
   Trig-Desig-26 (14:0).


27.  Signals Catch
   (   20) FE-0 Trigger as sent  (BEEFY)
   (   19) Synchronous Trigger   (BEEFY)
   (   18) FE-0 readout_sync_out (BEEFY)
   (   17) FE-0 frame_sync_in    (PHEOBE)
   (   16) FE-0 readout_sync_in  (PHEOBE)
   (15: 0) FE-0 Data into BE     (PHEOBE)
   
   
   
*28. Sequencer Control - reg_sequencer
	
	  (15: 0) Seq_en
     (25:16) SeqCount
     (29:26) <reserved for possibel increase in sequencer length

     29: SeqLoopEn - Enable seq infinite run by looping 
     30: SeqGo     - Start Seq running
     31: SeqReset  - Reset Seq (set counter to zero, stop loop, clear go)
     

*29. FIFO Squirt Read
	 Starts a read of all Trigger FIFO Data as a single command, with the 
	 contents of the *entire* FIFO serialised out as the payload data.
	 You should program the serial data length depending on FIFO depth.
   

30. RAM Port Data
    Reads and writes data to the address in Reg 31

31. RAM Port Address
    (   31) if set address is auto incremented (by 4) after a read or write.
    (15: 0) RAM address (lowest 2 bits ignored) (higher order bits might not 
            be used either.



------------------------------------------------------------------------------
RAM and FIFO
------------------------------------------------------------------------------

RAM:  1kx32: 0x0000-0x0FFC. Not used - For testing purposes only.

*
FIFO: Log Trig Activity. Depth: 1023  Width: 32bit
   Prior to a trigger this is kept 300 trigs full (oldest data replaced by newest
   data). It is allowed to fill after a trigger and is frozen when full.
   It gets reset and starts filling again when the trigger-busy is cleared.}


------------------------------------------------------------------------------
BE LEDs
------------------------------------------------------------------------------
Note all LED driver signals are stretched for visibilty

 BE single led - near FPGA:
 - be_led - flashes to show clocks are running

 Array - vertical row near center of board (numbered from top):

  1: BE Trigger
* 2: Trig Coinc-AND0
  3: BeTrg Trigger-Out (to fanout)
  4: Trigger in (from J0 A4/B4)
  5: Trigger in post enable
  6: FE0 Trigger (as sent out of pin)
  7: BeTrg Trigger-Out pre-busy
  8: FE5 Trigger (as sent out of pin)
  9: BeTrg serial command to VME
 10: BeTrg Busy
 11: <not under our control>


******************************************************************************
* BETrg
******************************************************************************

These are extras added to the original FED set

 15. Trigger Enables - reg_fe_trig_en
    Resets to 0x000000FF (i.e. all FE triggers enabled)

    (  9) crate_trig_loop_en - enable internal crate-trig loopback (bypass j0)
    (  8) crate_trig_in_en - enable j0 trigger input
    (7:0) trig_feN_en - enabled triggers to FEs