MCP_TARGET_BOTTOMv01 Project Status (07/20/2010 - 17:29:27)
Project File: MCP_TARGET_BOTTOMv01.ise Implementation State: Programming File Not Generated
Module Name: TOP
  • Errors:
No Errors
Target Device: xc3s400-4pq208
  • Warnings:
29 Warnings
Product Version:ISE 11.5
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
0 (Setup: 0, Hold: 0) (Timing Report)
 
MCP_TARGET_BOTTOMv01 Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 52 7,168 1%  
Number of 4 input LUTs 107 7,168 1%  
Number of occupied Slices 74 3,584 2%  
    Number of Slices containing only related logic 74 74 100%  
    Number of Slices containing unrelated logic 0 74 0%  
Total Number of 4 input LUTs 135 7,168 1%  
    Number used as logic 107      
    Number used as a route-thru 28      
Number of bonded IOBs 49 141 34%  
    IOB Master Pads 10      
    IOB Slave Pads 10      
Number of BUFGMUXs 1 8 12%  
Number of RPM macros 2      
Average Fanout of Non-Clock Nets 2.95      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Jul 21 12:50:42 2010017 Warnings2 Infos
Translation ReportCurrentWed Jul 21 12:50:55 2010000
Map ReportCurrentWed Jul 21 12:51:07 201008 Warnings2 Infos
Place and Route ReportCurrentWed Jul 21 12:51:27 201004 Warnings4 Infos
Post-PAR Static Timing ReportCurrentWed Jul 21 12:51:34 2010003 Infos
Bitgen ReportCurrentWed Jul 21 12:51:44 2010001 Info
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 07/21/2010 - 14:38:06