T | Synthesis Messages - Errors, Warnings, and Infos | New |
WARNING | Xst:753 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/TOP.vhf" line 1433: Unconnected output port 'xCLK_1kHz' of component 'CLK_MAIN_MUSER_TOP'. | |
WARNING | Xst:753 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/TOP.vhf" line 1518: Unconnected output port 'xSPA' of component 'MAIN_IO_MUSER_TOP'. | |
WARNING | Xst:753 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/TOP.vhf" line 1518: Unconnected output port 'xREF_CLK' of component 'MAIN_IO_MUSER_TOP'. | |
WARNING | Xst:753 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/TOP.vhf" line 1518: Unconnected output port 'xREV' of component 'MAIN_IO_MUSER_TOP'. | |
WARNING | Xst:753 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/TOP.vhf" line 1617: Unconnected output port 'xTRACK_COL' of component 'TARGET_TOP'. | |
WARNING | Xst:753 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/TOP.vhf" line 1617: Unconnected output port 'xLOCK_COL' of component 'TARGET_TOP'. | |
WARNING | Xst:753 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/TOP.vhf" line 1617: Unconnected output port 'xLOCK_ROW' of component 'TARGET_TOP'. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/HK_CLK.vhd" line 181: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/HK_CLK.vhd" line 186: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/HK_CLK.vhd" line 191: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/HK_CLK.vhd" line 196: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/OBUF4X.vhd" line 45: Instantiating black box module <OBUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/OBUF4X.vhd" line 50: Instantiating black box module <OBUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/OBUF4X.vhd" line 55: Instantiating black box module <OBUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/OBUF4X.vhd" line 60: Instantiating black box module <OBUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/OBUF3.vhd" line 45: Instantiating black box module <OBUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/OBUF3.vhd" line 50: Instantiating black box module <OBUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/OBUF3.vhd" line 55: Instantiating black box module <OBUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/OBUF5.vhd" line 45: Instantiating black box module <OBUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/OBUF5.vhd" line 50: Instantiating black box module <OBUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/OBUF5.vhd" line 55: Instantiating black box module <OBUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/OBUF5.vhd" line 60: Instantiating black box module <OBUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/OBUF5.vhd" line 65: Instantiating black box module <OBUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/OBUF6.vhd" line 45: Instantiating black box module <OBUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/OBUF6.vhd" line 50: Instantiating black box module <OBUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/OBUF6.vhd" line 55: Instantiating black box module <OBUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/OBUF6.vhd" line 60: Instantiating black box module <OBUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/OBUF6.vhd" line 65: Instantiating black box module <OBUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/OBUF6.vhd" line 70: Instantiating black box module <OBUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/OBUF2.vhd" line 45: Instantiating black box module <OBUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/OBUF2.vhd" line 50: Instantiating black box module <OBUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/MESS.vhd" line 155: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF16.vhd" line 45: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF16.vhd" line 50: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF16.vhd" line 55: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF16.vhd" line 60: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF16.vhd" line 65: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF16.vhd" line 70: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF16.vhd" line 75: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF16.vhd" line 80: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF16.vhd" line 85: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF16.vhd" line 90: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF16.vhd" line 95: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF16.vhd" line 100: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF16.vhd" line 105: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF16.vhd" line 110: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF16.vhd" line 115: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF16.vhd" line 120: Instantiating black box module <BUF>. | |
WARNING | Xst:753 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/DAC_MAIN.vhd" line 127: Unconnected output port 'xROGND' of component 'RCO_MAIN'. | |
WARNING | Xst:752 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/DAC_MAIN.vhd" line 127: Unconnected input port 'xPRCO' of component 'RCO_MAIN' is tied to default value. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/DAC_MAIN.vhd" line 180: Instantiating black box module <OBUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/DAC_MAIN.vhd" line 185: Instantiating black box module <OBUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/DAC_MAIN.vhd" line 190: Instantiating black box module <OBUF>. | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/RCO_INT.vhd" line 108: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<CNT_CLR> | |
WARNING | Xst:1962 - The length of the hex value for the attribute INIT_A on instance XLXI_226 should be 36 bits long. The current value set is 1 bits long. Value has been extended | |
WARNING | Xst:1962 - The length of the hex value for the attribute INIT_B on instance XLXI_226 should be 36 bits long. The current value set is 1 bits long. Value has been extended | |
WARNING | Xst:1962 - The length of the hex value for the attribute SRVAL_A on instance XLXI_226 should be 36 bits long. The current value set is 1 bits long. Value has been extended | |
WARNING | Xst:1962 - The length of the hex value for the attribute SRVAL_B on instance XLXI_226 should be 36 bits long. The current value set is 1 bits long. Value has been extended | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF4.vhd" line 45: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF4.vhd" line 50: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF4.vhd" line 55: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF4.vhd" line 60: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/GND_4.vhd" line 43: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/GND_4.vhd" line 48: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/GND_4.vhd" line 53: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/GND_4.vhd" line 58: Instantiating black box module <BUF>. | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/RCO_CALC.vhd" line 65: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xSET_VDD> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/RCO_CALC.vhd" line 92: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xSET_VDD> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/RCO_CALC.vhd" line 105: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xVDD_BUF>, <xVDD> | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/DAC_TIMING.vhd" line 77: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/DAC_TIMING.vhd" line 82: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/DAC_TIMING.vhd" line 87: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/DAC_TIMING.vhd" line 92: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/DAC_TIMING.vhd" line 97: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/DAC_TIMING.vhd" line 102: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/DAC_TIMING.vhd" line 107: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/DAC_TIMING.vhd" line 112: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/DAC_TIMING.vhd" line 117: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/DAC_TIMING.vhd" line 122: Instantiating black box module <INV>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/DAC_TIMING.vhd" line 127: Instantiating black box module <INV>. | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/DAC_TIMING.vhd" line 132: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xDONE> | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/DAC_SERIALIZER.vhd" line 65: Instantiating black box module <BUF>. | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/DAC_SERIALIZER.vhd" line 70: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xDAC_A>, <xDAC_B>, <xDAC_C>, <xDAC_D> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/DAC_SERIALIZER.vhd" line 92: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xDATA> | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/MAIN_REG.vhd" line 109: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/MAIN_REG.vhd" line 114: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF12.vhd" line 45: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF12.vhd" line 50: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF12.vhd" line 55: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF12.vhd" line 60: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF12.vhd" line 65: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF12.vhd" line 70: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF12.vhd" line 75: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF12.vhd" line 80: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF12.vhd" line 85: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF12.vhd" line 90: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF12.vhd" line 95: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF12.vhd" line 100: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF5.vhd" line 45: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF5.vhd" line 50: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF5.vhd" line 55: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF5.vhd" line 60: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF5.vhd" line 65: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF3.vhd" line 45: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF3.vhd" line 50: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF3.vhd" line 55: Instantiating black box module <BUF>. | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/SCALER_TOP.vhd" line 105: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<SCALER0>, <SCALER1>, <SCALER2> | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_TOP.vhd" line 283: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_TOP.vhd" line 288: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_TOP.vhd" line 293: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_TOP.vhd" line 298: Instantiating black box module <BUF>. | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_TSA_CTRL.vhd" line 120: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xCLR_ALL>, <xDONE> | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_TSA_CTRL.vhd" line 151: Instantiating black box module <BUF>. | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_TSA_CTRL.vhd" line 156: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xNRUN> | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_TSA_CTRL.vhd" line 288: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TSA_32CYCLE_ONESHOT.vhd" line 84: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF2.vhd" line 45: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF2.vhd" line 50: Instantiating black box module <BUF>. | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_RAMP.vhd" line 198: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<PED_COL>, <PED_ROW>, <LOCK_BACKUP> | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_RAMP.vhd" line 232: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_RAMP.vhd" line 237: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF6.vhd" line 45: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF6.vhd" line 50: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF6.vhd" line 55: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF6.vhd" line 60: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF6.vhd" line 65: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/BUF6.vhd" line 70: Instantiating black box module <BUF>. | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 108: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 108: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 108: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 108: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 108: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 108: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 108: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 108: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 108: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 108: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 108: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 108: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 108: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 108: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 108: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 108: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 123: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 123: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 123: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 123: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 123: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 123: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 123: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 123: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 123: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 123: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 123: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 123: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 123: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 123: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 123: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 123: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 138: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 138: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 138: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 138: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 138: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 138: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 138: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 138: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 138: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 138: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 138: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 138: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 138: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 138: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 138: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 138: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 153: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 153: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 153: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 153: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 153: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 153: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 153: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 153: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 153: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 153: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 153: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 153: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 153: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 153: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 153: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 153: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRESET_RAMP> | |
WARNING | Xst:790 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 168: Index value(s) does not match array range, simulation mismatch. | |
INFO | Xst:1433 - Contents of array <xCNT_RISING<0>> may be accessed with an index that exceeds the array size. This could cause simulation mismatch. | |
WARNING | Xst:790 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 168: Index value(s) does not match array range, simulation mismatch. | |
INFO | Xst:1433 - Contents of array <xCNT_FALLING<0>> may be accessed with an index that exceeds the array size. This could cause simulation mismatch. | |
WARNING | Xst:1610 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 168: Width mismatch. <xT_DATA> has a width of 16 bits but assigned expression is 12-bit wide. | |
WARNING | Xst:790 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 169: Index value(s) does not match array range, simulation mismatch. | |
INFO | Xst:1433 - Contents of array <xCNT_RISING<1>> may be accessed with an index that exceeds the array size. This could cause simulation mismatch. | |
WARNING | Xst:790 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 169: Index value(s) does not match array range, simulation mismatch. | |
INFO | Xst:1433 - Contents of array <xCNT_FALLING<1>> may be accessed with an index that exceeds the array size. This could cause simulation mismatch. | |
WARNING | Xst:1610 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_PIXx32.vhd" line 169: Width mismatch. <xB_DATA> has a width of 16 bits but assigned expression is 12-bit wide. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_RAM_TIMING.vhd" line 86: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_RAM_TIMING.vhd" line 91: Instantiating black box module <BUF>. | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_RAM_TIMING.vhd" line 120: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<CNT_A<3>> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_RAM_TIMING.vhd" line 117: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<xRAMP_DONE> | |
WARNING | Xst:819 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_RAM_TIMING.vhd" line 129: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<CNT_A<11>> | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_RAM_TIMING.vhd" line 135: Instantiating black box module <BUF>. | |
WARNING | Xst:2211 - "C:/Firmware/CREAM/v4_test/MCP_TARGETv04/src/TARGET_RAM_TIMING.vhd" line 140: Instantiating black box module <BUF>. | |
WARNING | Xst:1962 - The length of the hex value for the attribute INIT_A on instance XLXI_226 should be 36 bits long. The current value set is 1 bits long. Value has been extended | |
WARNING | Xst:1962 - The length of the hex value for the attribute INIT_B on instance XLXI_226 should be 36 bits long. The current value set is 1 bits long. Value has been extended | |
WARNING | Xst:1962 - The length of the hex value for the attribute SRVAL_A on instance XLXI_226 should be 36 bits long. The current value set is 1 bits long. Value has been extended | |
WARNING | Xst:1962 - The length of the hex value for the attribute SRVAL_B on instance XLXI_226 should be 36 bits long. The current value set is 1 bits long. Value has been extended | |
WARNING | Xst:1962 - The length of the hex value for the attribute INIT_A on instance XLXI_1749 should be 36 bits long. The current value set is 1 bits long. Value has been extended | |
WARNING | Xst:1962 - The length of the hex value for the attribute INIT_B on instance XLXI_1749 should be 36 bits long. The current value set is 1 bits long. Value has been extended | |
WARNING | Xst:1962 - The length of the hex value for the attribute SRVAL_A on instance XLXI_1749 should be 36 bits long. The current value set is 1 bits long. Value has been extended | |
WARNING | Xst:1962 - The length of the hex value for the attribute SRVAL_B on instance XLXI_1749 should be 36 bits long. The current value set is 1 bits long. Value has been extended | |
WARNING | Xst:1962 - The length of the hex value for the attribute INIT_A on instance XLXI_1770 should be 36 bits long. The current value set is 1 bits long. Value has been extended | |
WARNING | Xst:1962 - The length of the hex value for the attribute INIT_B on instance XLXI_1770 should be 36 bits long. The current value set is 1 bits long. Value has been extended | |
WARNING | Xst:1962 - The length of the hex value for the attribute SRVAL_A on instance XLXI_1770 should be 36 bits long. The current value set is 1 bits long. Value has been extended | |
WARNING | Xst:1962 - The length of the hex value for the attribute SRVAL_B on instance XLXI_1770 should be 36 bits long. The current value set is 1 bits long. Value has been extended | |
WARNING | Xst:1962 - The length of the hex value for the attribute INIT_A on instance XLXI_1862 should be 36 bits long. The current value set is 1 bits long. Value has been extended | |
WARNING | Xst:1962 - The length of the hex value for the attribute INIT_B on instance XLXI_1862 should be 36 bits long. The current value set is 1 bits long. Value has been extended | |
WARNING | Xst:1962 - The length of the hex value for the attribute SRVAL_A on instance XLXI_1862 should be 36 bits long. The current value set is 1 bits long. Value has been extended | |
WARNING | Xst:1962 - The length of the hex value for the attribute SRVAL_B on instance XLXI_1862 should be 36 bits long. The current value set is 1 bits long. Value has been extended | |
WARNING | Xst:647 - Input <xWADDR<15:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. | |
WARNING | Xst:1780 - Signal <xCHECK_RISING<1><31:16>> is never used or assigned. This unconnected signal will be trimmed during the optimization process. | |
WARNING | Xst:1780 - Signal <xCHECK_RISING<0><31:16>> is never used or assigned. This unconnected signal will be trimmed during the optimization process. | |
WARNING | Xst:1780 - Signal <xCHECK_FALLING<1><31:16>> is never used or assigned. This unconnected signal will be trimmed during the optimization process. | |
WARNING | Xst:1780 - Signal <xCHECK_FALLING<0><31:16>> is never used or assigned. This unconnected signal will be trimmed during the optimization process. | |
WARNING | Xst:646 - Signal <CH_NUMBER<4>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
INFO | Xst:1799 - State lo_1hz is never reached in FSM <STATE_10Hz>. | |
INFO | Xst:1799 - State hi_100hz is never reached in FSM <STATE_10Hz>. | |
INFO | Xst:1799 - State lo_100hz is never reached in FSM <STATE_10Hz>. | |
INFO | Xst:1799 - State hi_1khz is never reached in FSM <STATE_10Hz>. | |
INFO | Xst:1799 - State lo_1khz is never reached in FSM <STATE_10Hz>. | |
INFO | Xst:1799 - State lo_1hz is never reached in FSM <STATE_100Hz>. | |
INFO | Xst:1799 - State hi_10hz is never reached in FSM <STATE_100Hz>. | |
INFO | Xst:1799 - State lo_10hz is never reached in FSM <STATE_100Hz>. | |
INFO | Xst:1799 - State hi_1khz is never reached in FSM <STATE_100Hz>. | |
INFO | Xst:1799 - State lo_1khz is never reached in FSM <STATE_100Hz>. | |
INFO | Xst:1799 - State hi_10hz is never reached in FSM <STATE_1Hz>. | |
INFO | Xst:1799 - State lo_10hz is never reached in FSM <STATE_1Hz>. | |
INFO | Xst:1799 - State hi_100hz is never reached in FSM <STATE_1Hz>. | |
INFO | Xst:1799 - State lo_100hz is never reached in FSM <STATE_1Hz>. | |
INFO | Xst:1799 - State hi_1khz is never reached in FSM <STATE_1Hz>. | |
INFO | Xst:1799 - State lo_1khz is never reached in FSM <STATE_1Hz>. | |
INFO | Xst:1799 - State lo_1hz is never reached in FSM <STATE_1kHz>. | |
INFO | Xst:1799 - State hi_10hz is never reached in FSM <STATE_1kHz>. | |
INFO | Xst:1799 - State lo_10hz is never reached in FSM <STATE_1kHz>. | |
INFO | Xst:1799 - State hi_100hz is never reached in FSM <STATE_1kHz>. | |
INFO | Xst:1799 - State lo_100hz is never reached in FSM <STATE_1kHz>. | |
WARNING | Xst:647 - Input <xS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. | |
WARNING | Xst:646 - Signal <Locmd<15:13>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
WARNING | Xst:646 - Signal <Hicmd<15:12>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
WARNING | Xst:646 - Signal <DUMMY> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
INFO | Xst:2117 - HDL ADVISOR - Mux Selector <STATE> of Case statement line 139 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
- add an 'INIT' attribute on signal <STATE> (optimization is then done without any risk)
- use the attribute 'signal_encoding user' to avoid onehot optimization
- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization | |
WARNING | Xst:646 - Signal <xCNT<15:9>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
WARNING | Xst:646 - Signal <xCNT<5:1>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
WARNING | Xst:1780 - Signal <xGND> is never used or assigned. This unconnected signal will be trimmed during the optimization process. | |
WARNING | Xst:647 - Input <xDHIT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. | |
WARNING | Xst:646 - Signal <TEMP_F<7:6>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
WARNING | Xst:646 - Signal <TEMP_F<4:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
WARNING | Xst:646 - Signal <TEMP_C<7:6>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
WARNING | Xst:646 - Signal <TEMP_C<4:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
WARNING | Xst:646 - Signal <RAMP_ADDR<11:5>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
WARNING | Xst:646 - Signal <STRB> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
WARNING | Xst:1780 - Signal <MAP_ADDR> is never used or assigned. This unconnected signal will be trimmed during the optimization process. | |
WARNING | Xst:646 - Signal <CNT_B> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
WARNING | Xst:1780 - Signal <ADDR> is never used or assigned. This unconnected signal will be trimmed during the optimization process. | |
INFO | Xst:1799 - State rphase0 is never reached in FSM <STATE>. | |
INFO | Xst:1799 - State rphase1 is never reached in FSM <STATE>. | |
INFO | Xst:1799 - State rphase2 is never reached in FSM <STATE>. | |
INFO | Xst:1799 - State rphase3 is never reached in FSM <STATE>. | |
INFO | Xst:1799 - State phase1 is never reached in FSM <RSTATE>. | |
INFO | Xst:1799 - State phase2 is never reached in FSM <RSTATE>. | |
INFO | Xst:1799 - State phase3 is never reached in FSM <RSTATE>. | |
INFO | Xst:1799 - State rphase3 is never reached in FSM <RSTATE>. | |
WARNING | Xst:647 - Input <xRADDR<15:12>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. | |
WARNING | Xst:647 - Input <xWADDR<15:12>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. | |
WARNING | Xst:647 - Input <xFCLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. | |
WARNING | Xst:647 - Input <xCLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. | |
WARNING | Xst:647 - Input <xPRCO> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. | |
WARNING | Xst:647 - Input <xDEBUG> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. | |
WARNING | Xst:647 - Input <xCLK_10Hz> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. | |
WARNING | Xst:647 - Input <xCLK_1Hz> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. | |
WARNING | Xst:1780 - Signal <xREFRESH> is never used or assigned. This unconnected signal will be trimmed during the optimization process. | |
WARNING | Xst:646 - Signal <xROVDD<15:12>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
INFO | Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. | |
WARNING | Xst:1426 - The value init of the FF/Latch FFd2 hinder the constant cleaning in the block FSM.
You should achieve better results by setting this init to 1. | |
WARNING | Xst:1426 - The value init of the FF/Latch FFd2 hinder the constant cleaning in the block FSM.
You should achieve better results by setting this init to 1. | |
WARNING | Xst:1426 - The value init of the FF/Latch FFd2 hinder the constant cleaning in the block FSM.
You should achieve better results by setting this init to 1. | |
WARNING | Xst:1710 - FF/Latch <LOCK_COL_0> (without init value) has a constant value of 0 in block <xTARGET_TSA_CTRL>. This FF/Latch will be trimmed during the optimization process. | |
WARNING | Xst:2677 - Node <Locmd_13> of sequential type is unconnected in block <XLXI_2934>. | |
WARNING | Xst:2677 - Node <Locmd_14> of sequential type is unconnected in block <XLXI_2934>. | |
WARNING | Xst:2677 - Node <Locmd_15> of sequential type is unconnected in block <XLXI_2934>. | |
WARNING | Xst:2677 - Node <Hicmd_12> of sequential type is unconnected in block <XLXI_2934>. | |
WARNING | Xst:2677 - Node <Hicmd_13> of sequential type is unconnected in block <XLXI_2934>. | |
WARNING | Xst:2677 - Node <Hicmd_14> of sequential type is unconnected in block <XLXI_2934>. | |
WARNING | Xst:2677 - Node <Hicmd_15> of sequential type is unconnected in block <XLXI_2934>. | |
WARNING | Xst:2677 - Node <Locmd_13> of sequential type is unconnected in block <MAIN_REG>. | |
WARNING | Xst:2677 - Node <Locmd_14> of sequential type is unconnected in block <MAIN_REG>. | |
WARNING | Xst:2677 - Node <Locmd_15> of sequential type is unconnected in block <MAIN_REG>. | |
WARNING | Xst:2677 - Node <Hicmd_12> of sequential type is unconnected in block <MAIN_REG>. | |
WARNING | Xst:2677 - Node <Hicmd_13> of sequential type is unconnected in block <MAIN_REG>. | |
WARNING | Xst:2677 - Node <Hicmd_14> of sequential type is unconnected in block <MAIN_REG>. | |
WARNING | Xst:2677 - Node <Hicmd_15> of sequential type is unconnected in block <MAIN_REG>. | |
WARNING | Xst:1426 - The value init of the FF/Latch FSM_FFd2 hinder the constant cleaning in the block FSM_3-parent.
You should achieve better results by setting this init to 1. | |
WARNING | Xst:1426 - The value init of the FF/Latch FSM_FFd2 hinder the constant cleaning in the block FSM_1-parent.
You should achieve better results by setting this init to 1. | |
WARNING | Xst:1426 - The value init of the FF/Latch FSM_FFd2 hinder the constant cleaning in the block FSM_0-parent.
You should achieve better results by setting this init to 1. | |
WARNING | Xst:1710 - FF/Latch <LOCK_COL_0> (without init value) has a constant value of 0 in block <TARGET_TSA_CTRL>. This FF/Latch will be trimmed during the optimization process. | |
INFO | Xst:2261 - The FF/Latch <STATE_1kHz_FSM_FFd2> in Unit <HK_CLK> is equivalent to the following 2 FFs/Latches, which will be removed : <STATE_100Hz_FSM_FFd2> <STATE_10Hz_FSM_FFd2> | |
WARNING | Xst:2677 - Node <MAIN_CNT_7> of sequential type is unconnected in block <TARGET_TSA_CTRL>. | |
WARNING | Xst:2677 - Node <MAIN_CNT_8> of sequential type is unconnected in block <TARGET_TSA_CTRL>. | |
WARNING | Xst:2677 - Node <MAIN_CNT_9> of sequential type is unconnected in block <TARGET_TSA_CTRL>. | |
WARNING | Xst:2677 - Node <MAIN_CNT_10> of sequential type is unconnected in block <TARGET_TSA_CTRL>. | |
WARNING | Xst:2677 - Node <MAIN_CNT_11> of sequential type is unconnected in block <TARGET_TSA_CTRL>. | |
WARNING | Xst:2677 - Node <MAIN_CNT_12> of sequential type is unconnected in block <TARGET_TSA_CTRL>. | |
WARNING | Xst:2677 - Node <MAIN_CNT_13> of sequential type is unconnected in block <TARGET_TSA_CTRL>. | |
WARNING | Xst:2677 - Node <MAIN_CNT_14> of sequential type is unconnected in block <TARGET_TSA_CTRL>. | |
WARNING | Xst:2677 - Node <MAIN_CNT_15> of sequential type is unconnected in block <TARGET_TSA_CTRL>. | |
WARNING | Xst:2677 - Node <MAIN_CNT_8> of sequential type is unconnected in block <TARGET_RAMP>. | |
WARNING | Xst:2677 - Node <MAIN_CNT_9> of sequential type is unconnected in block <TARGET_RAMP>. | |
WARNING | Xst:2677 - Node <MAIN_CNT_10> of sequential type is unconnected in block <TARGET_RAMP>. | |
WARNING | Xst:2677 - Node <MAIN_CNT_11> of sequential type is unconnected in block <TARGET_RAMP>. | |
WARNING | Xst:2677 - Node <MAIN_CNT_12> of sequential type is unconnected in block <TARGET_RAMP>. | |
WARNING | Xst:2677 - Node <MAIN_CNT_13> of sequential type is unconnected in block <TARGET_RAMP>. | |
WARNING | Xst:2677 - Node <MAIN_CNT_14> of sequential type is unconnected in block <TARGET_RAMP>. | |
WARNING | Xst:2677 - Node <MAIN_CNT_15> of sequential type is unconnected in block <TARGET_RAMP>. | |
WARNING | Xst:2677 - Node <CNT_A_16> of sequential type is unconnected in block <TARGET_RAM_TIMING>. | |
WARNING | Xst:2677 - Node <CNT_A_17> of sequential type is unconnected in block <TARGET_RAM_TIMING>. | |
WARNING | Xst:2677 - Node <CNT_A_18> of sequential type is unconnected in block <TARGET_RAM_TIMING>. | |
WARNING | Xst:2677 - Node <CNT_A_19> of sequential type is unconnected in block <TARGET_RAM_TIMING>. | |
INFO | Xst:1901 - Instance XLXI_226 in unit XLXI_226 of type RAMB16_S4_S4 has been replaced by RAMB16 | |
INFO | Xst:1901 - Instance XLXI_1749 in unit XLXI_1749 of type RAMB16_S4_S4 has been replaced by RAMB16 | |
INFO | Xst:1901 - Instance XLXI_1770 in unit XLXI_1770 of type RAMB16_S4_S4 has been replaced by RAMB16 | |
INFO | Xst:1901 - Instance XLXI_1862 in unit XLXI_1862 of type RAMB16_S4_S4 has been replaced by RAMB16 | |
INFO | Xst:1901 - Instance xRCO_RAM/XLXI_226 in unit xRCO_RAM/XLXI_226 of type RAMB16_S4_S4 has been replaced by RAMB16 | |
INFO | Xst:2260 - The FF/Latch <xTARGET_TOP/xTARGET_TRIG/XLXI_22> in Unit <TOP> is equivalent to the following FF/Latch : <xTARGET_TOP/xTARGET_TRIG/XLXI_30> | |
INFO | Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. | |