Project Statistics |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_Simulator=Modelsim-SE Mixed |
PROP_Top_Level_Module_Type=Schematic |
PROP_PreferredLanguage=VHDL |
PROP_Enable_Message_Filtering=false |
PROP_Enable_Incremental_Messaging=false |
PROP_UseSmartGuide=false |
Partitions count=1 |
FILE_SCHEMATIC=10 |
FILE_UCF=1 |
FILE_VERILOG=1 |
FILE_VHDL=37 |
PROP_AutoTop=false |
PROP_CompxlibLang=VHDL |
PROP_CompxlibOverwriteLib=true |
PROP_DevDevice=xc3s400 |
PROP_DevFamily=Spartan3 |
PROP_DevSpeed=-4 |
PROP_FitterReportFormat=HTML |
PROP_MapEffortLevel=Standard |
PROP_PostTrceFastPath=false |
PROP_PreTrceFastPath=false |
PROP_PreferredLanguage=VHDL |
PROP_SimModelInsertBuffersPulseSwallow=false |
PROP_Top_Level_Module_Type=Schematic |
PROP_UserConstraintEditorPreference=Constraints Editor |
PROP_XPowerOptLoadXMLFile=changed |
PROP_XPowerOptOutputFile=changed |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_xilxPAReffortLevel=Standard |
Project duration(days)= |