SummaryTue Jul 13 04:52:56 2010


TSummaryNew
WARNING LIT:243 - Logical network XLXI_2933/XLXI_129/XLXI_3629/O has no load. 
WARNING LIT:395 - The above warning message is repeated 2 more times for the following (max. 5 shown): XLXI_2933/XLXI_129/XLXI_3630/O, XLXI_2933/XLXI_129/XLXI_3631/O To see the details of these warning messages, please use the -detail switch. 
INFO MapLib:562 - No environment variables are currently set. 
WARNING MapLib:701 - Signal REV_P connected to top level port REV_P has been removed. 
WARNING MapLib:701 - Signal REV_N connected to top level port REV_N has been removed. 
WARNING MapLib:701 - Signal SPA_P connected to top level port SPA_P has been removed. 
WARNING MapLib:701 - Signal SPA_N connected to top level port SPA_N has been removed. 
WARNING MapLib:701 - Signal REF_CLK_P connected to top level port REF_CLK_P has been removed. 
WARNING MapLib:701 - Signal REF_CLK_N connected to top level port REF_CLK_N has been removed. 
INFO LIT:244 - All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. 
WARNING PhysDesignRules:372 - Gated clock. Clock net xTARGET_TOP/xTARGET_TRIG/XLXN_403 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. 
WARNING PhysDesignRules:372 - Gated clock. Clock net xTARGET_TOP/xTARGET_TRIG/XLXN_404 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.