ROB-IN DESIGN REVIEW 2 (16-SEP-1997)
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(Last mod: 22-Sep-1997, R.Cranfield)


Points from detailed rob-in design review, 16-Sep-1997
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This is a list of questions, explanations and modifications arising
in the meeting. Starred and numbered items imply actions to be taken.

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*1) ALL schematic pages required (FIFOs, SRAM, test connector pinouts) --
to check e.g. are unused pins pulled up?

*2) General hardware description would be very useful.

*3) Register list would be very useful -- even before Mach logic design.

  STATUS:
18 address bits + stored status bits + other status bits are all
presented at the address of the used-page fifo. The "other" status
bits, which are dynamic (instantaneous), can also be read at another
address independent of the fifo.

*4) Are the dynamic status bits connected through? Do they clash with
used-fifo connections? (i.e. will it be necessary to cut fifo pins?)

*5) Add LDOWN to status register.
*6) LDERR should go into the input fifo.

  CONTROL:
*7) Add UTDO to control register.
*8) Add URESET to control register (requires a small handshake protocol
 -- see S-LINK spec -- could be hardware or software).

*9) XOFF should be RESET to XOFF (currently the opposite!).

  RESET:
"power-on" reset resets everything (S-LINK, 3 FIFOs, i960, MACH)
(input fifo read by MACH chip state machine -- uses same clock as
processor; flag changes with data).

*10) UDW[2] and URL[4] should be programmable via control register.

*11) Schematics should be numbered.

*12) Resistor values should be shown on schematics.
*13) Some busses look like single wires on page B.
*14) What is busname be10(1:0) on page B?

*15) Prefer active low indication via # behind names.

*16) LDERR should go into input fifo (along with dataword).
*17) Should check what is done with unused fifo pins (should be grounded
for all 3 fifos).

input_paf goes back into input fifo as bit 35 to keep record of when
fifo filled (almost-full cannot be used since the input fifo can no
longer be written into at this stage).

*18) Great care should be taken with LCLK (and ALL OTHER CLOCKS). Routing
should be serpentine rather than star. Termination should be at the
end rather than the middle. Should not go to HP Analyser test point in
production version (use a SLIBOX instead?).

How deep is input fifo? All 3 fifos are 1K.

*19) UXOFF# needs to be generated by nearly full input fifo as well as
control register and low free-page fifo.

rob-in must be able to handle S-LINK test data. This is sent by source
(cannot be triggered at destination end), and can be switched off by
UTDOUT. Note that LDOWN is ON while test data is being sent. Should be
ok, if start and end are recognised by Bit 30 only.

*20) If no S-LINK card is plugged in default should be LDOWN ON.

*21) Onboard clocks should be generated from PCI clock via a phase-lock
loop or similar (e.g. PLX), rather than SCLK (which was the older
recommendation). Only problem is that strictly this is not compatible with the
PCI spec, which allows the clock to vary -- but not a problem in
practice.

Is input fifo empty flag generated by ANDing both fifo flags? The
known problem with synchronisation of a pair of fifos is handled by
the MACH logic which looks at both flags.

Is there decoupling on 3.3V supply? Yes.

*22) Schematics should indicate whether board is PMC or PCI. (Note that
on PCI there is no BUSMODE, but 2 other lines, PRESENT1 and PRESENT2
specify required power as follows:
  PRESENT1  PRESENT2  Meaning
    open      open    no board
   ground     open    25W max
    open     ground   15W max
   ground    ground   7.5W max

*23) For PMC BUSMODE[1] should be a function of BUSMODE[4:2], not just
grounded.

*24) Check that pull-up/pull-down resistors have values as specified in
section 1.7 of "i960 RX I/O Processor Design Guide", and show values
on schematics.

*25) Decoupling of VCCPLL should be with 0.01uF/type X7R (not 0.1uF), as
specified in uP developer's manual. (Should be X7R type, which does
not go as high as 0.1uF).

*26) Should be a LED on FAIL pin.

*27) Suggested that DREQ# be connected to MACH (but not needed!).

*28) Comments should be used in MACH design files.

*29) Headers should be provided (author, function, mod list, date, etc).

What happens if BOB is in error? If hardware only looks at one bit,
every control word is either a BOB or an EOB, so system should not
hang.

*30) There should be a way to send input data down the drain e.g. by
holding the input fifo reset (might want to send data to rob-in as
fast as possible, with no XOFFs). Add a bit in the control register to
toggle this and choose how to implement.

MACH resources (MACH 512256):

100% usage! Not very nice, but cannot do anything at this stage --
a further version, using e.g. an FPGA or 2 MACHs will probaly take
6-12 months more.

Timing has not been simulated, but there are no multiple passes and
the chip delay should be =< 7ns.

*31) Be aware that connector on PCI board is only 36 pin, so can't use a
standard connector to an HP logic analyser -- will have to use
individual wires instead.

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