Minutes of ROB-IN meeting held at CERN on 20-Aug-1996

(G.J.Crone / R.Cranfield) -- converted to HTML 23-Oct-1996 GJC

Present

Owen Boyle Owen.Boyle@cern.ch
Bob Cranfield rc@hep.ucl.ac.uk
Gordon Crone gjc@hep.ucl.ac.uk
Barry Green B.Green@rhbnc.ac.uk
Robert McLaren Robert.Andrew.Mclaren@cern.ch
Giuseppe Mornacchi (Part time) g.mornacchi@cern.ch
John Strong J.Strong@rhbnc.ac.uk

Discussion of RoB-in URD

There was a long discussion of the RoB-in URD mainly based around the list of comments circulated by RC before the meeting.

The title of the document itself:

The suggestion to replace the word demonstrator with "RoB prototyping" was accepted.

References to external inputs/outputs vs. RoB controller:

OB said that he and RM had made a conscious decision to leave in the references to external components so as not to lose track of where they come from.

JS said that the RoB-in has a limited range of functions in response to messages from the RoB controller, we should define the interface between the RoB-in and the RoB controller not to external links.

RC suggested that "RoB-in = RoB - RoB-out", RM said basically yes.

RM said that RoB-in URD was longer lived than just this prototype.

JS said that he and RC had independently arrived at the same conclusion that the URD makes no reference to the role of the RoB controller.

RM stated that current RoB-in project will have all I/O through the RoB controller but this would not necessarily be true of the "final RoB-in".

JS suggested that the scope of the document is "Data buffer & related control".

RC stated that the current design document refers to a prototype of the thing described in the URD.

communication back to ROD:

RC asked isn't XOFF the only communication back to ROD?

RM said that there was the possibility of other control signals on the S-Link. People have suggested signals like "abort event" and "buffer nearly full (but not yet XOFF)". Suggests the prototype should have a couple of programmable bits for S-Link signals.

Event ID:

OB said this may not just go up by one it could be say a time stamp.

JS said we should require that the event ID increments by 1.

RM will check with Nick Ellis.

End of Event:

OB said that he understood there would be no end of event marker.

RM said the URD should say that it will comply with ROL spec (which currently does include an end of event marker).

JS said we should have one and it should be explicitly stated in the URD

UR DI-RATE:

JS suggested this should be specified as a table, plot or formula.

OB to speak to people and iterate again.

UR DI-FC:

"to prevent overflow" was accepted as a replacement for "in the event...full".

RM agreed that prototype won't implement L1_inhibit.

UR DI-EXP:

JS said this should be removed, it is not the RoB's responsibility L2 or L3 should process their own data.

RC expressed concern that if it were removed other people would think that it had been left out by mistake.

OB will re-word.

JS said it should state that if required it will be paid for by group making requirement.

Accept/Reject:

UR L2-BS:

RC asked if equation was meaningful since none of max, min or average is appropriate.

RM suggested changing wording to something like "An attempt to quantify buffer size"

UR L3-OUT:

OB agreed the current wording is ambiguous.

UR ERR-MON:

JS did not like "all kinds of errors" suggested a specific list or table.

UR ERR_DATA:

OB will add Unknown L3_REQ

In table 5 some actions are implementation specific some, like sending empty packet when data not found, are real URs.

UR ERR-REC:

Sentence about re-synchronisation will be removed. Phrase like "come up cleanly" will be added.

UR GBL-MON

JS said monitoring must introduce some latency, an acceptable amount should be quantified and the UR should limit to it.

UR CON-SIZE

May allow extra height for prototype. PMC only applies to prototype.

UR CON_POW & UR CON-COST:

Not applicable to prototype.

Comparison of URD and outline spec

OB suggested that the comments on the URD really came from comparison with outline design so the explicit comparison was not required.

Readout Link data format

RM showed a slide and distributed a note giving details of the proposed readout link data structure.

Hardware details

BG showed latest block diagram proposal. No serious problems/objections were raised. There was some discussion of PCI bridge options and choice of PowerPC board for development; JS mentioned the possibility of using PCs + LINUX for R&D. It was reported that the RHUL C40/PCI interface board (using the PLX bridge chip) was now designed, and the PCB was currently in manufacture.

Software details

GC had already gone through the operation of the current buffer-manager indexing scheme, in the URD discussion. There was a brief discussion of the software proposals put forward previously in notes by GC. GC also distributed draft versions of software documentation. No particular problems were foreseen, other than GM's query below:

GM asked why not use the PowerPC on the RIO2 to manage the buffer rather than a DSP on the RoB-in?

It was decided to make all resources on the RoB-in accessible from the PMC motherboard so that one could operate with or without the processor on the RoB-in doing the buffer management. i.e. the RoB-in would have a dual master bus.

GM suggested that it would be more difficult to integrate a RoB-in with an on-board CPU.

RC was of the opinion that it would make it easier!

Workplan:

The workplan originally prepared by RC/GC/BG was used as a starting point for discussion of the development timetable. There were no major objections to this timetable, but it was suggested that software development need not wait for processor choice. The hardware design start-point is largely constrained by other RHUL commitments (C40/PCI interface which gives relevant experience and demo_RoB work which is urgent). RC asked whether a Dec-1997 endpoint was early enough to fit in with the DAQ Prototype -1 plans. It was thought that this is probably ok, but it was pointed out that the length of the test/debug phase is hard to predict and 7 months may well be generous. Moreover some of the testing/debugging (e.g. PLX circuitry) could proceed earlier and independently. RC agreed to adjust the timetable accordingly.

Next Meeting:

The next meeting was pencilled in for Monday, 28-Oct-1996, at UCL. RC will confirm nearer to the date.