Memory size & organisation / FIFO width
Fragment buffer / program memory
The fragment buffer is now likely to be implemented as a pair of
256K x 16bit SRAM chips. Larger chips are not available with the
required access speed (< 12ns). Slower chips would require
introducing a wait state and latching the data in the MACH 5 PLD.
The program memory will be a single chip, probably the same size.
Free / used FIFOs
The free FIFO only needs to be wide enough to hold the page numbers
of free pages. If the fragment buffer is split into pages of 1Kbyte
the page numbers will occupy 10 bits.
The used FIFO needs to be wide enough to hold the address of the
last word written and at least 2 bits of status information. If
the address is stored in terms of 32bit words rather than bytes it
will take 18 bits. This gives us a minimum of 20 bits.
The free FIFO will be implemented as a single chip but the used FIFO
will need 2 chips.
GJC /
gjc@hep.ucl.ac.uk