ATLAS RoB-in project -- design issues

Processor options

Requirements

Processing power

The current implementation of buffer manager software, written in assembler and running on a ~15 MIP processor, just about manages the designed 100kHz event rate. The equivalent program in C ran at about half the speed, therefore to allow us to use C instead of assembler we need ~30 MIPs. However this is a minimal implementation without the monitoring and other requirements specified in the URD. In order to comfortably implement all functionality at the required rate, without resorting to coding in assembler, we should double this number again to give us a processor power requirement of ~60MIPs.

Power consumption

For a PMC module total power consumption is limited to 7.5W.

Chips consuming a large amount of power require heat-sinks which are a problem in terms of the physical size requirements.

Physical size

A PMC card is not very big!!

DMA

After some discussion we have decided that DMA capability is not required in the processor. The only place where DMA is desirable is in the PCI bridge.

The contenders

Quick comparison

Processor processing power (MIPS) power consumption physical size
C40 (60MHz) 30 1.75W 1.86"
C30 (60MHz) 30 ? 0.9"
SHARC (40MHz) 40 1.75W 1.428"
Am29040 (50MHz) 68.8 * 1.65W1.54"
i960 (RP) (33MHz) 31 * 3W 35mm
Pentium (100MHz) ? 10.1W 1.95"
Pentium (610=) (75MHz) ? 7.6W24mm
PowerPC 602 (66MHz) 40 ** 1.2W?
PowerPC 603 (80MHz) 75 ** 3.0W? ***
PowerPC 603e (100MHz) 120 ** 3.5W ?
IDT79R3051 (40MHz) 35 2.5W 1.195"
  *    Quoted as 'VAX MIPS'
  **   SPECint92
  ***  240 CQFP / 256 BGA 
  

Notes

Other considerations

Smaller chips may require a heat sink where a larger chip could dissipate enough heat without.

Chips packaged with a BGA may be more difficult to debug (hardware wise) because it is not obvious how you would attach logic analyser probes.

Processors such as the Cxx would be much simpler to integrate since we already have experience with the C40.

Processors such as the PowerPC would require a new debugging environment.

High clock speeds would make the design much more difficult in terms of routing of signals on the PCB.


Conclusions

Our choice

We have decided to use the i960RP as this seems to be the easiest from the hardware point of view. If we find that the processing power is really not enough for the job the newly announced i960RD (a clock doubled version of the i960RP) should give us the extra we need.
GJC (gjc@hep.ucl.ac.uk)