ROB-in Product Brief
(Last mod: 20-Apr-1998 / R.Cranfield)
Function
Block Diagram
Format
Purpose
Details
The function of the ROB-in module is to read in data from an LHC-like data
source and to buffer it for the duration of a second-level
trigger decision, making selected fragments available to the trigger
system as required.
The module is designed to be self-contained with a fully-featured
buffer manager integrated on-board. The buffer manager can be disabled
and the buffer hardware accessed from an external processor if
necessary to test alternative buffer manager algorithms.
The current version incorporates two standard protocols to fit
in with the other trigger/DAQ prototyping work: S-Link for front-end
input and PCI for all other communication, including data output and
message transfer.
Features include:
- 100 MBytes/sec front-end S-Link input
- Page-managed memory with configurable page size
- Accessible via PCI
- Integral buffer manager
- DMA output of event fragment data
- Conformance with ROB-in URD
- Diagnostics
- Programmable reset
- Error handling and diagnostics
"ROB-in Block Diagram" (B.Green)
The board will be available in two formats: a PCI card that can plug
directly into a PCI backplane slot, and a PMC format card for use with
a baseboard, e.g. a RIO2 acting as ROB controller.
The board's primary purposes are to provide a realistic input
component for prototyping studies in the developing ATLAS DAQ/trigger
readout systems and to help form the basis of the eventual ATLAS ROB
design. The board is a natural development of an earlier prototype ROB
used for various Level-2 trigger tests and demonstrations, taking note
of the various "standards" that are now emerging. The main features of
the upgrade are conformance with the newly published ROB URD and the
use of S-Link and PCI protocols. User requirements for the board have
been spelt out in its own ROB-in URD.
Data input
Event-fragment data is received on an S-LINK LDC interface
connection from a "ROD" source at an average rate of up to 100
MBytes/sec
and written directly into "pages" of buffer memory using addresses
taken from a "free-page FIFO".
The length of pages is adjustable in the hardware logic.
At the end of each page, or at the end of each event-fragment, the
last address used is written to a "used-page FIFO" along
with status bits; one of these is used to indicate the last page
of the event-fragment. The address logic
then reads the next value in the free-page FIFO as a base for
addressing the subsequent page.
Under certain circumstances an XOFF signal back to the ROD is
generated on the S-LINK interface in order to stem the flow of
data. This occurs automatically whenever the number of entries
in the free-page FIFO drops below a programmable threshold, or when
the ROB-in is powered up or reset. XOFF is also asserted when the input
FIFO reaches the half-full state.
Access to buffer memory
Access to the buffer memory is multiplexed between the
front-end input and the ROB-in processor. Both read and write
access are allowed from the processor side.
Buffer management
The tasks of the built-in buffer manager are:
- to service the free-page and used-page FIFOs
- to index the event-fragments
- to receive event-fragment-data requests (for RoI data,
monitoring data and Event Filter data) and provide the requested data if
possible
- to receive event release messages and make the relevant data pages
available for re-use (by putting them in the free-page FIFO)
- to monitor, record and report error conditions
- to be able to reset the buffer hardware and carry out appropriate
test procedures on request
The buffer-manager software is based on principles employed in the previous
prototype:
- input sources are polled and serviced in turn
- event-fragments are indexed in a simple cyclical lookup
scheme according to the low order bits of the event-ID
PCI communications
Apart from the front-end data input, all communication takes place in
PCI address space.
Communication with the on-board processor, including the transfer of data
destined for Level 2 and Event Filter, is achieved through the use of
circular buffers (software fifos) at user-definable locations.
Message history
The use of software fifos for message passing automatically provides
a "history window" of the most recent messages.
Error handling
Various kinds of errors specified in the ROB-in URD are detected
and counted for later interrogation and/or reporting.
Diagnostics
The on-board processor can be used to check the buffer memory. It can
also test the operation of the buffer by writing directly into the
input FIFO.
Software controllable LEDs and probe points are provided for diagnostic
purposes.