Change Log: 5d 20/06/24: Forced FFTV disable reg bit (reg 0x9c DEBUG_CTL=0x1000) -------------------- 2 0 2 4 ----------------------------------------------------------------- 5c 03/03/23: ?? 5b 21/02/23: Debug mode switch = 2 sets board to reset to RunMode for PRO-ANUBIS -------------------- 2 0 2 3 ----------------------------------------------------------------- 5a 9/06/16: Changed to using PULLDOWN primitives (using real resistors works!) Reverted to single stage 100us TTCrx reset 59 8/06/16: trying driving 1s instead of 0s 58 8/06/16: added two stage reset - to keep output driven longer than ttcrx reset 57 8/06/16: added tristate to subAddr, Dout lines - drives 0 are ttcrxreset. removed double reset. 56 8/06/16: made ttcrx_reset a double pulse, defaulted I2C lines to Z at init 55 8/06/16: fixed trx_reset inversion to i2c_reset 54 8/06/16: Added trx_reset to i2c_reset 53 8/06/16: Trying a stretched trx_Resetb pulse 52 6/06/16: v52 AGAIN, oops. Added ttype_strb to BO, and made all rod_busy LEDs flash when asserted -------------------- 2 0 1 6 ----------------------------------------------------------------- 52 26/11/15: undid below, now trying 4x faster i2c clock - fix 3F/ttcrx problem? 51 26/11/15: used not-clock for I2C clock gen - did not fix 3F/ttcrx problem :-( 50 27/07/15: Added FFTV-T BEmerg match counter readback: reg 113(0xe2) 4f 24/07/15: Added FFTV-T BEmerg timeout/leaky bucket - set n seconds in reg 112(0xe0) 4e 12/06/15: Moved all pipelines downstream of FFTV and other logic 4d 11/05/15: re-added 5b FFTVB, fixed busy/emergency counters and action 4c 11/05/15: Added FVB_COUNT and FVB_ID reset on write function 4b 11/05/15: Increased FVB_MATCH to 5 active bits. FFTV-B match level goes to 31 now 4a 30/04/15: changed clk debug options to BO=TTCrx_BCntRes, TRO=TTCrx_L1Accept 49 23/04/15: Added FFTVB decrement by 2 option reg 0x46(CONTROL) bit 0 48 22/04/15: fixed strobes on debnug and adde ttcclkdet 47 22/04/15: re-added chipscopt (doh!) 46 22/04/15: changed to Martins strobe handling, added more fp debug 45 20/04/15: fixed strobe handling bug 44 20/04/15: Changed the TTCrx B/EvCnt Strobe handling ... 43 16/04/15: Added L1IDnonconseq output on TRIO - set DEBUG_CTL,10 to enable 42 14/04/15: Snapshot mode now smarter and coupled to busy 41 14/04/15: Fixed no busy counter bug Added BCID snapshot check registers Added FFTVB counters registers 40 12/4/15: Moved to v40 to avoid confusion with TIM hardware IDs changed SEQ to allow src and sink sizes to be specified at build time changed NREG to 128, added new FVB registers 80-85 added fftvb_emergency to status3 reg, bit 12. 39 31/3/15: ttc sigs sample clock select option added. Bits 9:8 of reg_ttc_select control whether clk, clkn, TTCCLK, TTCCLKn are used to clock ttcrc sigs in 3a 1/4/15: Added non-conseq id debug. getting ready for chipscope NOTE there is no SEQUENCER in this build - makes room for CS 3b 10/4/15: CS version still Added piplelines to EVS and TTS FFTV-B included too! 3c 10/4/15: Added clocking the internal sigs in mixer_rtl.vhd to help make time Similar for output of FFTVb state machines 3d 10/4/15: Added clocking pre_trg and SAsigs in samod_rtl.vhd 38 17/12/14: Again - works this time! 37 15/12/14: added FFTV pre_under stuff for IBL 36 4/12/14: test with fftv min and max period unswapped 35 4/12/14: post-mortem buffer setup as rolling window, stops on fftv emergency 34 4/12/14: added emergencies to busy, so triggers get stopped in emeregency too 32 1/12/14: Bug fix bEmergency on l1a_fast too. 31 28/11/14: Emergency on multiple FFT busies with same freq 30 26/11/14: Busy duration fixed at 25us 2f 21/11/14: Busy duration fixed at 6us 2e 20/11/14: jumpers changed PL202 now selects IBL FFTV vs SCT 2d 20/11/14: made ibl jumper force to ibl mode fftv enabled, regardless 2c 20/11/14: added busylen = ff period x16, used busy_end to clear match_count 2b 19/11/14: ibl mode enable jumper on PL202, fix ible max freq to 40kHz 2a 18/11/14: added fftv ibl mode bit (reg 9c,11), to change to use IBL freq range 29 17/11/14: fix veto-len bug (was 40, should be 40000) 28 13/11/14: Mod FFTV for IBL range changed to 2kHz-30kHz (was 15-470kHz) 26 21/03/12: Fixes FFTV vetoing TTC trigger. Also new delay elements for TTC-L1A/BCR/ECR signals 23 Attempts to stop the FFTV vetoing ttcl1a when used via the pipeline (sa_ttcl1a_en) 20 15/04/09: Allowed ECR-ID reseting in Runmode 16/06/09: Reworked TTC signals clocking-in to fix wrong ttype bug (didn't) 20/12/09: Reverted to original TTC, changed TTC sig-in clock to clk (needs more testing) 1F 10/10/08: Fixed fast sigs out clocking bug 1E 6/10/08: Fixed double ECR bug when delayed 1D 26/09/08: Added ECR pipeline etc (using BCR pipline control sigss) Bypassed all deadtiming etc in runmode 1C 20/06/08: Preset vRodBusy at reset 1/07/08: Allowed writing of TTID(9:8) while in runmode 10/07/08: Reduced latency in pipeline 22/07/08: Released. 1B 10/06/08: Fixed IntTrig always random bug 12/06/08: Added option to delay BCR in a pipeline 16/06/08: Released. 1A 29/08/07: slow TTCrx/I2C clock to 10kHz (was 600-1200!!) 31/08/07: Added bcid_max_en for 0xFFF BCID rollover mode 23/10/07: split spare_bus, adding spare_bus15 for debug use. Added debug mode control for using m=1 to get vmewr from spare_bus15 5/12/07: fixed latch registers to also spot glitches (in spreadsheet). Updated reg discription 12/12/07: fixed ttc-ttype to use sattype bits <9:8> 08/05/08: fixed bcidoffset rollover from 3564 to 3563. 09/05/08: added bcidoffset 11:4 bits 19/05/08: Moved to FA8.1 ... hopefully ;-) Fixed ext_rodbusy not connected bug 21/05/08: Moved all bcidoffset bits to new bcidoffset register with compat with original too 19: : Corrected BCR timing for correct BCID