f2_vhdl Project Status (04/02/2015 - 11:06:46)
Project File:	f2_vhdl.ise	Current State:	Programming File Generated
Module Name:	f2_pcb_top	Errors:	No Errors
Target Device:	xc2s600e-7fg456	Warnings:	793 Warnings
Product Version:	ISE 10.1.03 - Foundation Simulator	Routing Results:	All Signals Completely Routed
Design Goal:	Balanced	Timing Constraints:	X 1 Failing Constraint
Design Strategy:	Xilinx Default (unlocked)	Final Timing Score:	104480

 

f2_vhdl Partition Summary				[-]
No partition information was found.

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	3,687	13,824	26%
Number of 4 input LUTs	3,436	13,824	24%
Logic Distribution
Number of occupied Slices	3,817	6,912	55%
Number of Slices containing only related logic	3,817	3,817	100%
Number of Slices containing unrelated logic	0	3,817	0%
Total Number of 4 input LUTs	4,663	13,824	33%
Number used as logic	3,436
Number used as a route-thru	699
Number used as Shift registers	528
Number of bonded IOBs
Number of bonded	277	325	85%
IOB Flip Flops	212
Number of Block RAMs	64	72	88%
Number of GCLKs	3	4	75%
Number of GCLKIOBs	3	4	75%
Number of BSCANs	1	1	100%

 

Performance Summary				[-]
Final Timing Score:	104480	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	X 1 Failing Constraint

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Thu Apr 2 11:04:17 2015	0	698 Warnings	31 Infos
Translation Report	Current	Thu Apr 2 11:04:58 2015	0	5 Warnings	0
Map Report	Current	Thu Apr 2 11:05:05 2015	0	86 Warnings	1 Info
Place and Route Report	Current	Thu Apr 2 11:06:39 2015	0	4 Warnings	0
Static Timing Report
Bitgen Report	Current	Thu Apr 2 11:06:45 2015	0	57 Warnings	0

Date Generated: 04/02/2015 - 11:06:46