"$Id: pld2.src,v 1.29 2001/11/14 20:10:51 warren Exp $
"==============================================================================
#TITLE	 'SCT TIM PLD2: Stand-Alone Signal Gen/Timing';
#ENGINEER 'Martin Postranecky / Dominic A Hayes / Matthew Warren';
#COMPANY	 'University College London';
#COMMENT	 '	 ';


"==============================================================================
"$Log: pld2.src,v $
"Revision 1.29  2001/11/14 20:10:51  warren
"improved rantrig, testbusy, timing, trigrig_win. Issues with latch-up
"
"Revision 1.28  2001/10/05 11:34:07  warren
"Rework of delayed TRIG hierachy/logic
"Rework of input logic/sync (no more pulsars)
"Added clocking to output signals
"
"Revision 1.27  2001/10/02 12:29:11  warren
"no change -- just getting dates good in CVS
"
"Revision 1.26  2001/09/11 16:28:06  warren
"removed new changes -- so no change should show
"
"Revision 1.25  2001/09/06 10:38:59  warren
"Reworked all code, with new busy system and CAL state-machine
"Seen to send cals with proper trig, and cal bursts
"
"Revision 1.24  2001/08/30 12:18:44  warren
"combined some combined some FER/ECR code
"tidied, rename, updated
"
"Revision 1.23  2001/08/08 18:40:20  warren
"signal name upper/lower case standardization
"
"Revision 1.22  2001/08/03 09:12:25  warren
"finalised inverting signals, and ensured worked as before
"improved stm
"
"Revision 1.21  2001/08/02 14:53:33  warren
"improved a liiiiiiittle
"
"Revision 1.20  2001/08/02 14:42:51  warren
"don't want to loose it
"
"Revision 1.19	 2001/07/27	17:40:33	 warren
"better layout
"
"Revision 1.18	 2001/07/24	10:04:04	 warren
"new simulation
"
"Revision 1.17	 2001/07/23	11:18:30	 warren
"renamed	signals with proper polarity n prefixes and removed LOW_TRUEs
"
"Revision 1.16	 2001/07/19	10:44:13	 warren
"removed	unused spare bus lines
"
"Revision 1.15	 2001/07/16	13:13:31	 warren
"*** empty log	message ***
"
"Revision	1.14	2001/06/05 10:33:23	warren
"Added pulser	the test_sw	input	(fp TRIG)
"	"Revision 1.13	 2001/04/25	19:01:53	 warren
"removed	the	testpin outputs -	not needed and	may be messing	up	clocks
"
"Revision 1.12	 2001/04/03	15:43:19	 warren
"Changed	from nOA_rst to OA_rst
"


"==============================================================================
"Receives:
"			  BC_RESET	 FE_RESET	 TRIGGER	 CALIBRATE	 ECR	 SPARE
"Modified:
"---------
"29mar00	enc_TRIG	output added (= SATRIG).
"31mar00	regs 00,	02, 0A added.
"04apr00	29mar00 mod	removed.
"05apr00	vina..f replaced with actual name, eg vBCR/v_BCR.
"			same for	extIn_a..f and	intIn_a..f (internal	pulsed versions)
"22may00	DelaySelect[7..0] removed	from .pi	file.
"24may00	enintSpare,	intInSpare,	intSpare	removed.
"			name:	RodBusy -> rod_crate_BusyOut,	SetToRunMode -> RunMode, SAClkDelay
"			->	CT.
"05jun00	entestbusy,	clrtestbusy	added	to	register	02	voaReset	moved.
"06jun00	OA_reset	removed.
"			testbusyON circuit added.
"07jun00	EclExt_Clk split int	1 & 2.
"			extbusy split into Nim and	Ecl flavours.
"			int_clk split into 2.  int_clk1 feeding clock circuit	int_clk2	feeding
"			count	in	busy2.
"				(fiTTing	problem with PT clk and	CE) int_clk	i/p to both	pins.
"08jun00	clk3 -> clk2b.
"03jul00	StartSink, StartSeq o/ps added.
"			Reg00	reordered.
"05jul00	enTRIGWin -> enWindow, enIntRptTRIG	->	enIntTRIG, enIntRan -> enRandom
"			enWindow	made an o/p.
"			new reg02 bit and	o/p vRodBusy.
"11jul00	OA_reset	reinstated.
"26sep00	nOA_rst INPUT now	LOW_TRUE.  Ooops!
"04oct00	Added	CLK_EN_BY (and	tidied write logic) for	reg 00,02,0A -	MRMW
"02Nov00	Fixed	up	nOA_rst discrepencies on registers
"03Nov00	Changed Register 00 bit	0 to be 1 on reset -	this involved spliTTing
"				the reg.	MRMW
"27Dec00	in	FUNC pulser chnged	'reset' to 'nOA_rst_' for legabilty.
"			Changed naming	in	Shift144	func to match their non-loCAL	signals (
"			Fixed	probable	inversion of nOA_rst	issues in:
"				-rst_pulse (in	FUNC pulser)
"				-q1 in SYNC	TRIG
"				-srclr
"28Dec00	Added	nodes	ext_BCR,	int_BCR that incorp.	Enables and	Nim/ECR combining
"			 for much more	ledgible	code.
"05Jan01	Removed lev2pulse	from voaReset - not needed?
"08jan01	added	test lines to sgbA for MP
"02Feb01	Sorted out sreset	(was wrong TRUE) MP,	MRMW
"			nOA_rst input is TRUE and the	signal is negative going logic on the pld
"			- MP,	MRMW
"12Feb01	Reset	(rst_pulse)	in	pulser: Added  ...	AND /RunMode ... for
"			extra	delay	MP, MRMW
"			changed TestBusyONreset	func to OR /EnTestBusy -  this should provide
"			proper enable	MP, MRMW
"14Feb01	In	q_SATRIG	func changed NOTed the Disable_TRIG	sig.
"15Feb01	Added	code for	better simulation	of	pulser	converter:
"			sim_level_2_pulse	MRMW
"21Mar01	Cleaned up nOA_rst legibity (added OA_rst	= /nOA_rst)
"24Apr01	Removed all	test points	and associated	code for	watch	vTRIG	etc.
"04Jun01	Added	pulser to test_sw, creating sw_TRIG.
"23Jul01	Renamed q1 to qStop_Clk
"			Renamed q0 to qenDeadTimerCAL
"03Aug01 Removed Stop_Clk and related logic.
"16Aug01	Added enIntFER = enIntFERx or enIntECR to enable osc in both cases
"			 The bit in the enables reg is now enIntFERx.
"28Aug01 Total rework and simplification of signals -- no enSig,enDeadTimer etc
"04Sep01	CAL state-machine added -- CALTRIG and and Bursts are run using this
"14Sep01 Reworked hierachy system to not affect undelayed TRIGs
"        This also implied that TRIG inputs would not be gated by the OA_busy
"         and TRIG imputs would not gate other input signals
"02Oct01 Signals are all clocked prior to leaving the PLD, at the output pin.
"03OCt01 Rework of signal flow and sync. All ext, vme, and async sigs now clock
"			 FFs that are reset by the OR of all SYNCed signals. This allows a 2 FF
"			 SYNC. TRIGS are not grouped with the other sigs, but work the same way.
"05Oct01 Added TRIG pipeline flushing if delay register is written to!
"12Nov01 i/p sig FF now hold level as a busy until a doneSIG issued.
"        other FFs not in the sig group are async disabled on signal reception.
"         danger here is that 2 sigs at exactly the same time will kill BOTH
"			Delayed trigs to not contribute to input signal inhibits


"-------------------------------------------------------------------------------
"PROCEDURE shift144
"-------------------------------------------------------------------------------
"CALled by procedure	sync_TRIGger.
"operates as a	128 +	16	shift	register	with selectable output.


PROCEDURE	shift144	(
					INPUT		outTRIG_,		"serial data from	sync'd TRIGger.
								DelaySelect_[7..0],	"8bit	selection from	TRIG delay register.
								clk2b_,			"clock from	delay	line 3.
								srclr_,			"sr reset.
								enDTRIG_;
								
					OUTPUT	outTRIGh_,		"was	shift_out_a,
								outTRIG1_	);	"was	shift_out_b



	NODE		serial_in; " added only	for legibilty,	reduces to zilch
				serial_in =	outTRIG_;


	NODE		shift_a[128],
				shift_b[16]
					CLOCKED_BY clk2b_
					RESET_BY	srclr_;

				shift_a = [shift_a[126..0],serial_in];


	NODE		selected_bit_a,
				selected_bit_b,
				shift_out;

	CASE DelaySelect_[7..4]
		WHEN 0 => selected_bit_a =	serial_in;
		WHEN 1 => selected_bit_a =	shift_a[15];
		WHEN 2 => selected_bit_a =	shift_a[31];
		WHEN 3 => selected_bit_a =	shift_a[47];
		WHEN 4 => selected_bit_a =	shift_a[63];
		WHEN 5 => selected_bit_a =	shift_a[79];
		WHEN 6 => selected_bit_a =	shift_a[95];
		WHEN 7 => selected_bit_a =	shift_a[111];
		WHEN 8 => selected_bit_a =	shift_a[127];
	END CASE;

	shift_b = [shift_b[14..0],	selected_bit_a];


	CASE DelaySelect_[3..0]
		WHEN	0 => selected_bit_b = selected_bit_a;
		WHEN	1 => selected_bit_b = shift_b[0];
		WHEN	2 => selected_bit_b = shift_b[1];
		WHEN	3 => selected_bit_b = shift_b[2];
		WHEN	4 => selected_bit_b = shift_b[3];
		WHEN	5 => selected_bit_b = shift_b[4];
		WHEN	6 => selected_bit_b = shift_b[5];
		WHEN	7 => selected_bit_b = shift_b[6];
		WHEN	8 => selected_bit_b = shift_b[7];
		WHEN	9 => selected_bit_b = shift_b[8];
		WHEN 10 => selected_bit_b = shift_b[9];
		WHEN 11 => selected_bit_b = shift_b[10];
		WHEN 12 => selected_bit_b = shift_b[11];
		WHEN 13 => selected_bit_b = shift_b[12];
		WHEN 14 => selected_bit_b = shift_b[13];
		WHEN 15 => selected_bit_b = shift_b[14];
	END CASE;

	outTRIGh_ =	selected_bit_a AND enDTRIG_;
	outTRIG1_ =	selected_bit_b AND enDTRIG_; 

END shift144;



"-----------------------------------------------------------------------
" FUNCTION PulseTrap
"-----------------------------------------------------------------------
"Take async signal and holds it until reset


FUNCTION PulseTrap	( INPUT signal, clr);

		NODE	q1
					CLOCKED_BY signal
					RESET_BY	clr;
				q1 = 1;

	RETURN 	q1;

END PulseTrap;



"------------------------------------------------------------------------------
"PROCEDURE SYNC
"------------------------------------------------------------------------------
"Uses	a set	of	2 flip-flops used	to	synchronise	the input clock signals
"	and 1 more to generate a single pulse only

"-------------------------------------------

FUNCTION SYNC	( INPUT signal, en, clk, clr);


	NODE		q1
					CLOCKED_BY clk
					CLOCK_ENABLED_BY en
					RESET_BY q4 OR clr;

	NODE		q2
					CLOCKED_BY clk
					RESET_BY clr;

				q1	= signal;
				q2	= q1;
				
				

	NODE		q4
					CLOCKED_BY q2
					RESET_BY /signal OR clr;
				q4 = 1;
				
	RETURN	q2;

END SYNC;



"===============================================================================
"
"
"	M A I	N	  B O	D Y
"
"
"===============================================================================

INPUT		nOA_rst;							"Low_True Board reset.
NODE		OA_rst;
			OA_rst =	/nOA_rst;

INPUT		sReset;

INPUT		clk2,	clk2b,
			int_clk1, int_clk2,
			enRodBusy,	rod_crate_BusyOut, TRIG_win, Disable_TRIG,
			eclExtBusy,	NimExtBusy,	enCALBurst;	"enCount	from PLD3

INPUT		Burst_Ready;		  "from PLD3, ***	was Burst_Busy

OUTPUT	BusyOut,
			outTRIGh,
			outTRIG,
			outTRIG1,
			MExtBusyOut;

NODE		OA_busy;
OUTPUT	nOA_busy;
			nOA_busy	= /OA_busy;

OUTPUT	intBusy;
			intBusy = OA_busy;

OUTPUT	RunMode,	SAMode;

OUTPUT	enWindow;

"===============================================================================
"
" RESETS
"
"===============================================================================
""Uses	counter to ensure	OA_reset	is	8x25ns duration


			NODE		vOAreset;	"reg02

			NODE		OA_reset_set;
						OA_reset_set =	sReset OR vOAreset;


			NODE		reset_count8
							DEFAULT_TO 1;


			NODE		qReset					"this	flip_flop is OA_reset, but	for clarity	...
							CLOCKED_BY	OA_reset_set
							RESET_BY		reset_count8;
						qReset =	1;


			NODE		reset_timer[4]
							CLOCKED_BY int_clk2
							CLOCK_ENABLED_BY qReset
							RESET_BY	reset_count8;

						reset_timer	= reset_timer .+.	1;		"make	NODE into a	counter

			CASE (reset_timer)									"set counter roll-over value
				WHEN 8 => reset_count8 = 1;					"used	to	reset	qReset
				ELSE		 reset_count8 = 0;
			END CASE;



OUTPUT	OA_reset,	"resets to other plds etc
			nOA_reset;

			OA_reset	 =	qReset;
			nOA_reset =	/qReset;




"===============================================================================
"
" REGISTERS	and VME Access
"
"===============================================================================


"-------------------------------------------------------------------------------
" VME	control signals
"-------------------------------------------------------------------------------


INPUT		bWriteb,
			bReadb,
			Reg00,
			Reg02,
			Reg0A,
			nLEb2;

BIPUT		db[15..0]
				ENABLED_BY dboe;
NODE		dboe;


"-------------------------
" Register 00 - Enables
"-------------------------

NODE		Register00high[15..1]
				CLOCKED_BY nLEb2
				CLOCK_ENABLED_BY (bWriteb AND	Reg00)
				RESET_BY	OA_rst;

NODE		Register00bit0		" This bit resets	to	1 (preset),	so	sep from	reg
				CLOCKED_BY nLEb2
				CLOCK_ENABLED_BY (bWriteb AND	Reg00)
				PRESET_BY OA_rst;


			Register00high[15..1] =	db[15..1];	"VME WRITES	to	Registers.
			Register00bit0			 =	db[0];		"needs to use split reg	here



"-------------------------
" Register 02 - Commands
"-------------------------


NODE		RegisterCommand[15..0]
				CLOCKED_BY nLEb2
				CLOCK_ENABLED_BY (bWriteb AND	Reg02)
				RESET_BY	OA_rst;

			RegisterCommand[15..0]	= db[15..0];

OUTPUT	vBurstGo, vBurstMode, vRodBusy;


			RunMode = RegisterCommand[12];		"setRunMode
			SAMode =	/RunMode;


"-------------------------
" Register 0A - Delays
"-------------------------

NODE		RegisterDelay[15..0]
				CLOCKED_BY nLEb2
				CLOCK_ENABLED_BY (bWriteb AND	Reg0A)
				RESET_BY	OA_rst;

			RegisterDelay = db;


OUTPUT	CT[5..0];
			CT[5..0] = RegisterDelay[13..8];

NODE		DelaySelect[7..0];
			DelaySelect[7..0] = RegisterDelay[7..0];




"-------------------------------------------------------------------------------
" Register Reads logic (write is controled by clock_enables)
"-------------------------------------------------------------------------------

			IF	(bReadb)	THEN

				IF	(Reg00) THEN
					db[15..1] =	Register00high[15..1];
					db[0]		 =	Register00bit0;

				ELSIF	(Reg02) THEN
					db	= RegisterCommand[15..0];

				ELSIF	(Reg0A) THEN
					db	= RegisterDelay[15..0];

				END IF;

			END IF;

			dboe = bReadb AND	(Reg00 OR Reg02 OR Reg0A);




"-------------------------------------------------------------------------------
"TESTBUSYON
"----------
" *** not been checked for rework yet

NODE		EnTestBusy,	ClrTestBusy;

			[	EnTestBusy,			"EnTestBUSY
				ClrTestBusy,		"ClrTestBUSY
				voaReset				"voaRESET
			] =  RegisterCommand[13..15];


OUTPUT	TestBusyON
				CLOCKED_BY syncTRIG
				RESET_BY	TestBusyONreset;
			TestBusyON = 1;

NODE		TestBusyONreset;
			TestBusyONreset  = ClrTestBusy OR /EnTestBusy OR OA_rst;


"==============================================================================
"
" CLOCKs
"
"==============================================================================

INPUT		NimExt_Clk,
			EclExt_Clk1,
			EclExt_Clk2;


NODE		Ext_Clk;
			Ext_Clk = (NimExt_Clk OR EclExt_Clk1 OR EclExt_Clk2);


NODE		enIntClk,	"Reg00
			enExtClk;	"Reg00

			enIntClk	= Register00bit0;
			enExtClk = Register00high[8];

NODE		selected_clk;


			IF	(enIntClk AND enExtClk)	THEN
				selected_clk =	Ext_Clk;

			ELSIF	(enIntClk)	THEN
				selected_clk =	Int_Clk1;

			ELSIF	(enExtClk)	THEN
				selected_clk =	Ext_Clk;

			END IF;



OUTPUT	clkIn;
			clkIn	= selected_clk;



"==============================================================================
"
"SIGNALS
"
"==============================================================================


NODE		doneBCR,
			doneDTRIG,
         doneCALP,
			doneECR,
			doneFER,
			doneSpare
				CLOCKED_BY clk2
				RESET_BY OA_rst;
				
NODE		doneTRIG;

NODE		doneCAL				"Generated in state machine
				DEFAULT_TO 0;  


NODE		doneALLxT;
			doneALLxT =    doneDTRIG    
							OR doneCAL
							OR doneBCR
							OR doneECR
							OR doneFER
							OR doneSpare
							OR OA_rst;

NODE		busyTRIG, busyCAL, busyBCR, busyECR, busyFER, busySpare;

NODE		busyDTRIG
				CLOCKED_BY syncDTRIG
				RESET_BY doneDTRIG OR OA_rst;
			busyDTRIG = 1;

NODE		busyRTRIG;	"busy for Real Trig (as opposed to a Cal-Trig
			busyRTRIG = busyDTRIG AND /busyCAL; "busy Real TRIG ie. not CAL_TRIG

NODE		busyCALP  			"Generated in state machine
				DEFAULT_TO 0;


NODE 		TRIG_winClosed;
			TRIG_winClosed = (/TRIG_win AND enWindow);




"TEST SWITCH                                              
"----------------------------------                       
                                                          
INPUT		test_sw;		"FP TRIG	push-button                 
NODE		sw_TRIG;                                         
			sw_TRIG = PulseTrap(test_sw, doneTRIG OR OA_rst);
      
      
      
"VME SOURCES (no enables)
"------------------------
NODE		vTRIG, vCAL, vBCR, vECR, vFER, vSpare;

			[vTRIG, vECR, vBCR, vCAL, vFER, vSpare] = RegisterCommand[1..6];


NODE		v_TRIG, v_CAL, v_BCR, v_ECR, v_FER, v_Spare;

			v_TRIG	= PulseTrap(vTRIG,  doneTRIG OR OA_rst);
			v_CAL		= PulseTrap(vCAL,   doneALLxT);
			v_BCR		= PulseTrap(vBCR,   doneALLxT);
			v_ECR		= PulseTrap(vECR,   doneALLxT);
			v_FER		= PulseTrap(vFER,   doneALLxT);
			v_Spare	= PulseTrap(vSpare, doneALLxT);



"EXTERNAL SOURCES	(enabled	by	pair)
"----------------------------------

INPUT		extInBCRNim, extInFERNim, extInTRIGNim, extInCALNim, extInECRNim, extInSpareNim;
INPUT		extInBCREcl, extInFEREcl, extInTRIGEcl, extInCALEcl, extInECREcl,	extInSpareEcl;


NODE		extTRIGNim, extCALNim, extBCRNim, extECRNim, extFERNim, extSpareNim;

			extTRIGNim	= PulseTrap(extInTRIGNim,  doneTRIG OR OA_rst);
			extCALNim	= PulseTrap(extInCALNim,   doneALLxT);
			extBCRNim	= PulseTrap(extInBCRNim,   doneALLxT);
			extECRNim	= PulseTrap(extInECRNim,   doneALLxT);
			extFERNim	= PulseTrap(extInFERNim,   doneALLxT);
			extSpareNim = PulseTrap(extInSpareNim, doneALLxT);


NODE		extTRIGEcl,	extCALEcl, extBCREcl, extECREcl, extFEREcl, extSpareEcl;

			extTRIGEcl	= PulseTrap(extInTRIGEcl,  doneTRIG OR OA_rst);
			extCALEcl	= PulseTrap(extInCALEcl,   doneALLxT );
			extBCREcl	= PulseTrap(extInBCREcl,   doneALLxT );
			extECREcl	= PulseTrap(extInECREcl,   doneALLxT );
			extFEREcl	= PulseTrap(extInFEREcl,   doneALLxT );
			extSpareEcl	= PulseTrap(extInSpareEcl, doneALLxT );


NODE		ext_TRIG,  ext_CAL,  ext_BCR,  ext_ECR,  ext_FER,  ext_Spare,
			enExtTRIG, enExtCAL, enExtBCR, enExtECR, enExtFER, enExtSpare;

			enExtTRIG 	= Register00high[9];
			enExtECR  	= Register00high[10];
			enExtBCR  	= Register00high[11];
			enExtCAL 	= Register00high[12];
			enExtFER 	= Register00high[13];
			enExtSpare	= Register00high[14];

			ext_TRIG		= (extTRIGNim	OR	extTRIGEcl)	 AND enExtTRIG;
			ext_CAL		= (extCALNim	OR	extCALEcl)	 AND enExtCAL;
			ext_BCR		= (extBCRNim	OR	extBCREcl)	 AND enExtBCR;
			ext_FER		= (extFERNim	OR	extBCREcl)	 AND enExtFER;
			ext_ECR		= (extECRNim	OR	extECREcl)	 AND enExtECR;
			ext_Spare	= (extSpareNim	OR	extSpareEcl) AND enExtSpare;


"ONBOARD	SOURCES (each has	enable)
"---------------------------------

INPUT		intInTRIG, intInRan, intInBCR, intInECR, intInFER;

OUTPUT	intTRIG;
			intTRIG = intInTRIG;

NODE		intTRIG2, intRanTRIG, intBCR, intECR, intFER;

			intTRIG2		= PulseTrap(intInTRIG, doneTRIG OR OA_rst);
			intRanTRIG	= PulseTrap(intInRan,  doneTRIG OR OA_rst);
			intBCR		= PulseTrap(intInBCR,  doneALLxT);
			intECR		= PulseTrap(intInECR,  doneALLxT);
			intFER		= PulseTrap(intInFER,  doneALLxT);
                                                             
                                                             
NODE		enIntBCR, enIntECR, enIntFERx;	"new x for combined with ECR sig
OUTPUT	enIntFER, enIntTRIG,	enRandom;

			enIntTRIG = Register00high[1];
			enIntECR	 = Register00high[2];
			enIntBCR	 = Register00high[3];

			enRandom	 = Register00high[4];
			enIntFERx = Register00high[5];"note x: new: enInFer now = ...x OR enIntECR
			enWindow	 = Register00high[6];


			enIntFER = enIntFERx OR enIntECR; "This needed as FER and ECR share osc.

NODE		int_BCR,	int_FER,	int_TRIG, int_RanTRIG,	int_ECR;

			int_TRIG	= (intTRIG2 AND enIntTRIG AND /enRandom) OR (intRanTRIG AND enRandom);
			int_BCR  =  intBCR AND enIntBCR;
			int_ECR  =  intECR AND enIntECR;
			int_FER  =  intFER AND enIntFERx;






"COMBINED SIGNAL
"----------------


NODE		asyncTRIG, asyncCAL, asyncBCR, asyncECR, asyncFER, asyncSpare;

			asyncTRIG  = 	(ext_TRIG  OR int_TRIG OR v_TRIG OR sw_TRIG);
			asyncCAL   = 	(ext_CAL               OR v_CAL);
			asyncBCR   = 	(ext_BCR	  OR int_BCR  OR v_BCR);
			asyncFER   = 	(ext_FER	  OR int_FER  OR v_FER);
			asyncECR	  = 	(ext_ECR	  OR int_ECR  OR v_ECR);
			asyncSpare = 	(ext_Spare OR 				  v_Spare);
			

NODE		enTRIG, enCAL, enBCR, enECR, enFER, enSpare;

			enTRIG  = /(             asyncCAL OR asyncBCR OR asyncECR OR asyncFER OR asyncSpare OR TestBusyON OR TRIG_winClosed); 
			enCAL   = /(asyncTRIG				 OR asyncBCR OR asyncECR OR asyncFER OR asyncSpare);
			enBCR   = /(asyncTRIG OR asyncCAL 				 OR asyncECR OR asyncFER OR asyncSpare);
			enECR   = /(asyncTRIG OR asyncCAL OR asyncBCR 				 OR asyncFER OR asyncSpare);
			enFER   = /(asyncTRIG OR asyncCAL OR asyncBCR OR asyncECR 				 OR asyncSpare);
			enSpare = /(asyncTRIG OR asyncCAL OR asyncBCR OR asyncECR OR asyncFER);


			busyTRIG	 = asyncTRIG;" OR syncTRIG; "Busy for TRIG is not timed, but 'manufactured'!!
			busyCAL	 = asyncCAL;
			busyBCR	 = asyncBCR;
			busyECR	 = asyncECR;
			busyFER	 = asyncFER;
			busySpare = asyncSpare;


"SYNCRONISERS (in asyncXXX, out syncXXX)
"-------------------------------------

NODE		CALTRIG,			"Trig generated at end of CAL pulse
			busyCALTRIG,	"for CAL state_machine;
			burst_CAL	   "CAL generated after CAL-Trig-BCALDelay for CALbursts
				DEFAULT_TO 0;

NODE		syncTRIG, syncCALP, syncBCR, syncFER, syncECR, syncSpare;


			syncTRIG	 = SYNC(asyncTRIG,  enTRIG,  clk2b, OA_rst) OR CALTRIG;
			syncCALP	 = SYNC(asyncCAL,	  enCAL,   clk2b, OA_rst) OR burst_CAL;
			syncBCR	 =	SYNC(asyncBCR,	  enBCR,   clk2b, OA_rst);
			syncECR 	 = SYNC(asyncECR,	  enECR,   clk2b, OA_rst);
			syncFER 	 = SYNC(asyncFER,   enFER,   clk2b, OA_rst);
			syncSpare = SYNC(asyncSpare, enSpare, clk2b, OA_rst);
			
						
			
NODE		qsyncTRIG				"1 clock delay for trigger busy timing
				CLOCKED_BY clk2
				RESET_BY OA_rst;
			qsyncTRIG = syncTRIG; 	
			
	      doneTRIG = qsyncTRIG;


"-------------------------------------------------------------------------------
"DELAYED TRIGGER in: suncTRIG, out: syncDTRIG
"-------------------------------------------------------------------------------


NODE		syncDTRIG;

			"TrigDelayChanged = (reg0A AND bWriteb); "*** delay reset on  write

NODE		shift144_clr;
			shift144_clr = syncCALP OR OA_rst; "OR TrigDelayChanged


NODE		enDTRIG;
			enDTRIG = /(busyCALP OR busyBCR OR busyECR OR busyFER OR busySpare);
	
			SHIFT144	(	syncTRIG, DelaySelect[7..0], clk2b, shift144_clr, enDTRIG,
							outTRIGh, syncDTRIG );


"-------------------------------------------------------------------------------
" DEAD-TIME BUSY GENERATOR
"-------------------------------------------------------------------------------


NODE		DeadTimer_Counter[5]
				CLOCKED_BY clk2
				CLOCK_ENABLED_BY enDeadTimer
				RESET_BY	rstDeadTimer OR OA_rst;

			DeadTimer_Counter = DeadTimer_Counter .+. 1;


NODE		DeadTimerGO; "= OR of all syncSIGs

			DeadTimerGO = 		syncDTRIG
								OR syncCALP
								OR	syncBCR
								OR syncECR
								OR syncFER
								OR syncSpare;

NODE		enDeadTimer
				CLOCKED_BY DeadTimerGO
				RESET_BY	rstDeadTimer OR OA_rst;
			enDeadTimer = 1;


NODE		rstDeadTimer;

NODE		DeadTimer3,
			DeadTimer6,
			DeadTimer27,
			DeadTimer31
				DEFAULT_TO	0;


			CASE DeadTimer_Counter
				WHEN 2  => DeadTimer3  = 1; "note the 'offset' due to clocking.
				WHEN 5  => DeadTimer6  = 1;
				WHEN 26 => DeadTimer27 = 1;
				WHEN 31 => DeadTimer31 = 1;
			END CASE;



"-----------------------------------------------
"CONTROL SIGNALS
"-----------------------------------------------



			OA_busy =	   busyTRIG
							OR busyDTRIG
							OR busyCAL
							OR	busyBCR
							OR busyECR
							OR busyFER
							OR busySpare
							OR TestBusyON
							OR OA_rst;


			doneDTRIG = (DeadTimer3  AND busyDTRIG);
			doneCALP	 = (DeadTimer27 AND busyCALP)	;
			doneBCR 	 = (DeadTimer6  AND busyBCR)	;
			doneECR 	 = (DeadTimer6  AND busyECR)	;
			doneFER 	 = (DeadTimer6  AND busyFER)	;
			doneSpare = (DeadTimer6  AND busySpare);

			rstDeadTimer =	   doneDTRIG
								OR doneCALP
								"OR doneCAL
								OR	doneBCR
								OR doneECR
								OR doneFER
								OR doneSpare;
								"OR TrigDelayChanged;
								"OR DeadTimer31;

NODE		clrTRIG, clrDTRIG, clrCAL, clrCALP, clrBCR, clrECR, clrFER, clrSpare;
NODE		clrRTRIG;

			clrBCR	= doneBCR   																				  OR OA_rst;
			clrFER	= doneFER   OR busyBCR																	  OR OA_rst;
			clrECR	= doneECR	OR busyBCR OR busyFER													  OR OA_rst;
			clrDTRIG	= doneDTRIG OR busyBCR OR busyFER OR busyECR					 OR Disable_TRIG OR OA_rst;
			clrCAL	= doneCAL   OR busyBCR OR busyFER OR busyECR OR busyRTRIG OR Disable_TRIG OR OA_rst;
			clrCALP	= doneCALP  OR clrCAL;
			clrSpare	= doneSpare OR busyBCR OR busyFER OR busyECR OR busyDTRIG OR busyCAL		  OR OA_rst;
			


"-------------------------------------------------------------------------------
"SIGNAL OUTPUTS (mapping)
"-------------------------------------------------------------------------------

OUTPUT	StartSink,
			StartSeq;	"JBL additions


OUTPUT	SATRIG  	CLOCKED_BY clk2b	RESET_BY clrDTRIG;
OUTPUT	SACAL 	CLOCKED_BY clk2b	RESET_BY clrCAL;
OUTPUT	SABCR1 	CLOCKED_BY clk2b	RESET_BY clrBCR;
OUTPUT	SAECR1 	CLOCKED_BY clk2b	RESET_BY clrECR;
OUTPUT	SAFER 	CLOCKED_BY clk2b	RESET_BY clrFER;
OUTPUT	SASpare 	CLOCKED_BY clk2b	RESET_BY clrSpare;


			outTRIG	= syncTRIG;
			outTRIG1 = syncDTRIG;

			StartSink =	outTRIG;
			StartSeq	 =	SASpare;

			SATRIG	= syncDTRIG;
			SACAL		= syncCALP;
			SABCR1	= syncBCR;
			SAECR1	= syncECR;
			SAFER		= syncFER;
			SASpare	= syncSpare;



"-------------------------------------------------------------------------------
"CAL pulse machine (NOT CALP!) - signals for CAL(P)+TRIG cycle
"-------------------------------------------------------------------------------

NODE		delayedBCAL,
			BCALdelayGO
				CLOCKED_BY clk2
				RESET_BY	OA_rst
				DEFAULT_TO 0;


"-------------------------------------
STATE_MACHINE	CAL_machine
						CLOCKED_BY	clk2b
						RESET_BY clrCAL OR OA_rst;

					STATE	wait_syncCALP:
						IF syncCALP THEN
							GOTO wait_doneCALP;
						ELSE
							GOTO wait_syncCALP;
						END IF;


					STATE wait_doneCALP:
						busyCALP = 1;
						IF doneCALP THEN
							GOTO issue_CALTRIG;
						ELSE
							GOTO wait_doneCALP;
						END IF;

					STATE issue_CALTRIG:
						CALTRIG = 1;
						busyCALTRIG = 1;
						GOTO wait_busyDTRIG;

					STATE wait_busyDTRIG:
						busyCALTRIG = 1;
						IF busyDTRIG THEN
							GOTO wait_doneDTRIG;
						ELSE
							GOTO wait_busyDTRIG;
						END IF;


					STATE	wait_doneDTRIG:
						IF doneDTRIG THEN
							GOTO check_burstCAL;
						ELSE
							GOTO wait_doneDTRIG;
						END IF;


					STATE	check_burstCAL:
						IF enCALburst THEN 	"enCALburst from PLD3 = enBurstCnt
							GOTO start_BCALdelay;
						ELSE
							GOTO finish;
						END IF;


					STATE	start_BCALdelay:
						BCALdelayGO = 1;
						GOTO	wait_delayedBCAL;


					STATE	wait_delayedBCAL:
						IF delayedBCAL = 1 THEN
							GOTO issue_burstCAL;
						ELSE
							GOTO wait_delayedBCAL;
						END IF;


					STATE	issue_burstCAL:
						burst_CAL = 1;
						GOTO wait_doneCALP;


					STATE finish:
							doneCAL = 1;
							GOTO wait_syncCALP;

					END CAL_machine;


"----------------------------------------------------
"burst CAL delay (fixed) in: ...Go, Out: delayedBCAL
"----------------------------------------------------

NODE		BCALdelay_rst
				CLOCKED_BY clk2
				RESET_BY OA_rst
				DEFAULT_TO 0;

NODE		enBCALdelay
				CLOCKED_BY BCALdelayGO
				RESET_BY	BCALdelay_rst OR OA_rst;
			enBCALdelay	= 1;

NODE		BCALdelay[11..0]		"*** should be ..0
				CLOCKED_BY clk2b
				CLOCK_ENABLED_BY enBCALdelay
				RESET_BY	BCALdelay_rst OR OA_rst;

			BCALdelay = BCALdelay .+. 1;

			IF	BCALdelay[11..1] = 01h THEN "### was roll-over on count 3320
				"delayedBCAL=	1;			"*** removed for testing
				IF	BCALdelay[0] THEN
					BCALdelay_rst = 1;
				END IF;
			END IF;
			
			delayedBCAL = BCALdelayGO; "*** Added for testing only


"===============================================================================
"
"TIM BUSYs
"
"===============================================================================


"*** this has not been checked at all

NODE		enIntBusy,	"reg00
			enExtBusy;	"reg00

			enintBusy = Register00high[7]; "EnintBusy
			enExtBusy = Register00high[15];"EnExtBUSY

NODE		vBusy;		"reg02


			[ vbusy, vRodBusy, vBurstMode, vBurstGo ] = RegisterCommand[7..10];


			MExtBusyOut	=	(NimExtBusy	OR	eclExtBusy)	AND enExtBusy ;


NODE		busyZ;
			busyZ = MExtBusyOut OR vBusy OR (enRodBusy AND rod_crate_busyOut);

NODE		busyTRIG2;
			busyTRIG2 =	OA_busy OR busyZ;

			BusyOut	= (OA_busy AND	enIntBusy) OR busyZ;


"===============================================================================
"
" Spare Lines
"
"===============================================================================

INPUT		sgbA[7..0];
INPUT		sgbB[7..0];
INPUT		sgbC[7..0];
INPUT		sgbD[5..0];

INPUT		s1_2[7..0];
INPUT		s2_3[7..0];
INPUT		s2_4a[7..0];
INPUT		s2_6[7..0];



"===============================================================================