"$Id: pld3.src,v 1.16 2001/11/14 20:11:14 warren Exp $
"===============================================================================
#TITLE	 'TIM	PLD3';
#ENGINEER 'Martin	Postranecky	/ Dominic A	Hayes';
#COMPANY	 'University College	London';
#COMMENT	 '';
"===============================================================================
"$Log: pld3.src,v $
"Revision 1.16  2001/11/14 20:11:14  warren
"minor layout
"
"Revision 1.15  2001/08/30 12:20:32  warren
"Tidied, Capitalization
"
"Revision 1.14  2001/08/08 18:40:27  warren
"signal name upper/lower case standardization
"
"Revision 1.13  2001/08/03 09:12:49  warren
"layout
"
"Revision 1.12  2001/07/27 17:40:49  warren
"fixed burst counter and assos sigs
"
"Revision 1.11  2001/07/26 15:10:03  warren
"new additions to our happy family
"
"Revision 1.10	 2001/07/23	11:18:33	 warren
"renamed	signals with proper polarity n prefixes and removed LOW_TRUEs
"
"Revision 1.9	2001/07/19 10:44:19	warren
"removed	unused spare bus lines
"
"Revision 1.8	2001/06/06 10:01:27	warren
"converted LF to CR/LF
"
"Revision 1.7	2001/05/31 17:14:55	jbl
"Remove dboe output
"
"Revision 1.6	2001/04/03 15:43:27	warren
"Changed	from nOA_rst to OA_rst
"


"===============================================================================
"MODIFICATIONS
"-------------
"05apr00	intIna -> intInaBCR,	intIn_c1	->	intIncRan
"			enCALBurst o/p.
"24may00	laser_inlck_state, SAClkOn	i/ps added
"			RodBusyOut -> rod_crate_BusyOut,	SequencerBusy -> SeqBusy,
"			MaskedExtBusy -> MExtBusyOut
"01jun00	clkInb -> clkInB1.
"05jun00	Burst_Ready connected	to	BurstEnd	internally.	still	o/p to pld2.
"			Reg22	i/p added to facilitate	"TIM version" ID stored	on	pld.
"03jul00	SinkBusy	i/p added.
"05jul00	ExtBusy now	a NODE fed by OR of new	i/ps Nim/eclExtBusy.
"12sep00	bWriteb and	bReadb now defined HIGH	TRUE like the rest of the PLDs.
"14sep00	nLEb2	clocking	removed from Registers 0C,	22.
"15sep00	Reg22	->	/Reg22 because	shared with	LOW_TRUE	enabled external register.
"20sep00	dboe sent to o/p pin	for debugging.
"			db	defaults	to	.z. instead	of	using	dboe to .z.	o/ps.
"				can't	do	that,	so	removed.
"			Can't	solve	without spliTTing	db	bus; Reg22 access	removed.
"03oct00	Added	CLK_EN_BY (and	tidied bWriteb	logic) for regs 04/06/08 -	MRMW
"01Nov00	Changed BurstEnd to BurstBusy	(status register bit) -	JBL
"02Nov00	Tidied nOA_rst	- MRMW
"06Nov00	Moved	Reg22	to	pld5 - MRMW
"Changed	Name and	address of ALL	sigs etc	of	Reg 22 --> Reg	32. Comments below
"				too!
"21Mar01	Remove LOW_TRUE from	nOA_rst,	added	OA_rst =	/nOA_rst	and replaced in
"				code
"25May01	dboe removed from	o/p pin
"24Jul01	Rearanged code for legi.
"25Jul01 Removed in-out tb_clk and renamed to enBurstCnt_clk
"			Renamed nvBurstBusy to qvBurstBusy
"			Removed qvBurstBusy -- it stoped bursts if vBurstMode not reset
"27Jul01 Added  level to pulse FF on vBurstGo sync-FF train
"14Nov01 Added  sync FFs to intTrig


"-----------------------------------------------------------------------------



"-------------------------------------------------------------------------------
"pseudo-random	binary sequence generator,	kicks	in	when repeat	TRIGger selected.
"CALled by Main Body.

PROCEDURE pseudo_random_generator

  (	INPUT	 intTRIG_, enRandom_, OA_rst_;
		OUTPUT intInRan_	);

		NODE		sr_in, 
					shift_reg_clk;
					
		shift_reg_clk = intTRIG_ AND enRandom_;	
		
					
		NODE		sr[1..39]
						CLOCKED_BY shift_reg_clk
						PRESET_BY OA_rst_;

		sr_in		 =	sr[39] (+) sr[35]; "XOR
		sr			 =	[sr_in,sr[1..38]];
		
		intInRan_ =	sr[39];

END pseudo_random_generator;



"-------------------------------------------------------------------------------
PROCEDURE BCR_generator
"synchronous 11.2456kHz	generator

  (INPUT	 clkInB1_, OA_rst_;
	OUTPUT intInBCR_);
	NODE	 count12[12] 
				CLOCKED_BY	clkInB1_
				RESET_BY		cnt_rst;
				
	NODE	 cnt_rst;
	
	NODE	 back2zero 
				DEFAULT_TO 0;

	count12 = count12	.+. 1;
	cnt_rst = back2zero OR OA_rst_;

	CASE count12
		WHEN 3564 => intInBCR_ =	1;
		WHEN 3565 => intInBCR_ =	0;
						 back2zero =	1;
						 
		ELSE			 intInBCR_ =	0;
	END CASE;

END BCR_generator;





"===============================================================================
"CODE
"-------------------

INPUT		nOA_rst;							"Low_True Board reset.
NODE		OA_rst;
			OA_rst =	/nOA_rst;

INPUT		bWriteb,	bReadb;
INPUT		nLEb2, clk3;

INPUT		Reg04, Reg06,	Reg08, Reg0C; "reg32;

"INPUT	 intTRIG, enint_c1,	intIn_c2, vBurstGo, vBurstMode;	 "From pld2


INPUT		SinkBusy;		"from	PLD7

INPUT		tb_clkIn;	" <--<--\	"*** not used at present
OUTPUT	tb_clkout;	" >-->--/	" ( was needed to fit clock.)


BIPUT		db[15..0]					"VME databus
				ENABLED_BY dboe;

NODE	 	dboe;							"db output enable



NODE	 	Register06[15..0]			"Repeat Frequency
				CLOCKED_BY nLEb2
				CLOCK_ENABLED_BY (bWriteb AND	Reg06)
				RESET_BY	OA_rst;


OUTPUT 	r[5..1],						"random TRIGger freq	range
		 	s[5..1];						"soft	reset	repeat frequency


NODE	 	Register08[15..0]			"TRIG	Window Size	and Delay
				CLOCKED_BY nLEb2
				CLOCK_ENABLED_BY (bWriteb AND	Reg08)
				RESET_BY	OA_rst;


OUTPUT 	ws[5..0],						"window size
		 	wd[5..0];						"window delay


INPUT		laser_intlck_state,
			SAMode,
			RunMode,
			SAClkOn,
			TTCClkOn,
			rod_crate_BusyOut,
			TestBusyON,
			SeqBusy,
			BusyOut,
			intBusy,
			MExtBusyOut,
		 	eclExtBusy,
		 	NimExtBusy;



NODE		ExtBusy;


NODE		Register0C[15..0];			"Busys &	State	- Read Only	(no clocking)

"NODE	  Register32[15..8];			  "TIM VERSION. -	Read Only (no clocking)




"===============================================================================
"MAIN	BODY
"---------




"==============================================================================
" Burst Counter etc
"==============================================================================

"Generates Disable_TRIG	which	stops	SATRIGs being emitted from	PLD2.
"Includes a	counter that counts SATRIGs during burst mode.

"**************** below no longer true:
"NB tb_clkout and	tb_clkIn	are SAME	signal linked externally.
"	(Requirement for fiTTing.)


NODE		Register04[15..0]			"Burst Count
				CLOCKED_BY nLEb2
				CLOCK_ENABLED_BY (bWriteb AND	Reg04)
				RESET_BY	OA_rst;

			Register04 = db;



"----- Burst Counter --------------------------------------

INPUT		SATRIG;	"from PLD2


INPUT		vBurstMode;	"from PLD2


"Sync up vBurstGo
INPUT		vBurstGo; 	"From	pld2

NODE		q1_vBurstGo,
			q2_vBurstGo
				CLOCKED_BY	clk3		"Sync 
				RESET_BY		OA_rst;

NODE		q3_vBurstGo
				CLOCKED_BY	q2_vBurstGo
				RESET_BY		l2p_vBurstGo OR OA_rst;

NODE		l2p_vBurstGo
				CLOCKED_BY	clk3
				RESET_BY		OA_rst;

			q1_vBurstGo	= vBurstGo;
			q2_vBurstGo	= q1_vBurstGo;
			q3_vBurstGo	= 1;
			l2p_vBurstGo = q3_vBurstGo;


NODE		enBurstCnt
				CLOCKED_BY clk3						"*** removed AND q2_...
				CLOCK_ENABLED_BY l2p_vBurstGo	"*** added C_E_B q2_.. instead
				RESET_BY	rst_enBurstCnt;
			enBurstCnt	= vBurstMode;				"Counter	enable FF

NODE		BurstCnt_at_zero;

NODE		rst_enBurstCnt;
			rst_enBurstCnt	 =	(/l2p_vBurstGo AND BurstCnt_at_zero) OR OA_rst;


NODE		BurstCnt[15..0]
				CLOCKED_BY BurstCnt_clk
				"CLOCK_ENABLED_BY enBurstCnt "*** removed and added to .._clk equ
				PRESET_BY OA_rst;	"*** why preset??

			"--- burst counter clocking
			"SATRIG used as the BurstCnt clock when vBurstMode	enabled.
NODE		BurstCnt_clk;
			BurstCnt_clk =	l2p_vBurstGo OR (SATRIG AND enBurstCnt);
			

			IF enBurstCnt THEN
				BurstCnt	= BurstCnt .-.	1;	"count down
			
			ELSIF	l2p_vBurstGo THEN
				BurstCnt = Register04;	"synchro preload from pre-loaded Reg04.
			
			ELSE
				BurstCnt = BurstCnt;

			END IF;


			CASE BurstCnt
				WHEN 0 => BurstCnt_at_zero	= 1;				"count finished
				ELSE		 BurstCnt_at_zero	= 0;
			END CASE;


"---------------------------------------------------------
"Burst_Ready/Disable_TRIG etc


OUTPUT	Disable_TRIG;	"to PLD2
OUTPUT	enCALBurst;		"to PLD2
OUTPUT	Burst_Ready	;	"to PLD2
NODE		BurstBusy;		"Stat reg bit


"*** what is this for
"NODE		qvBurstMode
"				CLOCKED_BY vBurstMode
"				RESET_BY	(enBurstCnt	OR	OA_rst);
"			qvBurstMode	= 1;


			Burst_Ready  = vBurstMode AND /enBurstCnt; "busy signal to PLD2
			Disable_TRIG =	Burst_Ready;	"to PLD2, Disable	SATRIG.

			BurstBusy	 =	enBurstCnt;		"BurstBusy	bit of the Status	reg
			enCALBurst	 =	enBurstCnt;



"===============================================================================
"RANDOM TRIGGER GEN

"PLD2 signals
INPUT		intTRIG, enRandom;
OUTPUT	intInRan;


			pseudo_random_generator
			  (intTRIG,	enRandom, OA_rst,
				intInRan);


"===============================================================================
"TIMED BCR GENERATOR

INPUT		clkInB1;


OUTPUT	intInBCR;	"to PLD2

			BCR_generator
			  (clkInB1,	OA_rst,
				intInBCR);


"----------------------------------------------------------------------
"VME access
"----------


			Register06 = db;	" ***	tidied
			Register08 = db;	"

			IF	(bReadb)	THEN						 "VME	READS	the Registers.

				IF	(Reg04) THEN
					db	= Register04;

				ELSIF	(Reg06) THEN
					db	= Register06;

				ELSIF	(Reg08) THEN
					db	= Register08;

				ELSIF	(Reg0C) THEN
					db	= Register0C;

				END IF;
			END IF;

			dboe = bReadb AND	(Reg04 OR Reg06 OR Reg08 OR Reg0C);


"--------------------------------------------------------------------------
"REPEAT FREQ SELECT OUTPUTS to programmable oscillators
"------------------------------------------------------
r[5..1] = Register06[4..0];
s[5..1] = Register06[12..8];



"--------------------------------------------------------------------------
"TRIGWIN	OUTPUTS to programmable	delay	lines?
"--------------------------------------------
ws[5..0]	= Register08[5..0];
wd[5..0]	= Register08[13..8];


"--------------------------------------------------------------------------
"INPUTS to BUSYS REGISTER
"------------------------
ExtBusy	= NimExtBusy OR eclExtBusy;

Register0C[15..0]	= [	laser_intlck_state,
								TestBusyON,
								0,
								0,
								SAMode,
								RunMode,
								SAClkOn,
								TTCClkOn,
								rod_crate_BusyOut,
								SinkBusy,
								SeqBusy,
								BurstBusy,
								BusyOut,
								intBusy,
								MExtBusyOut,
								ExtBusy			];




"-------------------------------------------------------------------------------
"SPARE I/O
"---------
			INPUT	sgbA[7..0];		 "Spare global	bus A
			INPUT	sgbB[7..0];		 "Spare global	bus B
			INPUT	sgbC[7..0];		 "Spare global	bus C
			INPUT	sgbD[5..0];		 "Spare global	bus D

			INPUT	s2_3[7..0];		 "Spare loCAL bus
			INPUT	s3_9[7..0];		 "Spare loCAL bus


"===============================================================================	