
	DATE:     Fri Nov 16 15:29:37 2001

	DESIGN:   pld6
	DEVICE:   M4-256/128:1

	TITLE:    ATLAS TIM	PLD6:	Backplane Mapping
	ENGINEER: Martin	Postranecky	/ Dominic A	Hayes
	COMPANY:  University College	London

	Product:     MACHXL
	             Copyright MINC Incorporated 1987-1998
	             Patent 5,140,526 and 5,499,191
	Version:     A6.2.1.11


           M4-256/128 SUCCEEDED FOR 67 FUNCTIONS
           ---------------------------------

 EFFORT_LEVEL: 5
 EFFETIVE UTILIZATION: 100

PARTITIONER REPORT:

	Notes: '@' flags nodes with fanouts within partition group.
	       '#' flags nodes with fanouts beyond partition group.

	Partition A;	Group-type MERGIBLE_GROUP;
	   0 Clocks;   0 Enables;   0 Register Sets
	    0 Functions
	    0 Signals

	Partition B;	Group-type MERGIBLE_GROUP;
	   0 Clocks;   0 Enables;   0 Register Sets
	    0 Functions
	    0 Signals

	Partition D;
	   0 Clocks;   1 Enables;   0 Register Sets
	    8 Functions
	       db[7]          db[6]          db[5]          db[4]         
	      @reg_ttcout[7] @reg_ttcout[6] @reg_ttcout[5] @reg_ttcout[4] 
	    18 Signals
	       nOA_rst            bReadb             bWriteb            
	       reg30              Reg18              enRodBusy          
	       enttc_register[6]  enttc_register[5]  enttc_register[4]  
	       dboe               nTTCout[6]         nTTCout[7]         
	       nTTCout[5]         nTTCout[4]         reg_ttcout[7]      
	       reg_ttcout[6]      reg_ttcout[5]      reg_ttcout[4]      

	Partition C;
	   1 Clocks;   1 Enables;   1 Register Sets
	    11 Functions
	      #enttc_register[3] #enttc_register[1]  db[3]             
	       db[2]              db[1]              db[0]             
	      #dboe              @reg_ttcout[3]     @reg_ttcout[2]     
	      @reg_ttcout[1]     @reg_ttcout[0]     
	    20 Signals
	       nOA_rst            bReadb             bWriteb            
	       reg30              Reg18              enttc_register[3]  
	       sgbB[4]            enttc_register[1]  enBCClk            
	       db[3]              db[1]              dboe               
	       nTTCout[0]         nTTCout[2]         nTTCout[1]         
	       nTTCout[3]         reg_ttcout[3]      reg_ttcout[2]      
	       reg_ttcout[1]      reg_ttcout[0]      

	Partition E;
	   0 Clocks;   1 Enables;   0 Register Sets
	    4 Functions
	       db[11]  db[10]  db[9]   db[8]  
	    6 Signals
	       reg30               enttc_register[11]  enTType             
	       enBCID              enL1ID              dboe                

	Partition F;
	   0 Clocks;   1 Enables;   0 Register Sets
	    4 Functions
	       db[15]  db[14]  db[13]  db[12] 
	    6 Signals
	       reg30               enSABCR2            enSAECR2            
	       enttc_register[13]  enttc_register[12]  dboe                

	Partition H;
	   1 Clocks;   0 Enables;   1 Register Sets
	    10 Functions
	       idTRIG              idBCR               idECR              
	      #enttc_register[12] #enttc_register[11]  enTType            
	       enBCID              enL1ID              enRodBusy          
	       enBCClk            
	    21 Signals
	       nOA_rst             bReadb              bWriteb             
	       Reg18               enttc_register[12]  enttc_register[11]  
	       enTType             enBCID              enL1ID              
	       enRodBusy           enBCClk             db[12]              
	       db[11]              db[10]              db[9]               
	       db[8]               db[7]               db[0]               
	       eclL1A              eclBCR              eclECR              

	Partition G;
	   1 Clocks;   0 Enables;   1 Register Sets
	    8 Functions
	       eclL1A    eclBCR    eclECR    eclCAL    eclFER   
	       eclSpare  eclID     eclTT    
	    9 Signals
	       nOA_rst     nTTCout[0]  nTTCout[2]  nTTCout[1]  
	       nTTCout[3]  nTTCout[6]  nTTCout[7]  nTTCout[5]  
	       nTTCout[4]  

	Partition I;
	   1 Clocks;   0 Enables;   1 Register Sets
	    5 Functions
	       enSABCR2    nTTCout[0]  nTTCout[2]  nTTCout[1] 
	       nTTCout[3] 
	    24 Signals
	       nOA_rst            bReadb             bWriteb            
	       Reg18              SATRIG             SACAL              
	       SABCR1             SAECR1             SABCR2             
	       SAECR2             L1Ain              BCRin              
	       ECRin              CALin              enSABCR2           
	       enttc_register[4]  enttc_register[3]  sgbB[4]            
	       enttc_register[1]  db[15]             seqTRIG            
	       seqCAL             seqBCR             seqECR             

	Partition J;
	   1 Clocks;   0 Enables;   1 Register Sets
	    9 Functions
	       enSAECR2           #enttc_register[13] #enttc_register[6]  
	      #enttc_register[5]  #enttc_register[4]   nTTCout[6]         
	       nTTCout[7]          nTTCout[5]          nTTCout[4]         
	    24 Signals
	       nOA_rst             bReadb              bWriteb             
	       Reg18               SAFER               SASpare             
	       FERin               Sparein             TTin                
	       IDin                enSAECR2            enttc_register[13]  
	       enttc_register[6]   enttc_register[5]   enttc_register[4]   
	       db[14]              db[13]              db[6]               
	       db[5]               db[4]               seqFER              
	       seqSpare            seqTT               seqID               

	Partition L;	Group-type MERGIBLE_GROUP;
	   0 Clocks;   0 Enables;   0 Register Sets
	    0 Functions
	    0 Signals

	Partition K;	Group-type MERGIBLE_GROUP;
	   0 Clocks;   0 Enables;   0 Register Sets
	    0 Functions
	    0 Signals

	Partition M;	Group-type MERGIBLE_GROUP;
	   0 Clocks;   0 Enables;   0 Register Sets
	    0 Functions
	    0 Signals

	Partition N;	Group-type MERGIBLE_GROUP;
	   0 Clocks;   0 Enables;   0 Register Sets
	    0 Functions
	    0 Signals

	Partition P;	Group-type MERGIBLE_GROUP;
	   0 Clocks;   0 Enables;   0 Register Sets
	    0 Functions
	    0 Signals

	Partition O;
	   1 Clocks;   0 Enables;   1 Register Sets
	    8 Functions
	       sgbB[4]  sgbB[7]  sgbB[6]  sgbB[5]  sgbB[3]  sgbB[2] 
	       sgbB[1]  sgbB[0] 
	    13 Signals
	       nOA_rst     bReadb      bWriteb     Reg18       
	       SAECR1      SAECR2      ECRin       idECR       
	       sgbB[4]     db[2]       seqECR      nTTCout[1]  
	       eclECR      




DEVICE and BLOCK RESOURCE TABLE LEGEND:

    1.  Reserved signifies resources that have been
        set aside by the global MACH_UTILIZATION
        property or by assigning NO_CONNECT to device pins.

    2.  A Set and Reset Group is the largest collection of
        functions that have both a preset and a reset signal
        such that every function in the group has both the same
        preset signal and the same reset signal.

    3.  A Set or Reset Group is the largest collection of
        functions that all have a preset signal or all have
        a reset signal but none have both. Also, every function
        in the group has either the same preset signal, if
        the functions have presets or the same reset signal, if
        the functions have resets.

    4.  Product terms are split into two types.  Equation Pterms
        and Asynchronous Pterms. Equation pterms are product terms 
        used for an equation. Asynchronous pterms are product terms  
        used for control functions in the asynchronous mode

    5.  Clusters are groups of product terms allocated
        to macrocells. Cluster pterms are pterms in all
        clusters steered to a macrocell regardless of whether
        all of the pterms are used by the function.


  M4-256/128 DEVICE RESOURCE UTILIZATION:

           Resource           Device Capacity   Used     Remaining  Utilization
     :==========================================================================:
     : Clock Pins                    4           2                              :
     :    Reserved Clock Pins                    0                              :
     :    ------------------------------------------------------------------    :
     :    Total Clock Pins           4           2            2         50%     :
     :==========================================================================:
     : Input Pins                   14           0                              :
     :    Reserved Input Pins                    0                              :
     :    ------------------------------------------------------------------    :
     :    Total Input Pins          14           0           14          0%     :
     :==========================================================================:
     : I/O Pins                    128                                          :
     :    Inputs                                62                              :
     :    Non-Tri-state Outputs                 34                              :
     :    Tri-state Outputs                     16                              :
     :    Reserved I/O Pins                      0                              :
     :    ------------------------------------------------------------------    :
WARN :    Total I/O Pins           128         112           16         88%     :
     :==========================================================================:
     : Input Registers             128                                          :
     :    D-Latches                              0                              :
     :    D-Flops                                0                              :
     :    ------------------------------------------------------------------    :
     :    Total Input Registers    128           0          128          0%     :
     :==========================================================================:
     : Macrocells                  256                                          :
     :    Combinatorial                         43                              :
     :    D-Latches                              0                              :
     :    D-Flops                                8                              :
     :    T-Flops                               16                              :
     :    Reserved Macrocells                    0                              :
     :    ------------------------------------------------------------------    :
     :    Total Macrocells         256          67          189         26%     :
     :==========================================================================:
     : Macrocell Mode                                                           :
     :    Synchronous                           67                              :
     :    Asynchronous                           0                              :
     :==========================================================================:
     : Nodes                       384          17          367          4%     :
     :==========================================================================:
     : Output Enables              128                                          :
     :    Enables                               16                              :
     :    Enables only for Test                  0                              :
     :    ------------------------------------------------------------------    :
     :    Total Output Enables     128          16          112         13%     :
     :==========================================================================:
     : XORs                        256           0          256          0%     :
     :==========================================================================:
     : Cluster Pterms             1280         249         1031         19%     :
     :==========================================================================:
     : Product Terms              1280                                          :
     :    Equation Pterms                      114                              :
     :    Async Pterms                           0                              :
     :    ------------------------------------------------------------------    :
     :    Total Pterms            1280         114         1166          9%     :
     :==========================================================================:
     : Product Term Clocks         256           0          256          0%     :
     :==========================================================================:
     : Central SM Inputs           384                                          :
     :    Pin Feedback                          45                              :
     :    Internal Feedback                     37                              :
     :    ------------------------------------------------------------------    :
     :    Total CSM Inputs         384          82          302         21%     :
     :==========================================================================:
     : Central SM Fanouts          544         141          403         26%     :
     :==========================================================================:
     : Set Groups                                                               :
     :    Set or Reset Groups      256           1          255          0%     :
     :    Set and Reset Groups      16           0           16          0%     :
     :==========================================================================:


BLOCK RESOURCE SUMMARY:

     :==========================================================================:
     :PAL       BLK   PT    I/O   IN                   CLST  EQN   SIGNAL ARRAY :
     :BLOCK     CLKS  CLKS  PINS  REG   MC  OES  XORS  PT    PTS   FANOUT INPUT :
     :==========================================================================:
     :AVAILABLE  4    16    8     8     16   8    16   80    80    24      34   :
     :==========================================================================:
     :USED                                                                      :
     :A          0    0     8     0     0    0    0    0     0     8       0    :
     :B          0    0     5     0     0    0    0    0     0     4       0    :
     :D          0    0     8     0     8    4    0    40    20    8       18   :
     :C          1    0     8     0     11   4    0    55    26    11      20   :
     :E          0    0     8     0     4    4    0    8     4     4       6    :
     :F          0    0     8     0     4    4    0    8     4     4       6    :
     :H          1    0     8     0     10   0    0    36    17    8       21   :
     :G          1    0     8     0     8    0    0    16    8     3       9    :
     :I          1    0     5     0     5    0    0    25    10    5       24   :
     :J          1    0     5     0     9    0    0    37    16    9       24   :
     :L          0    0     8     0     0    0    0    0     0     8       0    :
     :K          0    0     8     0     0    0    0    0     0     0       0    :
     :M          0    0     8     0     0    0    0    0     0     8       0    :
     :N          0    0     1     0     0    0    0    0     0     1       0    :
     :P          0    0     8     0     0    0    0    0     0     0       0    :
     :O          1    0     8     0     8    0    0    24    9     1       13   :
     :==========================================================================:


     BLK CLKS       - Block Clocks 
     PT CLKS        - Product Term Clocks
     I/O Pins       - I/O pins (Inputs + Non-Tristate + Tristate + Reserved) 
     IN REG         - Input Registers (D-Latches + D-FLops) 
     MC             - Macrocells (Comb + D-Latches + D-Flops + T-Flops + Reserved)
     OES            - Output Enables
     XOR            - Exclusive ORs
     CLST PTS       - Maximum of Asynchronous, equation and single Cluster Product Terms 
     EQN PTS        - Product Terms used in the pal block
     SIGNAL FANOUT  - Block Fanout to Central Switch Matrix
     ARRAY INPUTS   - Block Fanin from Central Switch Matrix


POWER SUMMARY:

Number of blocks with power set to LOW is 7
Number of blocks with power set to HIGH is 9

CLOCK ASSIGNMENTS:

    Notes: block usage 'H' indicates used in TRUE sense.
           block usage 'L' indicates used in INVERSE sense.

    clock signal        [ 68] clk6
    pin                 74
    block usage           ,   ,   ,   ,   ,   ,   , H , 
                          ,   ,   ,   ,   ,   ,   ,   

    clock signal        [ 73] nLEb2
    pin                 83
    block usage           ,   ,   , H ,   ,   , H ,   , 
                        H , H ,   ,   ,   ,   ,   , H 


SIGNAL DIRECTORY:

    LEGEND: The first line has the Signal Index, Signal Type and Signal name.
            The Signal Type is one of {Input | Reg.Input | Reg.Feedback | Node|
            Tri.State | Output}. The Second line contains the assignment
            information for the signal. If the signal appears on a pin, the pin
            number and type is provided. Functions provide macrocell assignment
            information along with specifics on how the function is fit.This
            includes the number of pterms required, the register type used to 
            implement the function, and notes if the function implementation has
            any notable characteristics.

    Notes: Register type suffix '_X' indicates XOR used;
           Register type suffix '_A' indicates Asynchronous mode used;
           Register type suffix '_LT' indicates function is LOW_TRUE.
           'RS_SWAP' flags functions which are preset at power-on.
           'OE' flags tri-state functions.

  [000]  Output:        idTRIG
         Pin 69 (I/O)  Block H  Macrocell_H11 1 Pterm COMB          

  [001]  Output:        idBCR
         Pin 70 (I/O)  Block H  Macrocell_H08 1 Pterm COMB          

  [002]  Output:        idECR
         Pin 71 (I/O)  Block H  Macrocell_H03 1 Pterm COMB          

  [003]  Output:        enSABCR2
         Pin 90 (I/O)  Block I  Macrocell_I13 2 Pterm TFF           

  [004]  Output:        enSAECR2
         Pin 100 (I/O)  Block J  Macrocell_J08 2 Pterm TFF           

  [005]  Node:          enttc_register[13]
                        Block J  Macrocell_J02 2 Pterm TFF           

  [006]  Node:          enttc_register[12]
                        Block H  Macrocell_H05 2 Pterm TFF           

  [007]  Node:          enttc_register[11]
                        Block H  Macrocell_H09 2 Pterm TFF           

  [008]  Output:        enTType
         Pin 66 (I/O)  Block H  Macrocell_H14 2 Pterm TFF           

  [009]  Output:        enBCID
         Pin 64 (I/O)  Block H  Macrocell_H00 2 Pterm TFF           

  [010]  Output:        enL1ID
         Pin 65 (I/O)  Block H  Macrocell_H01 2 Pterm TFF           

  [011]  Output:        enRodBusy
         Pin 67 (I/O)  Block H  Macrocell_H12 2 Pterm TFF           

  [012]  Node:          enttc_register[6]
                        Block J  Macrocell_J03 2 Pterm TFF           

  [013]  Node:          enttc_register[5]
                        Block J  Macrocell_J15 2 Pterm TFF           

  [014]  Node:          enttc_register[4]
                        Block J  Macrocell_J13 2 Pterm TFF           

  [015]  Node:          enttc_register[3]
                        Block C  Macrocell_C02 2 Pterm TFF           

  [016]  Output:        sgbB[4]
         Pin 161 (I/O)  Block O  Macrocell_O14 2 Pterm TFF           

  [017]  Node:          enttc_register[1]
                        Block C  Macrocell_C15 2 Pterm TFF           

  [018]  Output:        enBCClk
         Pin 68 (I/O)  Block H  Macrocell_H06 2 Pterm TFF_LT        

  [019]  Tri-state:     db[15]
         Tri-internal:  $NONE$
         Pin 45 (I/O)  Block F  Macrocell_F07 1 Pterm COMB           OE

  [020]  Tri-state:     db[14]
         Tri-internal:  $NONE$
         Pin 44 (I/O)  Block F  Macrocell_F05 1 Pterm COMB           OE

  [021]  Tri-state:     db[13]
         Tri-internal:  $NONE$
         Pin 43 (I/O)  Block F  Macrocell_F02 1 Pterm COMB           OE

  [022]  Tri-state:     db[12]
         Tri-internal:  $NONE$
         Pin 42 (I/O)  Block F  Macrocell_F00 1 Pterm COMB           OE

  [023]  Tri-state:     db[11]
         Tri-internal:  $NONE$
         Pin 35 (I/O)  Block E  Macrocell_E07 1 Pterm COMB           OE

  [024]  Tri-state:     db[10]
         Tri-internal:  $NONE$
         Pin 34 (I/O)  Block E  Macrocell_E05 1 Pterm COMB           OE

  [025]  Tri-state:     db[9]
         Tri-internal:  $NONE$
         Pin 33 (I/O)  Block E  Macrocell_E02 1 Pterm COMB           OE

  [026]  Tri-state:     db[8]
         Tri-internal:  $NONE$
         Pin 32 (I/O)  Block E  Macrocell_E00 1 Pterm COMB           OE

  [027]  Tri-state:     db[7]
         Tri-internal:  $NONE$
         Pin 16 (I/O)  Block D  Macrocell_D09 2 Pterm COMB           OE

  [028]  Tri-state:     db[6]
         Tri-internal:  $NONE$
         Pin 15 (I/O)  Block D  Macrocell_D10 2 Pterm COMB           OE

  [029]  Tri-state:     db[5]
         Tri-internal:  $NONE$
         Pin 14 (I/O)  Block D  Macrocell_D15 2 Pterm COMB           OE

  [030]  Tri-state:     db[4]
         Tri-internal:  $NONE$
         Pin 13 (I/O)  Block D  Macrocell_D01 2 Pterm COMB           OE

  [031]  Tri-state:     db[3]
         Tri-internal:  $NONE$
         Pin 6 (I/O)  Block C  Macrocell_C08 2 Pterm COMB           OE

  [032]  Tri-state:     db[2]
         Tri-internal:  $NONE$
         Pin 5 (I/O)  Block C  Macrocell_C10 2 Pterm COMB           OE

  [033]  Tri-state:     db[1]
         Tri-internal:  $NONE$
         Pin 4 (I/O)  Block C  Macrocell_C00 2 Pterm COMB           OE

  [034]  Tri-state:     db[0]
         Tri-internal:  $NONE$
         Pin 3 (I/O)  Block C  Macrocell_C01 2 Pterm COMB           OE

  [035]  Node:          dboe
                        Block C  Macrocell_C14 2 Pterm COMB          

  [036]  Output:        nTTCout[0]
         Pin 86 (I/O)  Block I  Macrocell_I00 2 Pterm COMB          

  [037]  Output:        nTTCout[2]
         Pin 88 (I/O)  Block I  Macrocell_I06 2 Pterm COMB          

  [038]  Output:        nTTCout[1]
         Pin 87 (I/O)  Block I  Macrocell_I04 2 Pterm COMB          

  [039]  Output:        nTTCout[3]
         Pin 89 (I/O)  Block I  Macrocell_I10 2 Pterm COMB          

  [040]  Output:        nTTCout[6]
         Pin 98 (I/O)  Block J  Macrocell_J06 2 Pterm COMB          

  [041]  Output:        nTTCout[7]
         Pin 99 (I/O)  Block J  Macrocell_J12 2 Pterm COMB          

  [042]  Output:        nTTCout[5]
         Pin 97 (I/O)  Block J  Macrocell_J07 1 Pterm COMB          

  [043]  Output:        nTTCout[4]
         Pin 96 (I/O)  Block J  Macrocell_J05 1 Pterm COMB          

  [044]  Node:          reg_ttcout[7]
                        Block D  Macrocell_D11 3 Pterm COMB          

  [045]  Node:          reg_ttcout[6]
                        Block D  Macrocell_D04 3 Pterm COMB          

  [046]  Node:          reg_ttcout[5]
                        Block D  Macrocell_D00 3 Pterm COMB          

  [047]  Node:          reg_ttcout[4]
                        Block D  Macrocell_D07 3 Pterm COMB          

  [048]  Node:          reg_ttcout[3]
                        Block C  Macrocell_C09 3 Pterm COMB          

  [049]  Node:          reg_ttcout[2]
                        Block C  Macrocell_C06 3 Pterm COMB          

  [050]  Node:          reg_ttcout[1]
                        Block C  Macrocell_C13 3 Pterm COMB          

  [051]  Node:          reg_ttcout[0]
                        Block C  Macrocell_C07 3 Pterm COMB          

  [052]  Output:        eclL1A
         Pin 58 (I/O)  Block G  Macrocell_G09 1 Pterm DFF           

  [053]  Output:        eclBCR
         Pin 54 (I/O)  Block G  Macrocell_G03 1 Pterm DFF           

  [054]  Output:        eclECR
         Pin 56 (I/O)  Block G  Macrocell_G00 1 Pterm DFF           

  [055]  Output:        eclCAL
         Pin 55 (I/O)  Block G  Macrocell_G01 1 Pterm DFF           

  [056]  Output:        eclFER
         Pin 57 (I/O)  Block G  Macrocell_G11 1 Pterm DFF           

  [057]  Output:        eclSpare
         Pin 59 (I/O)  Block G  Macrocell_G07 1 Pterm DFF           

  [058]  Output:        eclID
         Pin 60 (I/O)  Block G  Macrocell_G04 1 Pterm DFF           

  [059]  Output:        eclTT
         Pin 61 (I/O)  Block G  Macrocell_G02 1 Pterm DFF           

  [060]  Output:        sgbB[7]
         Pin 158 (I/O)  Block O  Macrocell_O00 1 Pterm COMB          

  [061]  Output:        sgbB[6]
         Pin 159 (I/O)  Block O  Macrocell_O03 1 Pterm COMB          

  [062]  Output:        sgbB[5]
         Pin 160 (I/O)  Block O  Macrocell_O01 1 Pterm COMB          

  [063]  Output:        sgbB[3]
         Pin 162 (I/O)  Block O  Macrocell_O07 1 Pterm COMB          

  [064]  Output:        sgbB[2]
         Pin 163 (I/O)  Block O  Macrocell_O09 1 Pterm COMB          

  [065]  Output:        sgbB[1]
         Pin 164 (I/O)  Block O  Macrocell_O04 1 Pterm COMB          

  [066]  Output:        sgbB[0]
         Pin 165 (I/O)  Block O  Macrocell_O05 1 Pterm COMB          

  [067]  Input:         nOA_rst
         Pin 206 (I/O)  Block B  

  [068]  Input:         clk6
         Pin 74 (InClk)

  [069]  Input:         bReadb
         Pin 202 (I/O)  Block B  

  [070]  Input:         bWriteb
         Pin 149 (I/O)  Block N  

  [071]  Input:         reg30
         Pin 204 (I/O)  Block B  

  [072]  Input:         Reg18
         Pin 203 (I/O)  Block B  

  [073]  Input:         nLEb2
         Pin 83 (InClk)

  [074]  Input:         RunMode
         Pin 201 (I/O)  Block B  

  [075]  Input:         SATRIG
         Pin 143 (I/O)  Block M  

  [076]  Input:         SACAL
         Pin 137 (I/O)  Block M  

  [077]  Input:         SABCR1
         Pin 136 (I/O)  Block M  

  [078]  Input:         SAECR1
         Pin 140 (I/O)  Block M  

  [079]  Input:         SAFER
         Pin 141 (I/O)  Block M  

  [080]  Input:         SASpare
         Pin 142 (I/O)  Block M  

  [081]  Input:         SABCR2
         Pin 138 (I/O)  Block M  

  [082]  Input:         SAECR2
         Pin 139 (I/O)  Block M  

  [083]  Input:         L1Ain
         Pin 194 (I/O)  Block A  

  [084]  Input:         BCRin
         Pin 190 (I/O)  Block A  

  [085]  Input:         ECRin
         Pin 191 (I/O)  Block A  

  [086]  Input:         CALin
         Pin 197 (I/O)  Block A  

  [087]  Input:         FERin
         Pin 192 (I/O)  Block A  

  [088]  Input:         Sparein
         Pin 195 (I/O)  Block A  

  [089]  Input:         TTin
         Pin 196 (I/O)  Block A  

  [090]  Input:         IDin
         Pin 193 (I/O)  Block A  

  [091]  Input:         seqTRIG
         Pin 123 (I/O)  Block L  

  [092]  Input:         seqCAL
         Pin 118 (I/O)  Block L  

  [093]  Input:         seqBCR
         Pin 117 (I/O)  Block L  

  [094]  Input:         seqECR
         Pin 119 (I/O)  Block L  

  [095]  Input:         seqFER
         Pin 120 (I/O)  Block L  

  [096]  Input:         seqSpare
         Pin 122 (I/O)  Block L  

  [097]  Input:         seqTT
         Pin 124 (I/O)  Block L  

  [098]  Input:         seqID
         Pin 121 (I/O)  Block L  

  [099]  Input:         sgbA[7]
         Pin 168 (I/O)  Block P  

  [100]  Input:         sgbA[6]
         Pin 169 (I/O)  Block P  

  [101]  Input:         sgbA[5]
         Pin 170 (I/O)  Block P  

  [102]  Input:         sgbA[4]
         Pin 171 (I/O)  Block P  

  [103]  Input:         sgbA[3]
         Pin 172 (I/O)  Block P  

  [104]  Input:         sgbA[2]
         Pin 173 (I/O)  Block P  

  [105]  Input:         sgbA[1]
         Pin 174 (I/O)  Block P  

  [106]  Input:         sgbA[0]
         Pin 175 (I/O)  Block P  

  [107]  Input:         s2_6[7]
         Pin 107 (I/O)  Block K  

  [108]  Input:         s2_6[6]
         Pin 108 (I/O)  Block K  

  [109]  Input:         s2_6[5]
         Pin 109 (I/O)  Block K  

  [110]  Input:         s2_6[4]
         Pin 110 (I/O)  Block K  

  [111]  Input:         s2_6[3]
         Pin 111 (I/O)  Block K  

  [112]  Input:         s2_6[2]
         Pin 112 (I/O)  Block K  

  [113]  Input:         s2_6[1]
         Pin 113 (I/O)  Block K  

  [114]  Input:         s2_6[0]
         Pin 114 (I/O)  Block K  

  [115]  Input:         s5_6[7]
         Pin 36 (I/O)  Block E  

  [116]  Input:         s5_6[6]
         Pin 37 (I/O)  Block E  

  [117]  Input:         s5_6[5]
         Pin 38 (I/O)  Block E  

  [118]  Input:         s5_6[4]
         Pin 39 (I/O)  Block E  

  [119]  Input:         s5_6[3]
         Pin 46 (I/O)  Block F  

  [120]  Input:         s5_6[2]
         Pin 47 (I/O)  Block F  

  [121]  Input:         s5_6[1]
         Pin 48 (I/O)  Block F  

  [122]  Input:         s5_6[0]
         Pin 49 (I/O)  Block F  

  [123]  Input:         s6_7[7]
         Pin 7 (I/O)  Block C  

  [124]  Input:         s6_7[6]
         Pin 8 (I/O)  Block C  

  [125]  Input:         s6_7[5]
         Pin 9 (I/O)  Block C  

  [126]  Input:         s6_7[4]
         Pin 10 (I/O)  Block C  

  [127]  Input:         s6_7[3]
         Pin 17 (I/O)  Block D  

  [128]  Input:         s6_7[2]
         Pin 18 (I/O)  Block D  

  [129]  Input:         s6_7[1]
         Pin 19 (I/O)  Block D  

  [130]  Input:         s6_7[0]
         Pin 20 (I/O)  Block D  

POWER TABLE:

BLOCK   A:    LOW
BLOCK   B:    LOW
BLOCK   D:    HIGH
BLOCK   C:    HIGH
BLOCK   E:    HIGH
BLOCK   F:    HIGH
BLOCK   H:    HIGH
BLOCK   G:    HIGH
BLOCK   I:    HIGH
BLOCK   J:    HIGH
BLOCK   L:    LOW
BLOCK   K:    LOW
BLOCK   M:    LOW
BLOCK   N:    LOW
BLOCK   P:    LOW
BLOCK   O:    HIGH


FANOUT TABLE:

Signal_Src       Fanouts Blk-Mux-------------------------------------


PAL_BLOCK 'A'
[083] Pin   194   I26 
[084] Pin   190   I31 
[085] Pin   191   I30 O30 
[086] Pin   197   I28 
[087] Pin   192   J31 
[088] Pin   195   J12 
[089] Pin   196   J00 
[090] Pin   193   J21 

PAL_BLOCK 'B'
[067] Pin   206   D08 C08 H08 G08 I08 J20 O08 
[069] Pin   202   D14 C19 H14 I14 J32 O14 
[071] Pin   204   D10 C10 E06 F06 
[072] Pin   203   D06 C06 H06 I06 J06 O06 
[074] Pin   201   

PAL_BLOCK 'D'
[027] Pin   16   H24 
[028] Pin   15   J30 
[029] Pin   14   J24 
[030] Pin   13   J09 
[044] Mcell D11  D11 
[045] Mcell D04  D13 
[046] Mcell D00  D19 
[047] Mcell D07  D17 
[127] Pin   17   
[128] Pin   18   
[129] Pin   19   
[130] Pin   20   

PAL_BLOCK 'C'
[015] Mcell C02  C15 I15 
[017] Mcell C15  C21 I21 
[031] Pin   6   C01 
[032] Pin   5   O24 
[033] Pin   4   C14 
[034] Pin   3   H28 
[035] Mcell C14  D03 C23 E03 F03 
[048] Mcell C09  C09 
[049] Mcell C06  C18 
[050] Mcell C13  C28 
[051] Mcell C07  C07 
[123] Pin   7   
[124] Pin   8   
[125] Pin   9   
[126] Pin   10   

PAL_BLOCK 'E'
[023] Pin   35   H07 
[024] Pin   34   H10 
[025] Pin   33   H23 
[026] Pin   32   H33 
[115] Pin   36   
[116] Pin   37   
[117] Pin   38   
[118] Pin   39   

PAL_BLOCK 'F'
[019] Pin   45   I00 
[020] Pin   44   J03 
[021] Pin   43   J17 
[022] Pin   42   H15 
[119] Pin   46   
[120] Pin   47   
[121] Pin   48   
[122] Pin   49   

PAL_BLOCK 'H'
[002] Mcell H03  O05 
[006] Mcell H05  F05 H21 
[007] Mcell H09  E00 H00 
[008] Mcell H14  E13 H13 
[009] Mcell H00  E17 H17 
[010] Mcell H01  E05 H05 
[011] Mcell H12  D32 H03 
[018] Mcell H06  C12 H12 

PAL_BLOCK 'G'
[052] Mcell G09  H11 
[053] Mcell G03  H04 
[054] Mcell G00  H01 O01 

PAL_BLOCK 'I'
[003] Mcell I13  F00 I23 
[036] Mcell I00  C31 G13 
[037] Mcell I06  C17 G12 
[038] Mcell I04  C03 G03 O26 
[039] Mcell I10  C04 G04 

PAL_BLOCK 'J'
[004] Mcell J08  F02 J02 
[005] Mcell J02  F04 J04 
[012] Mcell J03  D07 J07 
[013] Mcell J15  D21 J23 
[014] Mcell J13  D02 I02 J14 
[040] Mcell J06  D12 G15 
[041] Mcell J12  D27 G22 
[042] Mcell J07  D00 G00 
[043] Mcell J05  D20 G01 

PAL_BLOCK 'L'
[091] Pin   123   I17 
[092] Pin   118   I04 
[093] Pin   117   I27 
[094] Pin   119   I07 O07 
[095] Pin   120   J10 
[096] Pin   122   J27 
[097] Pin   124   J08 
[098] Pin   121   J05 

PAL_BLOCK 'K'
[107] Pin   107   
[108] Pin   108   
[109] Pin   109   
[110] Pin   110   
[111] Pin   111   
[112] Pin   112   
[113] Pin   113   
[114] Pin   114   

PAL_BLOCK 'M'
[075] Pin   143   I11 
[076] Pin   137   I03 
[077] Pin   136   I16 
[078] Pin   140   I12 O12 
[079] Pin   141   J15 
[080] Pin   142   J16 
[081] Pin   138   I33 
[082] Pin   139   I10 O10 

PAL_BLOCK 'N'
[070] Pin   149   D22 C22 H22 I29 J22 O09 

PAL_BLOCK 'P'
[099] Pin   168   
[100] Pin   169   
[101] Pin   170   
[102] Pin   171   
[103] Pin   172   
[104] Pin   173   
[105] Pin   174   
[106] Pin   175   

PAL_BLOCK 'O'
[016] Mcell O14  C00 I13 O00 




BLOCK CONFIGURATION TABLES:

   Notes: '*' indicates that the pin is bonded-out


BLOCK 'A': UNUSED

BLOCK 'B': UNUSED

BLOCK 'D': POWER=HIGH
   CONTROL PTERMS:
           OE00 = dboe ;


   SIGNALS CROSS REFERENCE:

ARRAY INPUTS:
Input  Sig_ID   Source     Signal Name
-----  ------   ------     -----------
I32    [011]    MC-H12     enRodBusy
I07    [012]    MC-J03     enttc_register[6]
I21    [013]    MC-J15     enttc_register[5]
I02    [014]    MC-J13     enttc_register[4]
I03    [035]    MC-C14     dboe
I12    [040]    MC-J06     nTTCout[6]
I27    [041]    MC-J12     nTTCout[7]
I00    [042]    MC-J07     nTTCout[5]
I20    [043]    MC-J05     nTTCout[4]
I11    [044]    MC-D11     reg_ttcout[7]
I13    [045]    MC-D04     reg_ttcout[6]
I19    [046]    MC-D00     reg_ttcout[5]
I17    [047]    MC-D07     reg_ttcout[4]
I08    [067]    Pin 206    nOA_rst
I14    [069]    Pin 202    bReadb
I22    [070]    Pin 149    bWriteb
I10    [071]    Pin 204    reg30
I06    [072]    Pin 203    Reg18

SIGNAL FANOUTS
TYPE   Sig_ID Signal Name
----   ------ -----------
OUT    [027]  db[7]
OUT    [028]  db[6]
OUT    [029]  db[5]
OUT    [030]  db[4]
NODE   [044]  reg_ttcout[7]
NODE   [045]  reg_ttcout[6]
NODE   [046]  reg_ttcout[5]
NODE   [047]  reg_ttcout[4]

ARRAY INPUTS AND CLUSTER ALLOCATION TABLES                      

   IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII    CCCCCCCCCCCCCCCC      P C S  R  S   
   0000000000111111111122222222223333 ## 0000000000111111 Pts  O L E  S  L   
MC 0123456789012345678901234567890123 AI 0123456789012345 Used L K T  T  W Node  OE   Pin
00 x-----x-x-x---x----x--x-----------  7 5---------------   3  L - -- -- - (046) VCC [046]
01 --xx------x------x----------------  4 -55-------------   2  H - -- -- F [---] OE0 [030]
02 ----------------------------------  0 --0-------------   -  - - -- -- - [---] GND [---]
03 ----------------------------------  0 ---0------------   -  - - -- -- - [---] GND [---]
04 ------x-x-x-xxx-------x-----------  7 ---55-----------   3  L - -- -- - (045) VCC [045]
05 ----------------------------------  0 -----5----------   -  - - -- -- - [---] GND [---]
06 ----------------------------------  0 ------0---------   -  - - -- -- - [---] GND [---]
07 ------x-x-x---x--x--x-x-----------  7 ------55--------   3  L - -- -- - (047) VCC [047]
08 ----------------------------------  0 --------0-------   -  - - -- -- - [---] GND [---]
09 ---x------xx--------------------x-  4 --------55------   2  H - -- -- F [---] OE0 [027]
10 ---x---x--x--x--------------------  4 ----------05----   2  H - -- -- F [---] OE0 [028]
11 ------x-x-xx--x-------x----x------  7 ----------50----   3  L - -- -- - (044) VCC [044]
12 ----------------------------------  0 ------------5---   -  - - -- -- - [---] GND [---]
13 ----------------------------------  0 -------------5--   -  - - -- -- - [---] GND [---]
14 ----------------------------------  0 --------------0-   -  - - -- -- - [---] GND [---]
15 ---x------x--------x-x------------  4 --------------55   2  H - -- -- F [---] OE0 [029]


BLOCK 'C': POWER=HIGH
   CONTROL PTERMS:
           OE00 = dboe ;
          RST00 = /nOA_rst ;

   BLOCK CLOCKS:
      BLK_CLK 2 (PIN_CLOCK:POL=HIGH) : nLEb2, pin 83



   SIGNALS CROSS REFERENCE:

ARRAY INPUTS:
Input  Sig_ID   Source     Signal Name
-----  ------   ------     -----------
I15    [015]    MC-C02     enttc_register[3]
I00    [016]    MC-O14     sgbB[4]
I21    [017]    MC-C15     enttc_register[1]
I12    [018]    MC-H06     enBCClk
I01    [031]    Pin 6      db[3]
I14    [033]    Pin 4      db[1]
I23    [035]    MC-C14     dboe
I31    [036]    MC-I00     nTTCout[0]
I17    [037]    MC-I06     nTTCout[2]
I03    [038]    MC-I04     nTTCout[1]
I04    [039]    MC-I10     nTTCout[3]
I09    [048]    MC-C09     reg_ttcout[3]
I18    [049]    MC-C06     reg_ttcout[2]
I28    [050]    MC-C13     reg_ttcout[1]
I07    [051]    MC-C07     reg_ttcout[0]
I08    [067]    Pin 206    nOA_rst
I19    [069]    Pin 202    bReadb
I22    [070]    Pin 149    bWriteb
I10    [071]    Pin 204    reg30
I06    [072]    Pin 203    Reg18

SIGNAL FANOUTS
TYPE   Sig_ID Signal Name
----   ------ -----------
NODE   [015]  enttc_register[3]
NODE   [017]  enttc_register[1]
OUT    [031]  db[3]
OUT    [032]  db[2]
OUT    [033]  db[1]
OUT    [034]  db[0]
NODE   [035]  dboe
NODE   [048]  reg_ttcout[3]
NODE   [049]  reg_ttcout[2]
NODE   [050]  reg_ttcout[1]
NODE   [051]  reg_ttcout[0]

ARRAY INPUTS AND CLUSTER ALLOCATION TABLES                      

   IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII    CCCCCCCCCCCCCCCC      P C S  R  S   
   0000000000111111111122222222223333 ## 0000000000111111 Pts  O L E  S  L   
MC 0123456789012345678901234567890123 AI 0123456789012345 Used L K T  T  W Node  OE   Pin
00 ----------x----------x-x----x-----  4 5---------------   2  H - -- -- F [---] OE0 [033]
01 -------x--x-x----------x----------  4 -5-5------------   2  H - -- -- F [---] OE0 [034]
02 -x----x-x------x---x--x-----------  6 --5-------------   2  H 2 -- 00 - (015) VCC [015]
03 ----------------------------------  0 ---0------------   -  - - -- -- - [---] GND [---]
04 ----------------------------------  0 ----5-----------   -  - - -- -- - [---] GND [---]
05 ----------------------------------  0 -----0----------   -  - - -- -- - [---] GND [---]
06 ------x-x-x------xxx--x-----------  7 -----50---------   3  L - -- -- - (049) VCC [049]
07 ------xxx-x--------x--x--------x--  7 ------50--------   3  L - -- -- - (051) VCC [051]
08 ---------xx----x-------x----------  4 -------50-------   2  H - -- -- F [---] OE0 [031]
09 ----x-x-xxx--------x--x-----------  7 --------55------   3  L - -- -- - (048) VCC [048]
10 x---------x-------x----x----------  4 ----------55----   2  H - -- -- F [---] OE0 [032]
11 ----------------------------------  0 -----------0----   -  - - -- -- - [---] GND [---]
12 ----------------------------------  0 ------------0---   -  - - -- -- - [---] GND [---]
13 ---x--x-x-x--------x--x-----x-----  7 ------------50--   3  L - -- -- - (050) VCC [050]
14 ------x---x--------x--------------  3 -------------50-   2  H - -- -- - (035) VCC [035]
15 ------x-x-----x----x-xx-----------  6 --------------55   2  H 2 -- 00 - (017) VCC [017]


BLOCK 'E': POWER=HIGH
   CONTROL PTERMS:
           OE00 = dboe ;


   SIGNALS CROSS REFERENCE:

ARRAY INPUTS:
Input  Sig_ID   Source     Signal Name
-----  ------   ------     -----------
I00    [007]    MC-H09     enttc_register[11]
I13    [008]    MC-H14     enTType
I17    [009]    MC-H00     enBCID
I05    [010]    MC-H01     enL1ID
I03    [035]    MC-C14     dboe
I06    [071]    Pin 204    reg30

SIGNAL FANOUTS
TYPE   Sig_ID Signal Name
----   ------ -----------
OUT    [023]  db[11]
OUT    [024]  db[10]
OUT    [025]  db[9]
OUT    [026]  db[8]

ARRAY INPUTS AND CLUSTER ALLOCATION TABLES                      

   IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII    CCCCCCCCCCCCCCCC      P C S  R  S   
   0000000000111111111122222222223333 ## 0000000000111111 Pts  O L E  S  L   
MC 0123456789012345678901234567890123 AI 0123456789012345 Used L K T  T  W Node  OE   Pin
00 ---x-xx---------------------------  3 5---------------   1  H - -- -- F [---] OE0 [026]
01 ----------------------------------  0 -5--------------   -  - - -- -- - [---] GND [---]
02 ---x--x----------x----------------  3 --5-------------   1  H - -- -- F [---] OE0 [025]
03 ----------------------------------  0 ---5------------   -  - - -- -- - [---] GND [---]
04 ----------------------------------  0 ----5-----------   -  - - -- -- - [---] GND [---]
05 ---x--x------x--------------------  3 -----5----------   1  H - -- -- F [---] OE0 [024]
06 ----------------------------------  0 ------5---------   -  - - -- -- - [---] GND [---]
07 x--x--x---------------------------  3 -------5--------   1  H - -- -- F [---] OE0 [023]
08 ----------------------------------  0 --------5-------   -  - - -- -- - [---] GND [---]
09 ----------------------------------  0 ---------5------   -  - - -- -- - [---] GND [---]
10 ----------------------------------  0 ----------5-----   -  - - -- -- - [---] GND [---]
11 ----------------------------------  0 -----------5----   -  - - -- -- - [---] GND [---]
12 ----------------------------------  0 ------------5---   -  - - -- -- - [---] GND [---]
13 ----------------------------------  0 -------------5--   -  - - -- -- - [---] GND [---]
14 ----------------------------------  0 --------------5-   -  - - -- -- - [---] GND [---]
15 ----------------------------------  0 ---------------5   -  - - -- -- - [---] GND [---]


BLOCK 'F': POWER=HIGH
   CONTROL PTERMS:
           OE00 = dboe ;


   SIGNALS CROSS REFERENCE:

ARRAY INPUTS:
Input  Sig_ID   Source     Signal Name
-----  ------   ------     -----------
I00    [003]    MC-I13     enSABCR2
I02    [004]    MC-J08     enSAECR2
I04    [005]    MC-J02     enttc_register[13]
I05    [006]    MC-H05     enttc_register[12]
I03    [035]    MC-C14     dboe
I06    [071]    Pin 204    reg30

SIGNAL FANOUTS
TYPE   Sig_ID Signal Name
----   ------ -----------
OUT    [019]  db[15]
OUT    [020]  db[14]
OUT    [021]  db[13]
OUT    [022]  db[12]

ARRAY INPUTS AND CLUSTER ALLOCATION TABLES                      

   IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII    CCCCCCCCCCCCCCCC      P C S  R  S   
   0000000000111111111122222222223333 ## 0000000000111111 Pts  O L E  S  L   
MC 0123456789012345678901234567890123 AI 0123456789012345 Used L K T  T  W Node  OE   Pin
00 ---x-xx---------------------------  3 5---------------   1  H - -- -- F [---] OE0 [022]
01 ----------------------------------  0 -5--------------   -  - - -- -- - [---] GND [---]
02 ---xx-x---------------------------  3 --5-------------   1  H - -- -- F [---] OE0 [021]
03 ----------------------------------  0 ---5------------   -  - - -- -- - [---] GND [---]
04 ----------------------------------  0 ----5-----------   -  - - -- -- - [---] GND [---]
05 --xx--x---------------------------  3 -----5----------   1  H - -- -- F [---] OE0 [020]
06 ----------------------------------  0 ------5---------   -  - - -- -- - [---] GND [---]
07 x--x--x---------------------------  3 -------5--------   1  H - -- -- F [---] OE0 [019]
08 ----------------------------------  0 --------5-------   -  - - -- -- - [---] GND [---]
09 ----------------------------------  0 ---------5------   -  - - -- -- - [---] GND [---]
10 ----------------------------------  0 ----------5-----   -  - - -- -- - [---] GND [---]
11 ----------------------------------  0 -----------5----   -  - - -- -- - [---] GND [---]
12 ----------------------------------  0 ------------5---   -  - - -- -- - [---] GND [---]
13 ----------------------------------  0 -------------5--   -  - - -- -- - [---] GND [---]
14 ----------------------------------  0 --------------5-   -  - - -- -- - [---] GND [---]
15 ----------------------------------  0 ---------------5   -  - - -- -- - [---] GND [---]


BLOCK 'H': POWER=HIGH
   CONTROL PTERMS:
          RST00 = /nOA_rst ;

   BLOCK CLOCKS:
      BLK_CLK 2 (PIN_CLOCK:POL=HIGH) : nLEb2, pin 83



   SIGNALS CROSS REFERENCE:

ARRAY INPUTS:
Input  Sig_ID   Source     Signal Name
-----  ------   ------     -----------
I21    [006]    MC-H05     enttc_register[12]
I00    [007]    MC-H09     enttc_register[11]
I13    [008]    MC-H14     enTType
I17    [009]    MC-H00     enBCID
I05    [010]    MC-H01     enL1ID
I03    [011]    MC-H12     enRodBusy
I12    [018]    MC-H06     enBCClk
I15    [022]    Pin 42     db[12]
I07    [023]    Pin 35     db[11]
I10    [024]    Pin 34     db[10]
I23    [025]    Pin 33     db[9]
I33    [026]    Pin 32     db[8]
I24    [027]    Pin 16     db[7]
I28    [034]    Pin 3      db[0]
I11    [052]    MC-G09     eclL1A
I04    [053]    MC-G03     eclBCR
I01    [054]    MC-G00     eclECR
I08    [067]    Pin 206    nOA_rst
I14    [069]    Pin 202    bReadb
I22    [070]    Pin 149    bWriteb
I06    [072]    Pin 203    Reg18

SIGNAL FANOUTS
TYPE   Sig_ID Signal Name
----   ------ -----------
OUT    [000]  idTRIG
OUT    [001]  idBCR
OUT    [002]  idECR
NODE   [006]  enttc_register[12]
NODE   [007]  enttc_register[11]
OUT    [008]  enTType
OUT    [009]  enBCID
OUT    [010]  enL1ID
OUT    [011]  enRodBusy
OUT    [018]  enBCClk

ARRAY INPUTS AND CLUSTER ALLOCATION TABLES                      

   IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII    CCCCCCCCCCCCCCCC      P C S  R  S   
   0000000000111111111122222222223333 ## 0000000000111111 Pts  O L E  S  L   
MC 0123456789012345678901234567890123 AI 0123456789012345 Used L K T  T  W Node  OE   Pin
00 ------x-x-----x--x----xx----------  6 5---------------   2  H 2 -- 00 F (009) VCC [009]
01 -----xx-x-----x-------x----------x  6 -5--------------   2  H 2 -- 00 F (010) VCC [010]
02 ----------------------------------  0 --5-------------   -  - - -- -- - [---] GND [---]
03 -x--------------------------------  1 ---5------------   1  H - -- -- F (002) VCC [002]
04 ----------------------------------  0 ----0-----------   -  - - -- -- - [---] GND [---]
05 ------x-x-----xx-----xx-----------  6 ----55----------   2  H 2 -- 00 - (006) VCC [006]
06 ------x-x---x-x-------x-----x-----  6 ------5---------   2  H 2 -- 00 F (018) VCC [018]
07 ----------------------------------  0 -------5--------   -  - - -- -- - [---] GND [---]
08 ----x-----------------------------  1 --------1-------   1  H - -- -- F (001) VCC [001]
09 x-----xxx-----x-------x-----------  6 --------45------   2  H 2 -- 00 - (007) VCC [007]
10 ----------------------------------  0 ----------5-----   -  - - -- -- - [---] GND [---]
11 -----------x----------------------  1 -----------1----   1  H - -- -- F (000) VCC [000]
12 ---x--x-x-----x-------x-x---------  6 -----------45---   2  H 2 -- 00 F (011) VCC [011]
13 ----------------------------------  0 -------------5--   -  - - -- -- - [---] GND [---]
14 ------x-x-x--xx-------x-----------  6 --------------5-   2  H 2 -- 00 F (008) VCC [008]
15 ----------------------------------  0 ---------------5   -  - - -- -- - [---] GND [---]


BLOCK 'G': POWER=HIGH
   CONTROL PTERMS:
          RST00 = /nOA_rst ;

   BLOCK CLOCKS:
      BLK_CLK 1 (PIN_CLOCK:POL=HIGH) : clk6, pin 74



   SIGNALS CROSS REFERENCE:

ARRAY INPUTS:
Input  Sig_ID   Source     Signal Name
-----  ------   ------     -----------
I13    [036]    MC-I00     nTTCout[0]
I12    [037]    MC-I06     nTTCout[2]
I03    [038]    MC-I04     nTTCout[1]
I04    [039]    MC-I10     nTTCout[3]
I15    [040]    MC-J06     nTTCout[6]
I22    [041]    MC-J12     nTTCout[7]
I00    [042]    MC-J07     nTTCout[5]
I01    [043]    MC-J05     nTTCout[4]
I08    [067]    Pin 206    nOA_rst

SIGNAL FANOUTS
TYPE   Sig_ID Signal Name
----   ------ -----------
OUT    [052]  eclL1A
OUT    [053]  eclBCR
OUT    [054]  eclECR
OUT    [055]  eclCAL
OUT    [056]  eclFER
OUT    [057]  eclSpare
OUT    [058]  eclID
OUT    [059]  eclTT

ARRAY INPUTS AND CLUSTER ALLOCATION TABLES                      

   IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII    CCCCCCCCCCCCCCCC      P C S  R  S   
   0000000000111111111122222222223333 ## 0000000000111111 Pts  O L E  S  L   
MC 0123456789012345678901234567890123 AI 0123456789012345 Used L K T  T  W Node  OE   Pin
00 ---x----x-------------------------  2 1---------------   1  H 1 -- 00 F (054) VCC [054]
01 ----x---x-------------------------  2 41--------------   1  H 1 -- 00 F (055) VCC [055]
02 x-------x-------------------------  2 -45-------------   1  H 1 -- 00 F (059) VCC [059]
03 --------x---x---------------------  2 ---5------------   1  H 1 -- 00 F (053) VCC [053]
04 -x------x-------------------------  2 ----5-----------   1  H 1 -- 00 F (058) VCC [058]
05 ----------------------------------  0 -----5----------   -  - - -- -- - [---] GND [---]
06 ----------------------------------  0 ------5---------   -  - - -- -- - [---] GND [---]
07 --------x-------------x-----------  2 -------5--------   1  H 1 -- 00 F (057) VCC [057]
08 ----------------------------------  0 --------5-------   -  - - -- -- - [---] GND [---]
09 --------x----x--------------------  2 ---------5------   1  H 1 -- 00 F (052) VCC [052]
10 ----------------------------------  0 ----------5-----   -  - - -- -- - [---] GND [---]
11 --------x------x------------------  2 -----------5----   1  H 1 -- 00 F (056) VCC [056]
12 ----------------------------------  0 ------------5---   -  - - -- -- - [---] GND [---]
13 ----------------------------------  0 -------------5--   -  - - -- -- - [---] GND [---]
14 ----------------------------------  0 --------------5-   -  - - -- -- - [---] GND [---]
15 ----------------------------------  0 ---------------5   -  - - -- -- - [---] GND [---]


BLOCK 'I': POWER=HIGH
   CONTROL PTERMS:
          RST00 = /nOA_rst ;

   BLOCK CLOCKS:
      BLK_CLK 2 (PIN_CLOCK:POL=HIGH) : nLEb2, pin 83



   SIGNALS CROSS REFERENCE:

ARRAY INPUTS:
Input  Sig_ID   Source     Signal Name
-----  ------   ------     -----------
I23    [003]    MC-I13     enSABCR2
I02    [014]    MC-J13     enttc_register[4]
I15    [015]    MC-C02     enttc_register[3]
I13    [016]    MC-O14     sgbB[4]
I21    [017]    MC-C15     enttc_register[1]
I00    [019]    Pin 45     db[15]
I08    [067]    Pin 206    nOA_rst
I14    [069]    Pin 202    bReadb
I29    [070]    Pin 149    bWriteb
I06    [072]    Pin 203    Reg18
I11    [075]    Pin 143    SATRIG
I03    [076]    Pin 137    SACAL
I16    [077]    Pin 136    SABCR1
I12    [078]    Pin 140    SAECR1
I33    [081]    Pin 138    SABCR2
I10    [082]    Pin 139    SAECR2
I26    [083]    Pin 194    L1Ain
I31    [084]    Pin 190    BCRin
I30    [085]    Pin 191    ECRin
I28    [086]    Pin 197    CALin
I17    [091]    Pin 123    seqTRIG
I04    [092]    Pin 118    seqCAL
I27    [093]    Pin 117    seqBCR
I07    [094]    Pin 119    seqECR

SIGNAL FANOUTS
TYPE   Sig_ID Signal Name
----   ------ -----------
OUT    [003]  enSABCR2
OUT    [036]  nTTCout[0]
OUT    [037]  nTTCout[2]
OUT    [038]  nTTCout[1]
OUT    [039]  nTTCout[3]

ARRAY INPUTS AND CLUSTER ALLOCATION TABLES                      

   IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII    CCCCCCCCCCCCCCCC      P C S  R  S   
   0000000000111111111122222222223333 ## 0000000000111111 Pts  O L E  S  L   
MC 0123456789012345678901234567890123 AI 0123456789012345 Used L K T  T  W Node  OE   Pin
00 -----------x-----x---x----x-------  4 5---------------   2  H - -- -- F (036) VCC [036]
01 ----------------------------------  0 -5--------------   -  - - -- -- - [---] GND [---]
02 ----------------------------------  0 --5-------------   -  - - -- -- - [---] GND [---]
03 ----------------------------------  0 ---0------------   -  - - -- -- - [---] GND [---]
04 -------x--x-xx----------------x---  5 ---55-----------   2  H - -- -- F (038) VCC [038]
05 ----------------------------------  0 -----0----------   -  - - -- -- - [---] GND [---]
06 ---------------xx----------x---x-x  5 -----55---------   2  H - -- -- F (037) VCC [037]
07 ----------------------------------  0 -------5--------   -  - - -- -- - [---] GND [---]
08 ----------------------------------  0 --------5-------   -  - - -- -- - [---] GND [---]
09 ----------------------------------  0 ---------0------   -  - - -- -- - [---] GND [---]
10 --xxx-----------------------x-----  4 ---------55-----   2  H - -- -- F (039) VCC [039]
11 ----------------------------------  0 -----------5----   -  - - -- -- - [---] GND [---]
12 ----------------------------------  0 ------------0---   -  - - -- -- - [---] GND [---]
13 x-----x-x-----x--------x-----x----  6 ------------55--   2  H 2 -- 00 F (003) VCC [003]
14 ----------------------------------  0 --------------5-   -  - - -- -- - [---] GND [---]
15 ----------------------------------  0 ---------------5   -  - - -- -- - [---] GND [---]


BLOCK 'J': POWER=HIGH
   CONTROL PTERMS:
          RST00 = /nOA_rst ;

   BLOCK CLOCKS:
      BLK_CLK 2 (PIN_CLOCK:POL=HIGH) : nLEb2, pin 83



   SIGNALS CROSS REFERENCE:

ARRAY INPUTS:
Input  Sig_ID   Source     Signal Name
-----  ------   ------     -----------
I02    [004]    MC-J08     enSAECR2
I04    [005]    MC-J02     enttc_register[13]
I07    [012]    MC-J03     enttc_register[6]
I23    [013]    MC-J15     enttc_register[5]
I14    [014]    MC-J13     enttc_register[4]
I03    [020]    Pin 44     db[14]
I17    [021]    Pin 43     db[13]
I30    [028]    Pin 15     db[6]
I24    [029]    Pin 14     db[5]
I09    [030]    Pin 13     db[4]
I20    [067]    Pin 206    nOA_rst
I32    [069]    Pin 202    bReadb
I22    [070]    Pin 149    bWriteb
I06    [072]    Pin 203    Reg18
I15    [079]    Pin 141    SAFER
I16    [080]    Pin 142    SASpare
I31    [087]    Pin 192    FERin
I12    [088]    Pin 195    Sparein
I00    [089]    Pin 196    TTin
I21    [090]    Pin 193    IDin
I10    [095]    Pin 120    seqFER
I27    [096]    Pin 122    seqSpare
I08    [097]    Pin 124    seqTT
I05    [098]    Pin 121    seqID

SIGNAL FANOUTS
TYPE   Sig_ID Signal Name
----   ------ -----------
OUT    [004]  enSAECR2
NODE   [005]  enttc_register[13]
NODE   [012]  enttc_register[6]
NODE   [013]  enttc_register[5]
NODE   [014]  enttc_register[4]
OUT    [040]  nTTCout[6]
OUT    [041]  nTTCout[7]
OUT    [042]  nTTCout[5]
OUT    [043]  nTTCout[4]

ARRAY INPUTS AND CLUSTER ALLOCATION TABLES                      

   IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII    CCCCCCCCCCCCCCCC      P C S  R  S   
   0000000000111111111122222222223333 ## 0000000000111111 Pts  O L E  S  L   
MC 0123456789012345678901234567890123 AI 0123456789012345 Used L K T  T  W Node  OE   Pin
00 ----------------------------------  0 5---------------   -  - - -- -- - [---] GND [---]
01 ----------------------------------  0 -0--------------   -  - - -- -- - [---] GND [---]
02 ----x-x----------x--x-x---------x-  6 -50-------------   2  H 2 -- 00 - (005) VCC [005]
03 ------xx------------x-x-------x-x-  6 --55------------   2  H 2 -- 00 - (012) VCC [012]
04 ----------------------------------  0 ----5-----------   -  - - -- -- - [---] GND [---]
05 -----x---------------x------------  2 -----5----------   1  H - -- -- F (043) VCC [043]
06 ----------x----x-------x-------x--  4 ------5---------   2  H - -- -- F (040) VCC [040]
07 x-------x-------------------------  2 -------5--------   1  H - -- -- F (042) VCC [042]
08 --xx--x-------------x-x---------x-  6 --------5-------   2  H 2 -- 00 F (004) VCC [004]
09 ----------------------------------  0 ---------5------   -  - - -- -- - [---] GND [---]
10 ----------------------------------  0 ----------5-----   -  - - -- -- - [---] GND [---]
11 ----------------------------------  0 -----------0----   -  - - -- -- - [---] GND [---]
12 -------x----x---x----------x------  4 -----------55---   2  H - -- -- F (041) VCC [041]
13 ------x--x----x-----x-x---------x-  6 -------------5--   2  H 2 -- 00 - (014) VCC [014]
14 ----------------------------------  0 --------------0-   -  - - -- -- - [---] GND [---]
15 ------x-------------x-xxx-------x-  6 --------------55   2  H 2 -- 00 - (013) VCC [013]


BLOCK 'L': UNUSED

BLOCK 'K': UNUSED

BLOCK 'M': UNUSED

BLOCK 'N': UNUSED

BLOCK 'P': UNUSED

BLOCK 'O': POWER=HIGH
   CONTROL PTERMS:
          RST00 = /nOA_rst ;

   BLOCK CLOCKS:
      BLK_CLK 2 (PIN_CLOCK:POL=HIGH) : nLEb2, pin 83



   SIGNALS CROSS REFERENCE:

ARRAY INPUTS:
Input  Sig_ID   Source     Signal Name
-----  ------   ------     -----------
I05    [002]    MC-H03     idECR
I00    [016]    MC-O14     sgbB[4]
I24    [032]    Pin 5      db[2]
I26    [038]    MC-I04     nTTCout[1]
I01    [054]    MC-G00     eclECR
I08    [067]    Pin 206    nOA_rst
I14    [069]    Pin 202    bReadb
I09    [070]    Pin 149    bWriteb
I06    [072]    Pin 203    Reg18
I12    [078]    Pin 140    SAECR1
I10    [082]    Pin 139    SAECR2
I30    [085]    Pin 191    ECRin
I07    [094]    Pin 119    seqECR

SIGNAL FANOUTS
TYPE   Sig_ID Signal Name
----   ------ -----------
OUT    [016]  sgbB[4]
OUT    [060]  sgbB[7]
OUT    [061]  sgbB[6]
OUT    [062]  sgbB[5]
OUT    [063]  sgbB[3]
OUT    [064]  sgbB[2]
OUT    [065]  sgbB[1]
OUT    [066]  sgbB[0]

ARRAY INPUTS AND CLUSTER ALLOCATION TABLES                      

   IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII    CCCCCCCCCCCCCCCC      P C S  R  S   
   0000000000111111111122222222223333 ## 0000000000111111 Pts  O L E  S  L   
MC 0123456789012345678901234567890123 AI 0123456789012345 Used L K T  T  W Node  OE   Pin
00 ------------x---------------------  1 1---------------   1  H - -- -- F (060) VCC [060]
01 ------------------------------x---  1 45--------------   1  H - -- -- F (062) VCC [062]
02 ----------------------------------  0 --5-------------   -  - - -- -- - [---] GND [---]
03 ----------x-----------------------  1 ---1------------   1  H - -- -- F (061) VCC [061]
04 -x--------------------------------  1 ---41-----------   1  H - -- -- F (065) VCC [065]
05 -----x----------------------------  1 ----45----------   1  H - -- -- F (066) VCC [066]
06 ----------------------------------  0 ------5---------   -  - - -- -- - [---] GND [---]
07 -------x--------------------------  1 -------5--------   1  H - -- -- F (063) VCC [063]
08 ----------------------------------  0 --------5-------   -  - - -- -- - [---] GND [---]
09 --------------------------x-------  1 ---------5------   1  H - -- -- F (064) VCC [064]
10 ----------------------------------  0 ----------5-----   -  - - -- -- - [---] GND [---]
11 ----------------------------------  0 -----------5----   -  - - -- -- - [---] GND [---]
12 ----------------------------------  0 ------------5---   -  - - -- -- - [---] GND [---]
13 ----------------------------------  0 -------------0--   -  - - -- -- - [---] GND [---]
14 x-----x-xx----x---------x---------  6 -------------55-   2  H 2 -- 00 F (016) VCC [016]
15 ----------------------------------  0 ---------------5   -  - - -- -- - [---] GND [---]




M4-256/128 SUCCEEDED FOR 67 FUNCTIONS

