"$Id: pld7.src,v 1.18 2001/11/14 20:12:25 warren Exp $
"=============================================================================
#TITLE	 'ATLAS TIM	PLD7:	RAM Interface'	;
#ENGINEER 'Martin	Postranecky	/ Dominic A	Hayes';
#COMPANY	 'University College	London';
#COMMENT	 '';
"=============================================================================
"$Log: pld7.src,v $
"Revision 1.18  2001/11/14 20:12:25  warren
"start of unimplimented test code
"
"Revision 1.17  2001/08/30 12:20:50  warren
"Tidied, Capitalization
"
"Revision 1.16  2001/08/08 18:42:22  warren
"and signal names case names
"
"Revision 1.15  2001/07/23 11:18:43  warren
"renamed signals with proper polarity n prefixes and removed LOW_TRUEs
"
"Revision 1.14  2001/07/19 10:45:06  warren
"removed unused spare bus lines
"
"Revision 1.13  2001/07/16 13:13:31  warren
"*** empty log message ***
"
"Revision	1.12	2001/06/08 18:23:26	warren
"Added pins fir testpoints
"
"Revision 1.11	 2001/04/25	19:03:53	 warren
"Brand new simulation file, so I	tidies the code/pi too!
"
"Revision 1.10	 2001/04/23	17:01:32	 warren
"jbl changed the SeqStopCount	to	be	CLOCKED_BY SeqClk
"					  SinkStopClock to be CLOCKED_BY	/SinkClk
"
"Revision 1.9	2001/04/09 16:41:25	warren
"Added inhibits to backplane sig	outputs
"
"Revision 1.8	2001/04/03 15:45:38	warren
"Added 4	clock	delay	between source	and sink
"


"=============================================================================

"MODS
" yes,	they are	expected!
"23mar00	rega15 regend -->	reg1a	reg1c.
"			told you!
"06apr00	made RAM	control line OUTPUTs	low true	eg	nSinkWrEn =	/SinkWrEn
"				(NB still a	NODE)
"			a14 lines added (LOW)
"23may00	oareset -> nOA_rst.
"			i/p RunMode	added.
"03jul	RAMselect, StartSink, StartSeq i/ps	added	 (function undefined).
"			SinkBusy	o/p added (logic undefined).
"04jul00	VME enables	restructed.	 VmeWrEn	->	VmeEn
"06jul00	SeqVmeEn	= /SinkVmeEn.
"11jul00	db	pins reassigned to fitter defaults.
"12jul00	seqTRIG et al clocked by SeqClk (clk7).
"			SinkD	o/p now clocked by SeqClk (clk7)
"				[eqiv	to	ttcout clocked	in	by	SinkClk].
"17jul00	db	o/ps reverted to original (constrined)	pins.
"			various jbl	mods.
"			SinkWeClk deleted	SinkClk used instead
"			Reading,	writing,	OE, and WrEn of RAM
"	NB		RAM ouput disable	to	output in high	Z = 6ns (-15 grade RAM).
"			SinkCountEn	code added (same as SeqCountEn).
"11sep00	Regxx, nLEb2, bReadb,	bWriteb now	HIGH_TRUE.
"18sep00	SinkD	unclocked pass-through option	(on VME write)	added.
"26sep00	DEFAULT_TO LAST_VALUE added to some	register	definitions.
"29sep00	now nSeqWrEn =	/(/nLEb2		AND  SeqRamWrAccess)		&
"			SinkWrEn	=	(SinkCountEn AND /SinkOE AND SinkClk) OR
"				(/nLEb2 AND SeqRamWrAccess).
"02oct00	Added	CLK_EN_BY to reg1A and reg1c + tidied bWriteb logic MRMW
"01Nov00	Changed timing	& resets	for SeqCount and SeqCountEn (& Sink...) regs.
"21Mar01	Removed LOW_TRUE from nOA_rst	and created	OA_rst =	/nOA_rst	and "			 "				 substituded in code
"02Apr01	Added	4 clocks	delay	to	the sink	counter enable
"05Apr01	Used SeqCountEn to enable the	backplane data	outputs.	(fiTTing	requ.)
"			 the building of redundent	NODEs	for each	pin. CALled	_seqTRIG	for eq.
"xxApr01	jbl synced up the	..Stops with respective	clocks for no glichiness
"24Apr01	Rearranged code for legibilty
"08Jun01	Added	outputs XSeqTRIG,	XSeqClk1, XSeqClk2 for debug/test points
"03Aug01 renamed eclTRIG --> eclL1A



"=============================================================================
"											GLOBAL SIGNAL DECLARATIONS
"=============================================================================

"Reset and RunMode
"-----------------

INPUT		nOA_rst;							"low true Board reset.
VIRTUAL	NODE		OA_rst;
			OA_rst =	/nOA_rst;


INPUT		RunMode;


"-----------------------------------------------------------------------------
"Clocks
"------

INPUT		SeqClk;							"Sequncer counter	clock.
INPUT		SinkClk;							"Sink	counter clock.


"----------------------------------------------------------------------------
"VME and	Registers
"-----------------


INPUT		RAMselect;						"SRAM	access (bdsel AND	a15).

BIPUT		db[15..0]						"VME data bus.
				ENABLED_BY dboe;
NODE		dboe;

INPUT		bWriteb;							"BufFERed VME write.
INPUT		bReadb;							"BufFERed VME read.
INPUT		ab[15..1];						"bufFERed address	bus





"=============================================================================
" Common	SEQ/SINK	logic.

NODE		SinkGoFF
				CLOCKED_BY	SinkClk
				RESET_BY	OA_rst;


NODE		RegisterEnSeqSink[15..0]	"Reg1A: Enable	Register
				CLOCKED_BY nLEb2
				CLOCK_ENABLED_BY (bWriteb and	Reg1A)
				RESET_BY	OA_rst;
				
				

			"ENseqTRIG	 =	RegisterEnSeqSink[0];
			"ENseqECR	 =	RegisterEnSeqSink[1];
			"ENseqBCR	 =	RegisterEnSeqSink[2];
			"ENseqCAL	 =	RegisterEnSeqSink[3];
			"ENseqID		 =	RegisterEnSeqSink[4];
			"ENseqTT		 =	RegisterEnSeqSink[5];
			"ENseqFER	 =	RegisterEnSeqSink[6];
			"ENseqSpare	 =	RegisterEnSeqSink[7];

			"SeqReset	 =	RegisterEnSeqSink[ 9];
			"SeqGo		 =	RegisterEnSeqSink[10];
			"SeqCyclicEn =	RegisterEnSeqSink[11];
			"SinkVmeEn;	 = RegisterEnSeqSink[12];
			"SinkReset	 = RegisterEnSeqSink[13];
			"SinkGo		 = RegisterEnSeqSink[14];
			"SinkStartEn = RegisterEnSeqSink[15];
			


RegisterEnSeqSink[15..0] =	db[15..0];

NODE		RegisterEnd[15..0]			"Reg1C: Stores	VME loadable count limit.
				CLOCKED_BY nLEb2
				CLOCK_ENABLED_BY (bWriteb and	Reg1C)
				RESET_BY	OA_rst;

			RegisterEnd[15..0] =	db[15..0];



"=============================================================================
" S E	Q	RAM control
"=============================================================================




NODE		SeqReset,
			SeqGo,
			SeqCyclicEn;
			"SeqVmeEn,

			SeqReset		 =	RegisterEnSeqSink[ 9];
			SeqGo			 =	RegisterEnSeqSink[10];
			SeqCyclicEn	 =	RegisterEnSeqSink[11];
			"SeqVmeEn	 =	/SinkVmeEn;	" = /RegisterEnSeqSink[12];


INPUT		StartSeq;

NODE		SeqGoFF
				CLOCKED_BY SeqClk
				RESET_BY	OA_rst;
			SeqGoFF.D =	SeqGo;

NODE		SeqCountStop
				CLOCKED_BY SeqClk
				RESET_BY	  OA_rst
				DEFAULT_TO 0;

NODE		SeqCountEnClk
				CLOCKED_BY SeqClk
				RESET_BY	OA_rst;
			SeqCountEnClk = (SeqGoFF OR StartSeq OR SinkGoFF);

NODE		SeqCountEn
				CLOCKED_BY SeqCountEnClk
				RESET_BY	SeqCountEnReset;
			SeqCountEn		 =	1;		

NODE		SeqCountEnReset;
			SeqCountEnReset =	(/SeqCyclicEn AND	SeqCountStop) 
										OR SeqReset OR OA_rst;
																				

NODE		SeqCount[14]
				CLOCKED_BY SeqClk
				CLOCK_ENABLED_BY SeqCountEn
				RESET_BY	SeqReset	OR	OA_rst;


BIPUT		SeqD[7..0]								"sequencer RAM	data.
				ENABLED_BY SeqRamWrAccess;


OUTPUT	SeqBusy;
			SeqBusy	= SeqCountEn;


OUTPUT	seqTRIG,
			seqECR,
			seqBCR,
			seqCAL,
			seqID,
			seqTT,
			seqFER,
			seqSpare;


NODE		_seqTRIG,
			_seqECR,
			_seqBCR,
			_seqCAL,
			_seqID,
			_seqTT,
			_seqFER,
			_seqSpare
				CLOCKED_BY SeqClk	  "clk7
				RESET_BY	OA_rst;


			_seqTRIG	 =	SeqD[0] AND RegisterEnSeqSink[0];
			_seqECR	 =	SeqD[1] AND RegisterEnSeqSink[1];
			_seqBCR	 =	SeqD[2] AND RegisterEnSeqSink[2];
			_seqCAL	 =	SeqD[3] AND RegisterEnSeqSink[3];
			_seqID	 =	SeqD[4] AND RegisterEnSeqSink[4];
			_seqTT	 =	SeqD[5] AND RegisterEnSeqSink[5];
			_seqFER	 =	SeqD[6] AND RegisterEnSeqSink[6];
			_seqSpare =	SeqD[7] AND RegisterEnSeqSink[7];


			seqTRIG	 =	 _seqTRIG  AND SeqCountEn; "*** note CountEn may arrive only just in time!
			seqECR	 =	 _seqECR	  AND SeqCountEn;
			seqBCR	 =	 _seqBCR	  AND SeqCountEn;
			seqCAL	 =	 _seqCAL	  AND SeqCountEn;
			seqID		 =	 _seqID	  AND SeqCountEn;
			seqTT		 =	 _seqTT	  AND SeqCountEn;
			seqFER	 =	 _seqFER	  AND SeqCountEn;
			seqSpare	 =	 _seqSpare AND SeqCountEn;





"-------------------------------------------------------------------------
"Seq RAM	Access
"--------------

NODE		SeqRamWrAccess;
NODE		SeqRamRdAccess;

OUTPUT	SeqA[14..0];							"sequencer RAM	address.
OUTPUT  nSeqWrEn;									"RAM Write Enable	LOW_TRUE
OUTPUT  nSeqOE;									"RAM Output	Enable LOW_TRUE
OUTPUT  nSeqCS;									"RAM Chip Select LOW_TRUE


			IF	(SeqCount =	RegisterEnd[13..0]) THEN
				SeqCount	= 0; " *** added for	synchronous	reset
				SeqCountStop =	1;
				
			ELSE
				SeqCount	= SeqCount .+.	1;
			
			END IF;

			
			IF	(RAMselect)	THEN
				SeqA[13..0]	= ab[14..1];
			
			ELSE
				SeqA[13..0]	= SeqCount;
			
			END IF;

			
			SeqA[14]	= 0;

			SeqRamWrAccess	= RAMselect	AND bWriteb;
			SeqRamRdAccess	= RAMselect	AND bReadb;

			nSeqWrEn	= /(/nLEb2	  AND	 SeqRamWrAccess);
			nSeqOE	= /( (SeqCountEn AND	/SeqRamWrAccess) OR SeqRamRdAccess );
			nSeqCS	= 0;




"=============================================================================
" S I	N K  RAM	control
"=============================================================================


INPUT		StartSink;

INPUT		eclSpare,
			eclFER,
			eclTT,
			eclID,
			eclCAL,
			eclBCR,
			eclECR,
			eclL1A;	"*** was eclTRIG


NODE		
			SinkReset,
			SinkGo,	
			SinkStartEn;
			"SinkVmeEn


			SinkReset	= RegisterEnSeqSink[13];
			SinkGo		= RegisterEnSeqSink[14];
			SinkStartEn	= RegisterEnSeqSink[15];
			"SinkVmeEn	 =	RegisterEnSeqSink[12];

			SinkGoFF	= SinkGo;


NODE		SinkGoDelay[5..1]
				CLOCKED_BY	SinkClk
				RESET_BY		OA_rst;
			
			SinkGoDelay[5..2]	= SinkGoDelay[4..1];
			SinkGoDelay[1]	= SinkGoFF;


NODE		SinkCountEnClk
				CLOCKED_BY /SinkClk
				RESET_BY	OA_rst;
			"SinkCountEnClk.D	= (SinkGoFF	OR	StartSink);
			SinkCountEnClk	= (SinkGoDelay[4]	OR	StartSink);


NODE		SinkCountEn
				CLOCKED_BY SinkCountEnClk
				RESET_BY	SinkCountEnReset;
			SinkCountEn		  = 1;		"Data	input	to	SinkCountEn	FF. (CLOCKED_BY SinkGo).

OUTPUT	SinkBusy;						"JBL o/p.
			SinkBusy	= SinkCountEn;

NODE		SinkCount[14]
				CLOCKED_BY /SinkClk
				CLOCK_ENABLED_BY SinkCountEn
				RESET_BY	SinkReset OR OA_rst;	" SinkCountReset;
"NODE		 SinkCountReset;

NODE		SinkCountStop
				CLOCKED_BY /SinkClk
				RESET_BY	  OA_rst
				DEFAULT_TO 0;

NODE		SinkCountEnReset;
			SinkCountEnReset = (/SeqCyclicEn	AND SinkCountStop) OR SinkReset OR OA_rst;			 "SinkCountEn FF Reset.
			"SinkCountReset	= SinkReset	OR	OA_rst;	 "Counter Reset.


NODE		SinkFFin[7..0]				  "sink RAM	data.
				 CLOCKED_BY	SinkClk
				 RESET_BY OA_rst;
			SinkFFin[7..0]	= [	eclSpare,
										eclFER,
										eclTT,
										eclID,
										eclCAL,
										eclBCR,
										eclECR,
										eclL1A	];

NODE		SinkFFout[7..0]				"sink	RAM data.
				 CLOCKED_BY	/SinkClk
				 RESET_BY OA_rst;
			SinkFFout =	SinkFFin;




OUTPUT	SinkA[14..0];		"sink	RAM address.

			IF	(SinkCount = RegisterEnd[13..0])	THEN
				SinkCount =	0;
				SinkCountStop = 1;

			ELSE
				SinkCount =	SinkCount .+. 1;

			END IF;



"--------------------------------------------------------------------------------
"*** below is a proposal for SmartSinkMode to ensure capture of L1A in sink
"This should be used no sink wrap-around 
"
"NODE		SmartSinkMode;
"			SmartSinkMode = RegisterEnSeqSink[12];

"NODE		 qL1A
"         	CLOCKED_BY eclL1A
"         	RESET_BY /SmartSinkMode OR OA_rst;
"         qL1A = 1;


"			IF	(SinkCount = RegisterEnd[13..0])	THEN
"				SinkCount =	0;
"				SinkCountStop = 1;

"			ELSIF (SmartSinkMode AND eclBCR AND /qL1A) THEN
"				SinkCount = 0;
				   
"			ELSE
"				SinkCount =	SinkCount .+. 1;
"				
"			END IF;
"---------------------------------------------------------------------------------			
			
			
			
			
			
			
			

			IF	(RAMselect)	THEN
				SinkA[13..0] =	ab[14..1];
			ELSE
				SinkA[13..0] =	SinkCount;
			END IF;

			SinkA[14] =	0;


BIPUT		SinkD[7..0]
				 ENABLED_BY	/SinkOE;


OUTPUT	nSinkWrEn;
			nSinkWrEn =	/((SinkCountEn AND /RAMselect AND /SinkClk)
							OR	(/nLEb2 AND SeqRamWrAccess));
			" ***added / to SinkClk	for better timing

NODE		SinkOE;
			SinkOE	=	RAMselect AND bReadb;

OUTPUT	nSinkOE;									 "RAM	Output Enable LOW_TRUE
			nSinkOE	 =	/SinkOE;


OUTPUT	nSinkCS;									 "RAM	Chip Select	LOW_TRUE
			nSinkCS	 =	 0;


			" NB this covers the	VME write to the Sink RAM
			"----------------------------------------------
			IF	(bWriteb	AND RAMselect)	THEN
				SinkD[7..0]	= db[15..8];		"VME writes	sink RAM	data.

			ELSE
				SinkD[7..0]	= SinkFFout[7..0];
		
			END IF;


"==============================================================================
"V	M E
"==============================================================================

INPUT		nLEb2;								"VME register clock.
INPUT		Reg1A, Reg1C;					"Register enables.


			IF	(bWriteb	AND RAMselect)	THEN		"RAMselect precludes	assertion of Reg lines.
					SeqD	= db[7..0];					"VME writes	seq RAM data.
			END IF;

			" ** NB this is defined	in	the Sink	RAM Control	section **
			"		 SinkD =	db[15..8];		 "VME	writes sink	RAM data.



"--------------------------------------------
"VME READ
"--------
			IF	(bReadb)	THEN
				IF	(RAMselect)	THEN
					db[7..0]	 =	SeqD[7..0];						"VME READs seq	RAM data.
					db[15..8] =	SinkD[7..0];					"VME READs sink RAM data.
				ELSIF	(Reg1A) THEN
					db	= RegisterEnSeqSink;						"VME read Register
				ELSIF	(Reg1C) THEN
					db[15..0] =	RegisterEnd;
				END IF;
			END IF;

			dboe = bReadb AND	(Reg1A OR Reg1C OR RAMSelect);	  "databus output	enable.



"==============================================================================
"TEST	POINTS
"==============================================================================

OUTPUT	XSeqTRIG,
			XSeqClk1,
			XSeqClk2;

			XSeqTRIG	= SeqD[0] AND SeqCountEn;
			XSeqClk1	= SeqClk;
			XSeqClk2	= /SinkClk;

"==============================================================================
"SPARE I/O
"==============================================================================

INPUT		sgbA[7..0];		 "Spare global	bus A
INPUT		sgbB[7..0];		 "Spare global	bus B
INPUT		sgbC[7..0];		 "Spare global	bus C
INPUT		sgbD[5..0];		 "Spare global	bus D

INPUT		s6_7[7..0];		 "Spare loCAL bus
INPUT		s7_8[7..0];		 "Spare loCAL bus

"==============================================================================	 