"$Id: pld1.src,v 1.25 2001/12/06 17:49:10 warren Exp $
"=============================================================================
#TITLE 'Atlas TIM	C+C, pld1: VME	Interface';
#ENGINEER 'HEP	Electronics';
#COMPANY'University College London';
#COMMENT'A32/A24 VME	interface';

"=============================================================================

"$Log: pld1.src,v $
"Revision 1.25  2001/12/06 17:49:10  warren
"fixed nIRQb=0000001 problem now = 1111111
"
"Revision 1.24  2001/08/30 12:17:07  warren
"signal capitalisation
"
"Revision 1.23  2001/08/08 18:39:56  warren
"signal name upper/lower case standardization only
"
"Revision 1.22  2001/08/03 09:11:32  warren
"layout
"
"Revision 1.21  2001/07/23 11:18:27  warren
"renamed signals with proper polarity n prefixes and removed LOW_TRUEs
"
"Revision 1.20  2001/06/22 13:06:46  warren
"Added ASB signal
"
"Revision 1.19  2001/06/08 18:23:05  warren
"Added  GA_error sig to buserr LED to flag bad GA on FP
"
"Revision 1.18  2001/06/08 09:51:15  warren
"A32/A24 autoselect working, GeogAddr re-implimented
"
"Revision	1.17	2001/06/06 10:06:09	warren
"improved layout	"
"Revision	1.16	2001/06/06 09:23:44	warren
"mainly	layout with	some testing with	the simulation	"

"Revision 1.15	 2001/06/05	10:32:48	 warren
"Added new pins and started work	on	improved	address decode

"Revision 1.14	 2001/06/02	13:10:13	 warren
"Added Baddr_Select code (not	implimented	yet)
"
"Revision 1.13	 2001/04/25	19:01:08	 warren
"commented out	all Irq stuff (still	too new,	and causes too	many problems)
"
"Revision	1.12	2001/04/02 16:06:06	warren
"Added more	Irq stuff -- mainly	the 'read' of stat/id reg
"



"=============================================================================
"
"D16:A24/A32 VME SLAVE interface.
"
" ***USES EXTERNAL VME DATA LATCHES	(74ALS543)***
"
"MODIFIED
"23may00	Stop_Clk, nStop_Clk o/p	and nOA_rst	i/p added.
"06jun00	i/o IackINB, IackOUTB and B added.NC at moment.
"*** NB no defined LOW_TRUE o/ps.****
"
"03jul00	RAMselect o/p added.
"11sep00	GA	implemented	for GAddress 13.
"12sep00	giggling	VME genrated control	lines.
"			reg22	output made	LOW_TRUE	enabled.
"20sep00	ack now generated	from dl3	not dl2.
"02oct00	le1 now uses dl3.(JBL)
"06oct00	Tidied le2 equation.	(Matt)
"02oct00	Only oe databus on read	if	valid	reg address
"			 (added addr_valid	bit) (MRMW)
"06Nov00	Moved	reg 22 (8 bit only on pld)	to	pld5 -
"			 this	used s1_5[7] -	renamed to reg22pld5- MRMW
"15Feb01	reg22	line now	= /reg22pld5 and is a posi-true signal.
"16Feb01	Changed Name and address of ALL sigs etc of Reg	22	--> Reg 32
"			 ANDReg 24 -->	Reg 30.
"			Changed Address decode to hex	fo	full address (added addr lsb)	- MRMW
"			*** pins	sgbD[7..6],	now used	bur reg22, reg24 respectively
"21Feb01	Renamed reg32pld5	(was a sparebus) to reg32.
"			Original	reg32	now CALled nReg32	- it is a negative true	o/p
"20Mar01	Added	'DEFAULT_TO	1'	to	nReg32
"			Added	reg34	line - using s1_5[6]	= Irq	Status/ID register on pld5
"			Added	addr 40h	= TRIG_Irq for	testing Irqs
"02Apr01	Added	code and	bits for	 Irq function - eg. ack_Irq, oeout_Irq
"25Apr01	Commented out Irq	code => current phase of development doesn't	need it
"			 [and	it	is	broken!!]
"01Jun01	Added	BAddr_Select for BoardAddr	= BaseAddr or /GeogAddr	select.
"04Jun01	Re-visited the	address decoder.
"05Jun01	Remove LOW_TRUE output from nStopClk and checked logic
"06Jun01	Implimented	auto address mode	(a32/a24) select based on AMb.
"			Using	(test	phase	only)	the a32_mode to select /GeogAddr	(O=GA,C=dips)
"			In	GA	mode,	the board is only	enabled if in slot 13
"08Jun01 Lights buserr led if GA_mode AND /slot_13 AND /slot_empty
"20Jun01 Added ASB (VME 'Addr Strobe BufFERed')
"20Jul01 Renamed all wrongly labeled low trues
"07Aug01 Removed unused A32_mode signal (pin is now used by BADDR_SELECT.
"06Nov01 Fixed DEFAULT_TO on nIRQb = 1111111b


"=============================================================================
" GLOBAL	SIGNAL DECLARATIONS
"=============================================================================

INPUT		nOA_rst;
NODE		OA_rst;
			OA_rst =	/nOA_rst;


NODE		addr_valid;			"1	= real	register	(or ram)	is	addressed,
									"0	= do not	latch	db	on	read


"=============================================================================
"GLOBAL VME	I/O SIGNALS
"=============================================================================


INPUT		nBErrb;					"BufFERed VME Bus	ERRor.

INPUT		nDS0b,					"BufFERed VME Data Strobes.
			nDS1b;		


NODE		ds;						" - "OR'ed"	ds0/1b. Data Strobes
			ds	= /nDS0b OR /nDS1b;	
			
OUTPUT	dl0;						"OR'ed" ds0/1b, Data	Strobe, to delay line.
			dl0 =	ds;

INPUT		nASb;						"BufFERed VME Addr Strobe

INPUT		nIackb;					"BufFERed VME Interupt ACKnowledge.


INPUT		dl1;						"delayed	Data Strobe.
INPUT		dl2;						"delayed	Data Strobe.
INPUT		dl3;						"delayed	Data Strobe	NOT USED.



INPUT		ab[31..1];				"BufFERed VME Address bus.

NODE		a[15..0]					"ab[15..0]
				CLOCKED_BY dl1
				RESET_BY	/ds;
			a[0] = 0;				"Helps with	address decode	legi.

			a[15..1].D = ab[15..1];	"Latched	low	address signals.



"-----------------------------------------------------------------------------
"GEOGRAPHICAL ADDRESSING
"------------------------

"we will	invert their sense and compare them	to	the address	bus as follows:
"
"						"->" means "gets compared with"
"A(31) -> 0
"A(30) -> 0
"A(29) -> 0
"A(28) -> NOT[GA(4)]
"A(27) -> NOT[GA(3)]
"A(26) -> NOT[GA(2)]
"A(25) -> NOT[GA(1)]
"A(24) -> NOT[GA(0)]


INPUT		nGAb[4..0];		"Geog. address (for slot specific addressing)

INPUT		nGAbp;

INPUT		BaseAddr_Select; " *** was A32_mode: new use: 
							  "BoardAddres	= BaseAddr(switches)	or	/GeogAddr select

INPUT		B_select;  "*** spare  - unused

NODE		GA; "***	true if geog address	avail	and enabled
				 "		 but outputs are still disabled if not	slot 13;

			GA	= BaseAddr_Select;


OUTPUT	nGAoutEn;
NODE		GA_slot13;
NODE		GA_error;


			IF	([/nGAb[4..0],/nGAbp] = 011010b) THEN  "Correct GA is slot 13:01101b
				GA_slot13 =	1;
			ELSE
				GA_slot13 =	0;
			END IF;


			IF	([/nGAb[4..0],/nGAbp]	= 0) THEN
				GA_error	= 0;
			ELSE
				GA_error	= /GA_slot13;
			END IF;

			nGAoutEn	= /GA_slot13;


"=============================================================================
"VME ADDRESS DECODER
"=============================================================================


INPUT		base_addr[31..16];	"base	address from DIP switch	(16bit address).

INPUT		amb[5..0];				"BufFERed VME Address Modifier.

INPUT		nlwordb;			"BufFERed VME signal.


NODE		am_OK						"Correct	Address Modifier for	board	access.
				CLOCKED_BY dl1
				RESET_BY	/ds;		"Falling	edge of ds (cycle	finished).

NODE		addr_OK					"VME address =	base address.
				CLOCKED_BY dl1
				RESET_BY	/ds
				DEFAULT_TO 0;

NODE		A32, A24;				"*** new	- for	legibility mainly


			"-------------------------------------------------------------------
			"Address	modifier	decode

			IF	(nIackb AND	nLWordb)	THEN
				CASE amb[5..0]
					WHEN 3Dh	=>	A24 =	1;	"SSDA:Standard	supervisory	data access
					WHEN 39h	=>	A24 =	1;	"SNDA:Standard	non-privileged	data access
					WHEN 0Dh	=>	A32 =	1;	"ESDA:Extended	supervisory	data access
					WHEN 09h	=>	A32 =	1;	"ENDA:Extended	non-privileged	data access
					ELSE
						A32=0;
						A24=0;
				END CASE;
			END IF;

			am_OK.D = A24 OR A32;



NODE		Board_Addr[31..16];	"*** added for	legi.

			IF	(A32)	THEN					"----------	A32 ------------------
				IF	(GA) THEN
					Board_Addr[31..16] =	0D00h;	"slot	13
				ELSE
					Board_Addr[31..16] =	base_addr[31..16];
				END IF;

				IF	(ab[31..16]	= Board_Addr[31..16]) THEN
					addr_OK.D =	1;
				END IF;

			ELSIF	(A24)	THEN				"----------	A24 ------------------
				IF	(GA) THEN
					Board_Addr[23..16] =	0Dh;	"slot	13
				ELSE
					Board_Addr[23..16] =	base_addr[23..16];
				END IF;

				IF	(ab[23..16]	= Board_Addr[23..16]) THEN
					addr_OK.D =	1;
				END IF;
			END IF;


NODE		bdsel;								"BoarD SELect.
			bdsel	= am_OK AND	addr_OK;		"BoarD SELected when	both asserted.



"-----------------------------------------------------------------------------
"Address	Resolution
"-----------------------------------------------------------------------------


OUTPUT	RAMselect				"SRAM	enable.
				DEFAULT_TO 0;


NODE		reg34access; "***	Needed to provide	reg34	activate	sources:	VME &	Irq



" reg32 & reg 34 was	s1_5[7,6] -	Reg32	moved	pld3 to pld5, reg34 new	on	pld5
OUTPUT	reg00, reg02, reg04,	reg06, reg08, reg0A,	reg0C, reg0E,
			reg10, reg12, reg14,	reg16, reg18, reg1A,	reg1C, reg1E,
			reg20, reg22, reg24,	reg26, reg28, reg2A,	reg2C, reg2E,
			reg30, reg32, reg34
				DEFAULT_TO 0;

OUTPUT	nReg32
				DEFAULT_TO 1;		" ***	added	default to 1
			nReg32 =	/reg32;



			IF	bdsel	THEN								"REGISTER ADDRESS	DECODE
				IF	( /a[15]	) THEN					"Sequencer RAM	NOT being addressed.
					CASE a[15..0]
						WHEN 00h	=>	reg00	= 1;		"=======================
						WHEN 02h	=>	reg02	= 1;		"REGISTER ADDRESS	DECODE
						WHEN 04h	=>	reg04	= 1;		"=======================
						WHEN 06h	=>	reg06	= 1;
						WHEN 08h	=>	reg08	= 1;
						WHEN 0Ah	=>	reg0A	= 1;
						WHEN 0Ch	=>	reg0C	= 1;
						WHEN 0Eh	=>	reg0E	= 1;
						WHEN 10h	=>	reg10	= 1;
						WHEN 12h	=>	reg12	= 1;
						WHEN 14h	=>	reg14	= 1;
						WHEN 16h	=>	reg16	= 1;
						WHEN 18h	=>	reg18	= 1;
						WHEN 1Ah	=>	reg1A	= 1;
						WHEN 1Ch	=>	reg1C	= 1;
						WHEN 1Eh	=>	reg1E	= 1;
						WHEN 20h	=>	reg20	= 1;
						WHEN 22h	=>	reg22	= 1;
						WHEN 24h	=>	reg24	= 1;
						WHEN 26h	=>	reg26	= 1;
						WHEN 28h	=>	reg28	= 1;
						WHEN 2Ah	=>	reg2A	= 1;
						WHEN 2Ch	=>	reg2C	= 1;
						WHEN 2Eh	=>	reg2E	= 1;
						WHEN 30h	=>	reg30	= 1;
						WHEN 32h	=>	reg32	= 1;
						WHEN 34h	=>	reg34access	= 1;	"*** new
						"WHEN	40h	=>	TRIG_Irq	= 1;		"*** added for	testing Irq's

					END CASE;

				ELSIF	( a[15] ) THEN			"NEW for	TIM (SRAM enable)
					RAMselect =	1;
				END IF;

			END IF;


			addr_valid =	reg00	OR	reg02	OR	reg04	OR	reg06	OR	reg08	OR	reg0A	OR
								reg0C	OR	reg0E	OR	reg10	OR	reg12	OR	reg14	OR	reg16	OR
								reg18	OR	reg1A	OR	reg1C	OR	reg1E	OR	reg20	OR	reg22	OR
								reg24	OR	reg26	OR	reg28	OR	reg2A	OR	reg2C	OR	reg2E	OR
								reg30	OR	reg32	OR	reg34access	OR	"TRIG_Irq OR ***Irq
								a[15];

								"*** added Reg34access for	Irq's
								"***Irq TRIG_Irq is not	used now

"-----------------------------------------------------------------------------
"VME I/O
"-------


OUTPUT	nOEin,
			nOEout;			"Output Enables for vme	data bus	'543 latches.
			
OUTPUT	nLE1;				" '543 vme data latches	enable (/LEAB = /LEBA)."***
OUTPUT	nLE2;				" PLD	registers clock.	"*** not clear on low_true

OUTPUT	nErrorLED;		"Bus ERRor when board addressed.
OUTPUT	bWrite;			"Write to registers.
OUTPUT	bRead;			"ReaD	to	registers

INPUT		nWriteb;				"BufFERed VME Data Write.

			bWrite	=	/nWriteb;						"goes	HIGH for	WRITE
			bRead		=  nWriteb;							"goes	HIGH for	READ


			nLE1		= /(bdsel AND /dl3);
			nLE2		=	 bdsel AND dl3	AND bwrite;						"low to high clocking
			
			nOEin		= /(bdsel AND bwrite);									"active low
			nOEout		= /(bdsel AND bread AND	dl2 AND addr_valid);	"active low
							"***Irq OR /(oeout_Irq);
			
			nErrorLED	= /((/nberrb AND addr_OK) OR GA_error);			"goes LOW for error
			            "*** added GA_error
			

OUTPUT	Stop_Clk;		"input to PLD2, stop	clocks when	reg08	write	accessed.
OUTPUT	nStop_Clk;		"inverted Stop_Clk. ***	removed LOW_TRUE

			Stop_Clk	=	reg08	AND bwrite;
			nStop_Clk =	/Stop_Clk;


OUTPUT	ack;						"Data	TransFER	ACK (to external OC device).
			ack		 =	(bdsel AND dl3);
						 "***Irq	OR	ack_Irq;			"*** added Irq	generated ack




"------------------------------------------------------------------------------
"INTERRUPT HANDLING
"------------------

			OUTPUT	nIrqb[7..1]
							DEFAULT_TO 1111111b; "*** fixed

"******************************************************************************
comp_off	"***Irq
						nIrqb[7..2]=	111111b;	"all HIGH, ***	except test	bit


			NODE		TRIG_Irq					"added for Irq	testing
							DEFAULT_TO 0;

			NODE		Irq1_ff
							CLOCKED_BY	TRIG_Irq
							RESET_BY		ack;
						Irq1_ff = 1;

						Irqb[1] = Irq1_FF;


			NODE	Irq_level[2..0];
					Irq_level =	1;			"*** This is preset for	testing,	maybe	a reg	later



		IF	a[3..1]=Irq_level[2..0]	THEN
			Irq_level_valid =	Iackinb;	"ensure addrs and	Irqs don't get	mixed	up
		ELSE
			Irq_level_valid =	0;
		END IF;


			NODE	Irq_level_valid;
comp_on
"*****************************************************************************


INPUT		nIackinb;			" This board's	specific	Iack
NODE		Iackinb;
			Iackinb = /nIackinb;

OUTPUT	nIackoutb;					" For	Iack pass-thorough (low	true)
			nIackoutb = nIackinb;
			
"***Irq	Iackoutb	= /(Iackinb	AND	/Irq_level_valid AND	/ds);
						"low true Iack	pass-through unless interrupting

NODE		ack_Irq;
			ack_Irq	=	(nIackoutb AND dl3);


"***Irq
"NODE		oeout_Irq;
"			oeout_Irq =	/(Irq_level_valid	AND dl2);	"goes	low when	active
"			reg34		 =	Irq_level_valid OR reg34access;



"-----------------------------------------------------------------------------
"SPARE I/O
"---------

			INPUT	sgbA[7..0];		"Spare global bus	A
			INPUT	sgbB[7..0];		"Spare global bus	B
			INPUT	sgbC[7..0];		"Spare global bus	C
			INPUT	sgbD[5..0];		"Spare global bus	D ***	removed 6,7	- used for reg	lines

			INPUT	s1_2[7..0];		"Spare loCAL bus
			INPUT	s1_5[5..0];		"Spare loCAL bus
										"s1_5[7]	is	now used	by	reg32
										"s1_5[6]	is	now used	by	reg34


"==============================================================================