"$Id: pld6.src,v 1.16 2001/11/20 16:54:43 warren Exp $
"==============================================================================
#TITLE	 'ATLAS TIM	PLD6:	Backplane Mapping';
#ENGINEER 'Martin	Postranecky	/ Dominic A	Hayes';
#COMPANY	 'University College	London';
#COMMENT	 '';
"==============================================================================
"$Log: pld6.src,v $
"Revision 1.16  2001/11/20 16:54:43  warren
"removed all sgb assignments
"
"Revision 1.15  2001/11/14 20:12:03  warren
"minor layout
"
"Revision 1.14  2001/08/30 12:20:47  warren
"Tidied, Capitalization
"
"Revision 1.13  2001/08/08 18:42:04  warren
"new stm outline
"and signal names case names
"
"Revision 1.12  2001/07/23 11:18:41  warren
"renamed signals with proper polarity n prefixes and removed LOW_TRUEs
"
"Revision 1.11  2001/07/19 10:45:01  warren
"removed unused spare bus lines
"
"Revision 1.10  2001/06/15 17:01:50  warren
"Cleaned up code organisation
"
"Revision	1.9  2001/04/03 15:45:14  warren	"OA_rst stuff
"




"==============================================================================
"MODS
"14jan00	nLEb2 -> /nLEb2.
"23mar00	reg_enttc reg_test --> reg18 reg0E
"			reg0E	split	between pld5 and pld6. entailed db split into dbh and	dbl.
"			wr0E and	rst0E	nodes	created.
"			test_register contains mapped	nTTCout data, not input data.
"10may00	vreset replaced by nOA_rst.
"23MAY00	added	idTRIG, idBCR,	idECR	o/ps
"24may00	new i/p RunMode.
"05jun00	enRodBusy added to register18	and o/p to pld2.
"06jun00	o/p enBCClk	added	in	Reg18.
"05jul00	Reg0E	changed to Reg24 (so	Reg0E	no	longer split).
"			wr0E and	rst0E	changed to 24 versions.
"11jul00	dbh/l	renamed db and	pins refitted to defaults.	 same	for dbh/loe.
"14jul00	nTTCout id &	tt	o/ps clocked as eclID/eclTT (these are	input	to	PLD7)
"11sep00	Regxx, nLEb2, bReadb,	bWriteb now	HIGH_TRUE.
"29Sep00	Reduced the	enttc_reg. = [...] to [...] =	enttc_reg. 
"			 This solved reg	read problem.
"01Nov00	changed order of component	bits in enttc_register (..ECR	then ..BCR)
"29nov00	added	DEFAULT_To 0 to wr24	- MRMW/JBL
"16Feb01	*** renamed	all sigs	for Register 24 TO Register 30"
"16Mar01	Removed LOW_TRUE from nOA_rst, and fixed all	assos. nOA_rst
"16Mar01	Changes ttc_out to low_true, and	moded	implicated code.
"21Mar01	Added	OA_rst (	= /nOA_rst)	and replaced instances of /nOA_rst



"==============================================================================
"							  SIGNAL	DECLARATIONS
"==============================================================================

INPUT		nOA_rst;							"low_true Board reset.
NODE		OA_rst;
			OA_rst =	/nOA_rst;


INPUT		clk6;								"sync	clock	for ecl o/ps.
INPUT		bReadb;							"BufFERed VME read.
INPUT		bWriteb;							"BufFERed VME write.
INPUT		reg30, Reg18;					"Register enable.
INPUT		nLEb2;								"VME register clock.

INPUT		RunMode;
INPUT		SATRIG, SACAL,	SABCR1, SAECR1, SAFER, SASpare;	 "Sync'd	inputs.
INPUT		SABCR2, SAECR2;													"?? inputs.
INPUT		L1Ain, BCRin, ECRin,	CALin, FERin, Sparein;	"TTCrx	inputs.
INPUT		TTin,	IDin;												"Serialised	data inputs.





OUTPUT	idTRIG,							 "
			idBCR,							 "	to	pld4 (same as ecl	version)
			idECR;							 "

"------------------------------------------------------------------------------
" EnTTCRegister			(Reg18)							(VME R/W, MASTER R)
"-----------------

NODE		enttc_register[15..0]
				CLOCKED_BY nLEb2
				RESET_BY	OA_rst
				DEFAULT_TO LAST_VALUE;
				 "CLOCK_ENABLED_BY (bWriteb AND reg18)	"*** -this fails to fit!

NODE		enL1A,
			enBCR,
			enECR,
			enCAL,
			enFER,
			enspare;
	
OUTPUT	enRodBusy,
			enTType,
			enBCID,
			enL1ID,
			enSABCR2,
			enSAECR2,
			/enBCClk;		"Inverted o/p


"------------------------------------------------------------------------------
" TestRegister	  (reg30)									(COUNTER/MASTER W, VME R)
"--------------
"("registered"	using	self clocking circuitry, VME write causes	reset)



"------------------------------------------------------------------------------

BIPUT		db[15..0]					"databus.
				ENABLED_BY dboe;
NODE		dboe;						"db output enable.





"==============================================================================
"SIGNALS
"=======


INPUT		seqTRIG,					"Sequencer inputs.
			seqCAL,
			seqBCR,
			seqECR,
			seqFER,
			seqSpare,
			seqTT,
			seqID;

NODE		L1A,						"or'd	internal	signals.
			BCR,
			ECR,
			CAL,
			FER,
			zSpare,
			TT,
			ID;

			L1A	 =	SATRIG  OR				(L1Ain AND enL1A)	  OR seqTRIG;
			BCR	 =	SABCR1  OR SABCR2	OR	(BCRin AND enBCR)	  OR seqBCR;
			ECR	 =	SAECR1  OR SAECR2	OR	(ECRin AND enECR)	  OR seqECR;
			CAL	 =	SACAL	  OR				(CALin AND enCAL)	  OR seqCAL;
			FER	 =	SAFER	  OR				(FERin AND enFER)	  OR seqFER;
			zSpare =	SASpare OR			 (Sparein AND enSpare) OR seqSpare;
			TT		 =	TTin	  OR											  seqTT;
			ID		 =	IDin	  OR											  seqID;



"-------------------------------------------------------------------------------
"TTC_OUT
"-------


OUTPUT	nTTCout[7..0];			"outputs	to	bufFER FFs.


"### MODIFY THIS TO CHANGE BACKPLANE MAPPING ###

			nTTCout[7] = /zSpare;
			nTTCout[6] = /FER;
			nTTCout[5] = /tt;
			nTTCout[4] = /id;
			nTTCout[3] = /CAL;
			nTTCout[2] = /BCR;
			nTTCout[1] = /ECR;
			nTTCout[0] = /L1A;

"###############################################


"----------------------------------------------------------
" SELF-CLOCKING FOR TEST_REGISTER	(requires reset by VME)
"---------------------------------
"One-time/one-way (0->1) latch with reset
"Created without	F/F to overcome limits on multple clock sources for FF in PLD



NODE		test_register[7..0] ;
NODE		reg_ttcout[7..0];

NODE		rst30;
NODE		wr30
				DEFAULT_TO 0;
					"CLOCKED_BY	nLEb2
					"CLOCK_ENABLED_BY	(bWriteb	AND reg30)
					"RESET_BY OA_rst
					"DEFAULT_TO	0;

			reg_ttcout[7] = rst30 AND (/nTTCout[7] OR reg_ttcout[7]);
			reg_ttcout[6] = rst30 AND (/nTTCout[6] OR reg_ttcout[6]);
			reg_ttcout[5] = rst30 AND (/nTTCout[5] OR reg_ttcout[5]);
			reg_ttcout[4] = rst30 AND (/nTTCout[4] OR reg_ttcout[4]);
			reg_ttcout[3] = rst30 AND (/nTTCout[3] OR reg_ttcout[3]);
			reg_ttcout[2] = rst30 AND (/nTTCout[2] OR reg_ttcout[2]);
			reg_ttcout[1] = rst30 AND (/nTTCout[1] OR reg_ttcout[1]);
			reg_ttcout[0] = rst30 AND (/nTTCout[0] OR reg_ttcout[0]);

			rst30	= /(OA_rst OR wr30);


"----------------------------------------------------------
"Signal OUTPUTS
"-----------------
OUTPUT	eclL1A,					"
			eclBCR,					"
			eclECR,					"outputs	to	ECL bufFERs.
			eclCAL,					"
			eclFER,					"
			eclSpare,				"
			eclID,					"
			eclTT						"
				CLOCKED_BY clk6
				RESET_BY	OA_rst;
				
				

			eclL1A.D	  = L1A;
			eclBCR.D	  = BCR;
			eclECR.D	  = ECR;
			eclCAL.D	  = CAL;
			eclFER.D	  = FER;
			eclSpare.D = zspare;
			eclID.D	  = id;		  "addition
			eclTT.D	  = tt;		  "addition
			
			
			idTRIG =	 eclL1A;
			idBCR	 =	 eclBCR;
			idECR	 =	 eclECR;



"----------------------------------------------------------
"ASSEMBLINMG REGISTERS FOR OUTPUT
"--------------------------------

			"reg30
			"-----

			test_register[7..0] = reg_ttcout[7..0];	
			


			"Reg18 (enttc_register)
			"-----

			[	
			enSABCR2,	"15
			enSAECR2,	"14
	
			enTType,		"10
			enBCID,		" 9
			enL1ID,		" 8
			enRodBusy,	" 7
			enspare,		" 6
			enFER,		" 5
			enCAL,		" 4
			enBCR,		" 3
			enECR,		" 2
			enL1A,		" 1
			enBCClk		" 0
			] = [	enttc_register[15..14],	enttc_register[10..0] ];



"==============================================================================
"VME I/O
"=======

			IF	(bReadb)	THEN
				IF	(reg30) THEN
					db[15..8] =	0;	"*** for TESTING: remove if pld space is limited
					db[7..0]	 =	test_register;	 "VME	READs	test_register.
			
				ELSIF	(Reg18) THEN
					db	= enttc_register;
				END IF;
			
			ELSIF	(bWriteb) THEN
			
				IF	(Reg18) THEN
					enttc_register	= db;
			
				ELSIF	(reg30) THEN
					wr30 = 1;
				END IF;
			END IF;
			
			
			dboe = bReadb AND	(reg30 OR Reg18);			  "databus output	enable.






"==============================================================================
"SPARE I/O
"=========
 

"*** testing ECR sources
"OUTPUT	sgbB[7..0];		"Spare global bus	B

"			sgbB[7] = SAECR1;
"			sgbB[6] = SAECR2;
"			sgbB[5] = ECRin;
"			sgbB[4] = enECR;
"			sgbB[3] = seqECR;
"			sgbB[2] = ECR;
"			sgbB[1] = eclECR;
"			sgbB[0] = idECR;


INPUT		sgbA[7..0];		"Spare global bus	A
INPUT		sgbB[7..0];		"Spare global bus	B
INPUT		s2_6[7..0];		"Spare loCAL bus
INPUT		s5_6[7..0];		"Spare loCAL bus
INPUT		s6_7[7..0];		"Spare loCAL bus



"==============================================================================
