"$Id: pld2.src,v 1.37 2002/05/22 11:34:25 warren Exp $
"==============================================================================
#TITLE    'SCT TIM PLD2: Stand-Alone Signal Gen/Timing';
#ENGINEER 'Martin Postranecky / Dominic A Hayes / Matthew Warren';
#COMPANY  'University College London';
#COMMENT  '  ';


"==============================================================================
"$Log: pld2.src,v $
"Revision 1.37  2002/05/22 11:34:25  warren
"changed pins for CT, changed clocks polarity for enSACLK, Added TTCready
"redirect to pld6
"
"Revision 1.36  2002/03/22 17:40:10  warren
"new reg clocking, excl reg02
"
"Revision 1.35  2002/02/11 18:33:17  warren
"Added clock sync - req'd new sparebus signals and new sigs too
"
"Revision 1.34  2002/01/16 16:50:59  warren
"tidied up tabs
"
"Revision 1.33  2002/01/15 10:29:55  warren
"bugfix: added /disableTRIG to swTRIG enable
"
"Revision 1.32  2001/11/28 14:11:55  warren
"Added not repCAL mode when enExtCAL
"
"Revision 1.31  2001/11/27 16:46:21  warren
"code debug to working condition
"FF added to input of pipeline to fix double width triggers
"Sync fixed to stop oscillations ....
"
"Revision 1.30  2001/11/20 16:54:21  warren
"fixed latch-up on internal signals, stand-alone mode looks good(!)
"
"Revision 1.29  2001/11/14 20:10:51  warren
"improved rantrig, testbusy, timing, trigrig_win. Issues with latch-up
"
"Revision 1.28  2001/10/05 11:34:07  warren
"Rework of delayed TRIG hierachy/logic
"Rework of input logic/sync (no more pulsars)
"Added clocking to output signals
"
"Revision 1.27  2001/10/02 12:29:11  warren
"no change -- just getting dates good in CVS
"
"Revision 1.26  2001/09/11 16:28:06  warren
"removed new changes -- so no change should show
"
"Revision 1.25  2001/09/06 10:38:59  warren
"Reworked all code, with new busy system and CAL state-machine
"Seen to send cals with proper trig, and cal bursts
"
"Revision 1.24  2001/08/30 12:18:44  warren
"combined some combined some FER/ECR code
"tidied, rename, updated
"
"Revision 1.23  2001/08/08 18:40:20  warren
"signal name upper/lower case standardization
"
"Revision 1.22  2001/08/03 09:12:25  warren
"finalised inverting signals, and ensured worked as before
"improved stm
"
"Revision 1.21  2001/08/02 14:53:33  warren
"improved a liiiiiiittle
"
"Revision 1.20  2001/08/02 14:42:51  warren
"don't want to loose it
"
"Revision 1.19  2001/07/27 17:40:33  warren
"better layout
"
"Revision 1.18  2001/07/24 10:04:04  warren
"new simulation
"
"Revision 1.17  2001/07/23 11:18:30  warren
"renamed signals with proper polarity n prefixes and removed LOW_TRUEs
"
"Revision 1.16  2001/07/19 10:44:13  warren
"removed unused spare bus lines
"
"Revision 1.15  2001/07/16 13:13:31  warren
"*** empty log message ***
"
"Revision   1.14  2001/06/05 10:33:23  warren
"Added pulser  the test_sw input (fp TRIG)
"  "Revision 1.13  2001/04/25 19:01:53  warren
"removed the   testpin outputs - not needed and may be messing up clocks
"
"Revision 1.12  2001/04/03 15:43:19  warren
"Changed from nOA_rst to OA_rst
"


"==============================================================================
"Receives:
"          BC_RESET   FE_RESET    TRIGGER  CALIBRATE   ECR   SPARE
"Modified:
"---------
"29mar00 enc_TRIG output added (= SATRIG).
"31mar00 regs 00, 02, 0A added.
"04apr00 29mar00 mod removed.
"05apr00 vina..f replaced with actual name, eg vBCR/v_BCR.
"        same for extIn_a..f and intIn_a..f (internal pulsed versions)
"22may00 DelaySelect[7..0] removed  from .pi file.
"24may00 enintSpare, intInSpare, intSpare removed.
"        name: RodBusy -> rod_crate_BusyOut, SetToRunMode -> RunMode, SAClkDelay
"        -> CT.
"05jun00 entestbusy, clrtestbusy added to register 02 voaReset moved.
"06jun00 OA_reset removed.
"        testbusyON circuit added.
"07jun00 EclExt_Clk split int 1 & 2.
"        extbusy split into Nim and Ecl flavours.
"        int_clk split into 2.  int_clk1 feeding clock circuit int_clk2 feeding
"        count in busy2.
"           (fiTTing problem with PT clk and CE) int_clk i/p to both pins.
"08jun00 clk3 -> clk2b.
"03jul00 StartSink, StartSeq o/ps added.
"        Reg00 reordered.
"05jul00 enTRIGWin -> enWindow, enIntRptTRIG -> enIntTRIG, enIntRan -> enRandom
"        enWindow made an o/p.
"        new reg02 bit and o/p vRodBusy.
"11jul00 OA_reset reinstated.
"26sep00 nOA_rst INPUT now LOW_TRUE.  Ooops!
"04oct00 Added CLK_EN_BY (and tidied write logic) for reg 00,02,0A - MRMW
"02Nov00 Fixed up nOA_rst discrepencies on registers
"03Nov00 Changed Register 00 bit 0 to be 1 on reset - this involved spliTTing
"           the reg. MRMW
"27Dec00 in FUNC pulser chnged   'reset' to 'nOA_rst_' for legabilty.
"        Changed naming in Shift144 func to match their non-local signals (
"        Fixed probable inversion of nOA_rst issues in:
"           -rst_pulse (in FUNC pulser)
"           -q1 in SYNC TRIG
"           -srclr
"28Dec00 Added nodes ext_BCR, int_BCR that incorp. Enables and Nim/ECR combining
"         for much more ledgible code.
"05Jan01 Removed lev2pulse from voaReset - not needed?
"08jan01 added test lines to sgbA for MP
"02Feb01 Sorted out sreset (was wrong TRUE) MP, MRMW
"        nOA_rst input is TRUE and the signal is negative going logic on the pld
"        - MP, MRMW
"12Feb01 Reset (rst_pulse) in pulser: Added  ...   AND /RunMode ... for
"        extra delay MP, MRMW
"        changed TestBusyONreset func to OR /EnTestBusy -  this should provide
"        proper enable  MP, MRMW
"14Feb01 In q_SATRIG func changed NOTed the Disable_TRIG sig.
"15Feb01 Added code for better simulation of pulser   converter:
"        sim_level_2_pulse MRMW
"21Mar01 Cleaned up nOA_rst legibity (added OA_rst = /nOA_rst)
"24Apr01 Removed all test points and associated code for watch vTRIG etc.
"04Jun01 Added pulser to test_sw, creating sw_TRIG.
"23Jul01 Renamed q1 to qStop_Clk
"        Renamed q0 to qenDeadTimerCAL
"03Aug01 Removed Stop_Clk and related logic.
"16Aug01 Added enIntFER = enIntFERx or enIntECR to enable osc in both cases
"         The bit in the enables reg is now enIntFERx.
"28Aug01 Total rework and simplification of signals -- no enSig,enDeadTimer etc
"04Sep01 CAL state-machine added -- CALTRIG and and Bursts are run using this
"14Sep01 Reworked hierachy system to not affect undelayed TRIGs
"        This also implied that TRIG inputs would not be gated by the OA_busy
"         and TRIG imputs would not gate other input signals
"02Oct01 Signals are all clocked prior to leaving the PLD, at the output pin.
"03OCt01 Rework of signal flow and sync. All ext, vme, and async sigs now clock
"         FFs that are reset by the OR of all SYNCed signals. This allows a 2 FF
"         SYNC. TRIGS are not grouped with the other sigs, but work the same way.
"05Oct01 Added TRIG pipeline flushing if delay register is written to!
"16Nov01 i/p sig FF now hold level as a busy until a syncSIG issued.
"         the sync clock a FF to setup busy
"        other FFs not in the sig group are async disabled on signal reception.
"         danger here is that 2 sigs at exactly the same time will kill BOTH
"26Nov01 Created disableTRIG as (Disable_TRIG OR writeReg0A) that resets all
"         TRIG and CAL signals and funcs for bursts/delay changes
"27Nov01 Added busyCAL to busyTRIG eqn.
"        Added clocking to input of shiftreg to solve double width trig problem
"14Jan02 Added /disableTrig to vTRIG and swTRIG enables
"16Jan02 Removed busyTRIG2 -- not used
"29Jan02 Tidied more sig defs (aminly busy, clocks) to be nearer logic.
"        Tried changing the resets for the sr to be just OA_rst 
"         = no significant change in inter-seg utilisation
"01Feb02 Add clock change syncing - used lots of spare bus pins
"08Feb02 Modded busys to match docs
"26Feb02 Fixed clock-changer with extra FF. it seems to work
"27Feb02 Changed to new register clocking scheme
"20Feb02 Removed above clocking scheme from reg02 to allow vResets or unsetting 
"         SAMode bit (useful on older TIMs (0/1))
"17May02 Added TTC_ready redirect to pld2 via spare bus
"        Changed reset counter to only reset if it has a clock
"22May02 Re-ordeed CT pins in pi file to match delay-unit pins
"        Changed clocking on SA-clock-select FF to positive

"-------------------------------------------------------------------------------
"PROCEDURE shift144
"-------------------------------------------------------------------------------
"operates as a 128 + 16 shift register with selectable output.


PROCEDURE   shift144 (
               INPUT    outTRIG_,      "serial data from sync'd TRIGger.
                        DelaySelect_[7..0],  "8bit selection from TRIG delay register.
                        clk_,       "clock from delay line 3.
                        srclr_,     "used to clear the shift register during reg writes etc..
                        OA_rst_;

               OUTPUT   DTRIGh_,
                        DTRIG_   );



   NODE     serial_in; " added only for legibility,   reduces to zilch
            serial_in = outTRIG_;

   NODE     sr_rst;
            sr_rst = OA_rst_ OR srclr_;

"   NODE     clr[127..0],
"            c;
"            c = srclr_;

"            clr = [
"            c,c,c,c,c,c,c,c, c,c,c,c,c,c,c,c, c,c,c,c,c,c,c,c, c,c,c,c,c,c,c,c,
"            c,c,c,c,c,c,c,c, c,c,c,c,c,c,c,c, c,c,c,c,c,c,c,c, c,c,c,c,c,c,c,c,
"            c,c,c,c,c,c,c,c, c,c,c,c,c,c,c,c, c,c,c,c,c,c,c,c, c,c,c,c,c,c,c,c,
"            c,c,c,c,c,c,c,c, c,c,c,c,c,c,c,c, c,c,c,c,c,c,c,c, c,c,c,c,c,c,c,c
"            ];


   NODE     shift_a[127..0],
            shift_b[15..0]
               CLOCKED_BY clk_
               RESET_BY   sr_rst;

   NODE     qserial_in
               CLOCKED_BY clk_
               RESET_BY   sr_rst;

            qserial_in = serial_in;

            shift_a[127..0] = [shift_a[126..0],qserial_in];


   NODE     selected_bit_a,
            selected_bit_b
               DEFAULT_TO 0;

   CASE DelaySelect_[7..4]
      WHEN 0 => selected_bit_a = qserial_in;
      WHEN 1 => selected_bit_a = shift_a[15];
      WHEN 2 => selected_bit_a = shift_a[31];
      WHEN 3 => selected_bit_a = shift_a[47];
      WHEN 4 => selected_bit_a = shift_a[63];
      WHEN 5 => selected_bit_a = shift_a[79];
      WHEN 6 => selected_bit_a = shift_a[95];
      WHEN 7 => selected_bit_a = shift_a[111];
      WHEN 8 => selected_bit_a = shift_a[127];
   END CASE;

   shift_b = [shift_b[14..0], selected_bit_a];


   CASE DelaySelect_[3..0]
      WHEN  0 => selected_bit_b = selected_bit_a;
      WHEN  1 => selected_bit_b = shift_b[0];
      WHEN  2 => selected_bit_b = shift_b[1];
      WHEN  3 => selected_bit_b = shift_b[2];
      WHEN  4 => selected_bit_b = shift_b[3];
      WHEN  5 => selected_bit_b = shift_b[4];
      WHEN  6 => selected_bit_b = shift_b[5];
      WHEN  7 => selected_bit_b = shift_b[6];
      WHEN  8 => selected_bit_b = shift_b[7];
      WHEN  9 => selected_bit_b = shift_b[8];
      WHEN 10 => selected_bit_b = shift_b[9];
      WHEN 11 => selected_bit_b = shift_b[10];
      WHEN 12 => selected_bit_b = shift_b[11];
      WHEN 13 => selected_bit_b = shift_b[12];
      WHEN 14 => selected_bit_b = shift_b[13];
      WHEN 15 => selected_bit_b = shift_b[14];
   END CASE;

   DTRIGh_ = selected_bit_a;
   DTRIG_  = selected_bit_b;

END shift144;



"-----------------------------------------------------------------------
" FUNCTION PulseTrap
"-----------------------------------------------------------------------
"Take async signal and holds it until reset


FUNCTION PulseTrap   ( INPUT signal, enable, rst);

      NODE  q1
               CLOCKED_BY signal
               RESET_BY rst;
            q1 = enable;

   RETURN   q1;

END PulseTrap;



"------------------------------------------------------------------------------
"FUNCTION SYNC
"------------------------------------------------------------------------------
"Uses a set of 3 flip-flops used to synchronise the input clock signals
"------------------------------------------------------------------------------

FUNCTION SYNC  ( INPUT signal, clk, clr, rst);

   NODE     q0
               CLOCKED_BY signal
               RESET_BY clr OR q2;
            q0 = 1;

   NODE     q1
               CLOCKED_BY clk
               RESET_BY clr;

   NODE     q2
               CLOCKED_BY clk
               RESET_BY rst;


            q1     = q0;
            q2     = q1 AND q0;

   RETURN   q2;

END SYNC;



"===============================================================================
"
"
"  M A I N    B O D Y
"
"
"===============================================================================

INPUT    nOA_rst;                   "Low_True Board reset.
NODE     OA_rst;
         OA_rst = /nOA_rst;

NODE     OA_busy;
OUTPUT   nOA_busy;
         nOA_busy = /OA_busy;

INPUT    Burst_Ready,      "from PLD3, was Burst_Busy
         enCALBurst,       "enCount from PLD3
         Disable_TRIG;


OUTPUT   enWindow;

"===============================================================================
"
" RESETS
"
"===============================================================================
""Uses   counter to ensure OA_reset is 8x25ns duration

INPUT    sReset;
NODE     vOAreset;   "reg02

NODE     OA_reset_set;
         OA_reset_set = sReset OR vOAreset;

NODE     reset_count8
            DEFAULT_TO 1;

NODE     qReset              
            CLOCKED_BY  OA_reset_set
            RESET_BY    reset_count8;
         qReset = 1;

OUTPUT   OA_reset,   "resets to other plds etc
         nOA_reset;
         
         nOA_reset = /OA_reset;

NODE     reset_timer[4]
            CLOCKED_BY int_clk2
            CLOCK_ENABLED_BY qReset
            RESET_BY reset_count8;

         reset_timer = reset_timer .+. 1;


         IF ( reset_timer = 0) THEN            "set counter roll-over value
            OA_reset = 0;
            reset_count8 = 0;
            
         ELSIF ( reset_timer = 9 ) THEN
            OA_reset = 0;
            reset_count8 = 1;
            
         ELSE
            OA_reset = 1;
            reset_count8 = 0;
            
         END IF;
            
        

INPUT    clk2, clk2b;



"===============================================================================
"
" REGISTERS and VME Access
"
"===============================================================================


"-------------------------------------------------------------------------------
" VME control signals
"-------------------------------------------------------------------------------


INPUT    bWriteb,
         bReadb,
         Reg00,
         Reg02,
         Reg0A,
         nLEb2;

BIPUT    db[15..0]
            ENABLED_BY dboe;
NODE     dboe;


"-------------------------
" Register 00 - Enables
"-------------------------

NODE     Register00[15..0]
            CLOCKED_BY clk2b
            CLOCK_ENABLED_BY (Reg00 AND /nLEb2)
            RESET_BY OA_rst;

         Register00[15..0] = db[15..0];  "VME WRITES to Registers.


"-------------------------
" Register 02 - Commands
"-------------------------

"NODE     RegisterCommand[15..0]
"            CLOCKED_BY clk2b
"            CLOCK_ENABLED_BY (Reg02 AND /nLEb2)
"            RESET_BY OA_rst;
            
NODE     RegisterCommand[15..0]  "*** using older scheme to set SAmode on older TIMs
            CLOCKED_BY nLEb2
            CLOCK_ENABLED_BY (bWriteb AND Reg02)
            RESET_BY OA_rst;

         RegisterCommand[15..0]  = db[15..0];


OUTPUT   vBurstGo, vBurstMode, vRodBusy;

         vRodBusy   = RegisterCommand[8];
         vBurstMode = RegisterCommand[9];
         vBurstGo   = RegisterCommand[10];


"-------------------------
" Register 0A - Delays
"-------------------------

NODE     RegisterDelay[15..0]
            CLOCKED_BY clk2b
            CLOCK_ENABLED_BY (Reg0A AND /nLEb2)
            RESET_BY OA_rst;

         RegisterDelay = db;


OUTPUT   CT[5..0];
         CT[5..0] = RegisterDelay[13..8]; "*** note these have been re-ordered in 
                                          "the .pi file to match 'incorrectly' numbered sch.

NODE     DelaySelect[7..0];
         DelaySelect[7..0] = RegisterDelay[7..0];



"-------------------------------------------------------------------------------
" Register Reads logic (write is controled by clock_enables)
"-------------------------------------------------------------------------------

         IF (bReadb) THEN

            IF (Reg00) THEN
               db[15..0] = Register00[15..0];

            ELSIF (Reg02) THEN
               db = RegisterCommand[15..0];

            ELSIF (Reg0A) THEN
               db = RegisterDelay[15..0];

            END IF;

         END IF;

         dboe = bReadb AND (Reg00 OR Reg02 OR Reg0A);



"-------------------------------------------------------------------------------
"TESTBUSYON
"----------

NODE     EnTestBusy, ClrTestBusy;

         [  EnTestBusy,       "EnTestBUSY
            ClrTestBusy,      "ClrTestBUSY
            vOAReset          "voaRESET
         ] =  RegisterCommand[13..15];


OUTPUT   TestBusyON
            CLOCKED_BY syncDTRIG
            RESET_BY TestBusyONreset;
         TestBusyON = 1;

NODE     TestBusyONreset;
         TestBusyONreset  = ClrTestBusy OR /EnTestBusy OR OA_rst;


"==============================================================================
"
" CLOCKS and RUN/SA MODES
"
"==============================================================================

OUTPUT   RunMode, SAMode;
         RunMode = RegisterCommand[12];      "setRunMode
         SAMode  = /RunMode;


"=============================================================================
" STAND-ALONE CLOCKS
"=============================================================================


INPUT    int_clk1, "On BIPUT pin
         int_clk2; "On CLOCK1 pin



"----------------------------
"STAND ALONE clock selection
"----------------------------

INPUT    NimExt_Clk,
         EclExt_Clk1,
         EclExt_Clk2;

NODE     intClk,
         extClk;

         intClk = int_clk1;
         extClk = (NimExt_Clk OR EclExt_Clk1 OR EclExt_Clk2);
         
INPUT    SAClkON_out;    "from pld3
NODE     SAClk;
                  
NODE     enExtClk;           
         enExtClk  = Register00[8];
               

NODE     qenIntClk
            CLOCKED_BY /intClk
            PRESET_BY  OA_rst;

NODE     enExtClk2,
         qenExtClk
            CLOCKED_BY /extClk
            RESET_BY   /SAClkON_out OR OA_rst;
                     
         enExtClk2  =  enExtClk;
         qenIntClk  = /enExtClk2;
         qenExtClk  = /qenIntClk AND enExtClk2;

         SAClk = (intClk AND qenIntClk) OR (extClk AND qenExtClk);
         

OUTPUT   clkIn;         "SA CLOCK output to board
         clkIn = SAClk;


         
"--------------------------------
"MAIN clock selection and control
"--------------------------------

INPUT    TTCClkIn,
         TTC_Ready_in,  "from pld9  sgbD
         TTCClkON_out,  "from pld3  s2_3
         enTTCClk;      "from pld6  s2_6
         
OUTPUT   TTC_ready2_6;   "forward on the pld6 (has no sgbD) "was s2_6[5]; 

NODE     TTCClkON2,
         enTTCClk2;
        
NODE     qenSAClk
            CLOCKED_BY SAClk     "*** removed / to remove glitch cause by delay unit problem
            PRESET_BY  OA_rst;

NODE     qenTTCClk
            CLOCKED_BY /TTCClkIn
            RESET_BY   /TTCClkON2 OR OA_rst;


         TTCClkON2 = TTC_Ready_in AND TTCClkON_out;
			enTTCClk2 = enTTCClk AND TTCClkON2; 
			
         qenSAClk  = /qenTTCClk AND /enTTCClk2;
         qenTTCClk = /qenSAClk  AND  enTTCClk2;
         



OUTPUT   nSA_CLK_MODE,
         nTTC_CLK_MODE; 
         
         nSA_CLK_Mode  = /qenSAClk;
         nTTC_CLK_MODE = /qenTTCClk;
         
VIRTUAL  
NODE     Clk_TTCtest; "for sim waveforms only -- will reduce away at fit.
         Clk_TTCtest = (TTCClkIN AND qenTTCClk) OR (SAclk AND qenSAClk);
        


"TIM-OK generation
"-----------------

NODE     SAClk_OK,
         TTCClk_OK;
         
         SAClk_OK  =    (qenExtClk   AND  enExtClk) 
                     OR (SAClkON_out AND /enExtClk);
                     
         TTCClk_OK = (qenTTCClk AND enTTCClk);


OUTPUT   TIM_OK_out;    "was sgbD[0]
         TIM_OK_out =    (TTCClk_OK AND  enTTCClk) 
                      OR (SAClk_OK  AND /enTTCClk);



"==============================================================================
"
"SIGNALS
"
"==============================================================================

NODE     disableTRIG;   "new async pulse to ensure things work after a delay reg write
         disableTRIG = Disable_TRIG OR (Reg0A AND bwriteb) OR OA_rst;


NODE     doneDTRIG,
         doneTRIG,
         doneBCR,
         doneCALP,
         doneECR,
         doneFER,
         doneSpare;

NODE     doneCAL           "Generated in state machine
            DEFAULT_TO 0;

NODE     doneANY;

NODE     busyANY;

NODE     syncTRIG, syncCAL, syncBCR, syncFER, syncECR, syncSpare;
NODE     syncCALP;

NODE     syncDTRIG
            CLOCKED_BY clk2b
            RESET_BY OA_rst;


"BUSYs
"-----

NODE     clrDTRIG, clrCAL, clrCALP, clrBCR, clrECR, clrFER, clrSpare;

NODE     busyTRIG, busyCAL, busyCALP, busyBCR, busyECR, busyFER, busySpare;
NODE     busyDTRIG;
NODE     busyRTRIG;  "busy for Real Trig (as opposed to a Cal-Trig


         busyTRIG  = syncTRIG OR busyCAL OR disableTRIG OR OA_rst; "allows trigs to be stacked-up
         busyDTRIG = PulseTrap(syncDTRIG, 1, clrDTRIG) OR TestBusyON;
         busyCAL   = PulseTrap(syncCAL,   1, clrCAL);
         busyCALP  = PulseTrap(syncCALP,  1, clrCALP);
         busyBCR   = PulseTrap(syncBCR,   1, clrBCR);
         busyECR   = PulseTrap(syncECR,   1, clrECR);
         busyFER   = PulseTrap(syncFER,   1, clrFER);
         busySpare = PulseTrap(syncSpare, 1, clrSpare);

         busyRTRIG = busyDTRIG AND (/busyCAL OR busyCALP); "busy Real TRIG ie. not CAL_TRIG

         busyANY =    busyDTRIG
                   OR busyCAL
                   OR busyBCR
                   OR busyECR
                   OR busyFER
                   OR busySpare
                   OR disableTRIG
                   OR OA_rst;


"Over-All busy
"-------------
"generated with input latches for faster feedback

NODE     asyncTRIG, asyncCAL, asyncBCR, asyncECR, asyncFER, asyncSpare;

         OA_busy =   asyncTRIG
                  OR asyncCAL
                  OR asyncBCR
                  OR asyncECR
                  OR asyncFER
                  OR asyncSpare
                  OR busyANY     "sync sig BUSY
                  OR busyDTRIG
                  OR disableTRIG
                  OR OA_rst;



"TEST SWITCH
"----------------------------------

INPUT    test_sw;    "FP TRIG push-button
NODE     sw_TRIG;
         sw_TRIG = PulseTrap(test_sw, /disableTRIG, busyTRIG);



"VME SOURCES (no enables)
"------------------------
NODE     vTRIG, vCAL, vBCR, vECR, vFER, vSpare;

         [ vTRIG, vECR, vBCR, vCAL, vFER, vSpare ] = RegisterCommand[1..6];


NODE     v_TRIG, v_CAL, v_BCR, v_ECR, v_FER, v_Spare;

         v_TRIG   = PulseTrap(vTRIG,  1, busyTRIG);
         v_CAL    = PulseTrap(vCAL,   1, busyANY);
         v_BCR    = PulseTrap(vBCR,   1, busyANY);
         v_ECR    = PulseTrap(vECR,   1, busyANY);
         v_FER    = PulseTrap(vFER,   1, busyANY);
         v_Spare  = PulseTrap(vSpare, 1, busyANY);



"EXTERNAL SOURCES (enabled by pair)
"----------------------------------

INPUT    extInBCRNim, extInFERNim, extInTRIGNim, extInCALNim, extInECRNim, extInSpareNim;
INPUT    extInBCREcl, extInFEREcl, extInTRIGEcl, extInCALEcl, extInECREcl, extInSpareEcl;
NODE     ext_TRIG,  ext_CAL,  ext_BCR,  ext_ECR,  ext_FER,  ext_Spare,
         enExtTRIG, enExtCAL, enExtBCR, enExtECR, enExtFER, enExtSpare;


NODE     extTRIGNim, extCALNim, extBCRNim, extECRNim, extFERNim, extSpareNim;

         extTRIGNim  = PulseTrap(extInTRIGNim,  enExtTrig,  busyTRIG);
         extCALNim   = PulseTrap(extInCALNim,   enExtCAL,   busyANY);
         extBCRNim   = PulseTrap(extInBCRNim,   enExtBCR,   busyANY);
         extECRNim   = PulseTrap(extInECRNim,   enExtECR,   busyANY);
         extFERNim   = PulseTrap(extInFERNim,   enExtFER,   busyANY);
         extSpareNim = PulseTrap(extInSpareNim, enExtSpare, busyANY);


NODE     extTRIGEcl, extCALEcl, extBCREcl, extECREcl, extFEREcl, extSpareEcl;

         extTRIGEcl  = PulseTrap(extInTRIGEcl,  enExtTrig,  busyTRIG);
         extCALEcl   = PulseTrap(extInCALEcl,   enExtCAL,   busyANY);
         extBCREcl   = PulseTrap(extInBCREcl,   enExtBCR,   busyANY);
         extECREcl   = PulseTrap(extInECREcl,   enExtECR,   busyANY);
         extFEREcl   = PulseTrap(extInFEREcl,   enExtFER,   busyANY);
         extSpareEcl = PulseTrap(extInSpareEcl, enExtSpare, busyANY);

         enWindow  = Register00[6];

INPUT    TRIG_win;
NODE     TRIG_win_open;
         TRIG_win_open = (TRIG_win AND enWindow) OR /enWindow;


         enExtTRIG   = Register00[9] AND TRIG_win_open;
         enExtECR    = Register00[10];
         enExtBCR    = Register00[11];
         enExtCAL    = Register00[12];
         enExtFER    = Register00[13];
         enExtSpare  = Register00[14];

         ext_TRIG    = (extTRIGNim  OR extTRIGEcl);
         ext_CAL     = (extCALNim   OR extCALEcl);
         ext_BCR     = (extBCRNim   OR extBCREcl);
         ext_FER     = (extFERNim   OR extFEREcl);
         ext_ECR     = (extECRNim   OR extECREcl);
         ext_Spare   = (extSpareNim OR extSpareEcl);


"ONBOARD SOURCES (each has enable)
"---------------------------------

INPUT    intInTRIG, intInRan, intInBCR, intInECR, intInFER;
NODE     enIntBCR, enIntECR, enIntFERx;   "new x for combined with ECR sig
OUTPUT   enIntFER, enIntTRIG,  enRandom;
NODE     enIntTRIG2, enRandom2;

OUTPUT   intTRIG;
         intTRIG = intInTRIG;

NODE     intTRIG2, intRanTRIG, intBCR, intECR, intFER;
NODE     int_BCR, int_FER, int_TRIG, int_ECR;

         intTRIG2    = PulseTrap(intInTRIG, enIntTRIG2, busyTRIG);
         intRanTRIG  = PulseTrap(intInRan,  enRandom2,  busyTRIG);
         intBCR      = PulseTrap(intInBCR,  enIntBCR,   busyANY);
         intECR      = PulseTrap(intInECR,  enIntECR,   busyANY);
         intFER      = PulseTrap(intInFER,  enIntFERx,  busyANY);


         enIntTRIG  = Register00[1];
         enIntTRIG2 = Register00[1] AND /enRandom;
         enIntECR   = Register00[2];
         enIntBCR   = Register00[3];
         enRandom   = Register00[4];
         enRandom2  = Register00[4];
         enIntFERx  = Register00[5];"note x: new: enInFer now = ...x OR enIntECR

         enIntFER = enIntFERx OR enIntECR; "This needed as FER and ECR share osc.


         int_TRIG =  intTRIG2 OR intRanTRIG;
         int_BCR  =  intBCR;
         int_ECR  =  intECR;
         int_FER  =  intFER;



"COMBINED SIGNAL
"----------------

         asyncTRIG  =   (ext_TRIG  OR int_TRIG OR v_TRIG  OR sw_TRIG);
         asyncCAL   =   (ext_CAL               OR v_CAL             );
         asyncBCR   =   (ext_BCR   OR int_BCR  OR v_BCR             );
         asyncFER   =   (ext_FER   OR int_FER  OR v_FER             );
         asyncECR   =   (ext_ECR   OR int_ECR  OR v_ECR             );
         asyncSpare =   (ext_Spare OR             v_Spare           );



"SYNCRONISERS (in asyncXXX, out syncXXX)
"-------------------------------------

NODE     busyCALTRIG    "from CAL state_machine;
            DEFAULT_TO 0;

NODE     burst_CAL,     "CAL generated after CAL-Trig-BCALDelay for CALbursts
         CALTRIG        "Trig generated at end of CAL pulse
            DEFAULT_TO 0;



         syncTRIG  = SYNC(asyncTRIG,  clk2b, disableTRIG, OA_rst) OR CALTRIG;
         syncCAL   = SYNC(asyncCAL,   clk2b, busyANY,     OA_rst);
         syncBCR   = SYNC(asyncBCR,   clk2b, busyANY,     OA_rst);
         syncECR   = SYNC(asyncECR,   clk2b, busyANY,     OA_rst);
         syncFER   = SYNC(asyncFER,   clk2b, busyANY,     OA_rst);
         syncSpare = SYNC(asyncSpare, clk2b, busyANY,     OA_rst);

         syncCALP  = syncCAL OR burst_CAL;



"-------------------------------------------------------------------------------
"DELAYED TRIGGER in: suncTRIG, out: syncDTRIG
"-------------------------------------------------------------------------------

NODE     shift144_clr;
         shift144_clr = syncCAL OR disableTRIG;

NODE     DTRIG,
         DTRIGh;

         SHIFT144 (  syncTRIG, DelaySelect[7..0], clk2b, shift144_clr, OA_rst,
                     DTRIGh, DTRIG );

         syncDTRIG = DTRIG AND (/busyANY OR busyCALTRIG); "AND /syncDTRIG "clocked sig


"-------------------------------------------------------------------------------
" DEAD-TIME BUSY GENERATOR
"-------------------------------------------------------------------------------


NODE     DeadTimer_Counter[5]
            CLOCKED_BY clk2b
            CLOCK_ENABLED_BY enDeadTimer
            RESET_BY doneANY;

         DeadTimer_Counter = DeadTimer_Counter .+. 1;


NODE     DeadTimerGO;
         DeadTimerGO =     syncDTRIG
                        OR syncCALP
                        OR syncBCR
                        OR syncECR
                        OR syncFER
                        OR syncSpare;


         doneANY     =     doneDTRIG
                        OR doneCALP
                        OR doneBCR
                        OR doneECR
                        OR doneFER
                        OR doneSpare
                        OR disableTRIG
                        OR OA_rst;

NODE     enDeadTimer
            CLOCKED_BY DeadTimerGO
            RESET_BY doneANY;
         enDeadTimer = 1;


NODE     DeadTimer1,
         DeadTimer3,
         DeadTimer7,
         DeadTimer27
            DEFAULT_TO  0;


         CASE DeadTimer_Counter
            WHEN 1  => DeadTimer1  = 1;
            WHEN 2  => DeadTimer3  = 1; "note the 'offset' due to clocking.
            WHEN 6  => DeadTimer7  = 1;
            WHEN 26 => DeadTimer27 = 1;
         END CASE;



"-----------------------------------------------
"CONTROL SIGNALS
"-----------------------------------------------


         doneTRIG  = syncTRIG OR OA_rst;

         doneDTRIG = (DeadTimer3  AND busyDTRIG);
         doneCALP  = (DeadTimer27 AND busyCALP) ;
         doneBCR   = (DeadTimer7  AND busyBCR)  ;
         doneECR   = (DeadTimer7  AND busyECR)  ;
         doneFER   = (DeadTimer7  AND busyFER)  ;
         doneSpare = (DeadTimer7  AND busySpare);


         clrBCR   = doneBCR                                                            OR disableTRIG OR OA_rst;
         clrFER   = doneFER   OR busyBCR                                               OR disableTRIG OR OA_rst;
         clrECR   = doneECR   OR busyBCR OR busyFER                                    OR disableTRIG OR OA_rst;
         clrDTRIG = doneDTRIG OR busyBCR OR busyFER OR busyECR                         OR disableTRIG OR OA_rst;
         clrCAL   = doneCAL   OR busyBCR OR busyFER OR busyECR OR busyRTRIG            OR disableTRIG OR OA_rst;
         clrCALP  = doneCALP  OR clrCAL;
         clrSpare = doneSpare OR busyBCR OR busyFER OR busyECR OR busyDTRIG OR busyCAL OR disableTRIG OR OA_rst;



"-------------------------------------------------------------------------------
"SIGNAL OUTPUTS (mapping)
"-------------------------------------------------------------------------------

OUTPUT   outTRIGh,
         outTRIG,
         outTRIG1;

         outTRIG  = syncTRIG;   "pin and track for scoping only (via)
         outTRIGh = DTRIGh;
         outTRIG1 = syncDTRIG;


OUTPUT   SATRIG   CLOCKED_BY clk2b  RESET_BY OA_rst;
OUTPUT   SACAL    CLOCKED_BY clk2b  RESET_BY OA_rst;
OUTPUT   SABCR1   CLOCKED_BY clk2b  RESET_BY OA_rst;
OUTPUT   SAECR1   CLOCKED_BY clk2b  RESET_BY OA_rst;
OUTPUT   SAFER    CLOCKED_BY clk2b  RESET_BY OA_rst;
OUTPUT   SASpare  CLOCKED_BY clk2b  RESET_BY OA_rst;

         SATRIG   = syncDTRIG AND /clrDTRIG;
         SACAL    = syncCALP  AND /clrCAL;
         SABCR1   = syncBCR   AND /clrBCR;
         SAECR1   = syncECR   AND /clrECR;
         SAFER    = syncFER   AND /clrFER;
         SASpare  = syncSpare AND /clrSpare;



OUTPUT   StartSink,
         StartSeq;   "JBL additions

         StartSink = syncTRIG;
         StartSeq  = SASpare;



"-------------------------------------------------------------------------------
"CAL pulse machine (NOT CALP!) - signals for CAL(P)+TRIG cycle
"-------------------------------------------------------------------------------


"burst CAL delay (fixed)
"-----------------------
NODE     BCALdelay[11..0]
            CLOCKED_BY clk2b
            CLOCK_ENABLED_BY enBCALdelay
            RESET_BY rst_BCALDelay;

NODE     rst_BCALDelay;
         rst_BCALDelay = burst_CAL OR disableTRIG OR OA_rst;


         BCALdelay = BCALdelay .+. 1;



NODE     enBCALdelay
            DEFAULT_TO 0;

NODE     repCALBurstMode;
         repCALBurstMode = enCALBurst AND /enExtCAL; "enCALburst from PLD3 = enBurstCnt

NODE     rst_CAL_machine;
         rst_CAL_machine = clrCAL OR disableTRIG OR OA_rst;

"-------------------------------------
STATE_MACHINE  CAL_machine
                  CLOCKED_BY  clk2b
                  RESET_BY rst_CAL_machine;

               STATE wait_busyCALP1:
                  IF busyCALP THEN
                     GOTO wait_busyCALP2;
                  ELSE
                     GOTO wait_busyCALP1;
                  END IF;

               STATE wait_busyCALP2:
                  IF busyCALP THEN     "extra delay for slow to react busys
                     GOTO wait_doneCALP;
                  ELSE
                     GOTO wait_busyCALP1;
                  END IF;


               STATE wait_doneCALP:
                  IF /busyCALP THEN
                     GOTO issue_CALTRIG;
                  ELSE
                     GOTO wait_doneCALP;
                  END IF;

               STATE issue_CALTRIG:
                  CALTRIG = 1;
                  busyCALTRIG = 1;
                  GOTO wait_busyDTRIG;


               STATE wait_busyDTRIG:
                  busyCALTRIG = 1;
                  IF busyDTRIG THEN
                     GOTO wait_doneDTRIG;
                  ELSE
                     GOTO wait_busyDTRIG;
                  END IF;

               STATE wait_doneDTRIG:
                  busyCALTRIG = 1;
                  IF /busyDTRIG THEN
                     GOTO check_burstCAL;
                  ELSE
                     GOTO wait_doneDTRIG;
                  END IF;


               STATE check_burstCAL:
                  IF repCALburstMode THEN
                     GOTO run_BCALdelay;
                  ELSE
                     GOTO finish;
                  END IF;


               STATE run_BCALdelay:
                  enBCALdelay = 1;        "*** what is the default?
                  IF BCALdelay = 01h THEN "### was roll-over on count 3320
                     GOTO issue_burstCAL;
                  ELSE
                     GOTO run_BCALdelay;
                  END IF;


               STATE issue_burstCAL:
                     burst_CAL = 1;
                  GOTO issue_burstCAL2;


               STATE issue_burstCAL2:  "for delays in setting busys
                  GOTO wait_doneCALP;


               "----------------------------------------
               STATE finish:
                     doneCAL = 1;
                     GOTO wait_busyCALP1;

               END CAL_machine;


"===============================================================================
"
"TIM BUSYs
"
"===============================================================================


INPUT    enRodBusy,     "aka enRod_crate_BusyOut ...
         rod_crate_BusyOut, "same as RodBusy
         eclExtBusy,
         nimExtBusy;
         
NODE     extBusy;
         extBusy = eclExtBusy OR nimExtBusy;

 
         
NODE     enIntBusy,  "reg00
         enExtBusy,  "reg00
         vBusy;      "reg02

         enintBusy = Register00[7]; "EnintBusy
         enExtBusy = Register00[15];"EnExtBUSY
         vBusy     = RegisterCommand[7];
         
         
OUTPUT   intBusy;     "to pld3 (stat reg)        
         intBusy = OA_busy;


OUTPUT   BusyOut;     "to pld3 (stat reg) and FP
         BusyOut =    (OA_busy AND enIntBusy) 
                   OR (extBusy AND enExtBusy)
                   OR (rod_crate_busyOut AND enRodBusy)
                   OR vBusy; 


OUTPUT   MExtBusyOut; "to pld3 (stat reg)
         MExtBusyOut = extBusy AND enExtBusy;
         
INPUT    enExtRodBusy_in; " was s2_6[6] 
OUTPUT   enExtRodBusy;    " was sgbD[5]         
         enExtRodBusy = enExtRodBusy_in; "only for feed through at the mo

"===============================================================================
"
" Spare Lines
"
"===============================================================================

"OUTPUT  sgbB[7..0];


"        sgbB[0] = 0;"asyncTRIG; "121
"        sgbB[1] = syncTRIG;     "123
"        sgbB[2] = CALTRIG;      "125
"        sgbB[3] = 0;      "qCALTRIG;     "131
"        sgbB[4] = DTRIG;        "129
"        sgbB[5] = syncDTRIG;    "127
"        sgbB[6] = 0;"SATRIG;    "133
"        sgbB[7] = 0;


INPUT    sgbA[7..0];
INPUT    sgbB[7..0];
INPUT    sgbC[7..0];
INPUT    sgbD[4..2];
        "sgbD[5] now = enExtRodBusy
        "sgbD[0] now = TIM_OK_OUT
        "sgbD[1] now = TTC_ready_in

INPUT    s1_2[7..0];
INPUT    s2_3[5..0];
        "s2_3[6] now = SAClkON_out
        "s2_3[7] now = TTCClkON_out

INPUT    s2_4a[7..0];
INPUT    s2_6[4..0];    "Spare local bus

        "s2_6[5] now = TTC_ready2_6
        "s2_6[6] now = enExtRodBusy_in
        "s2_6[7] now = enTTCClk
        



"===============================================================================