"$Id: pld6.src,v 1.20 2002/05/22 11:36:05 warren Exp $
"==============================================================================
#TITLE    'ATLAS TIM PLD6: Backplane Mapping';
#ENGINEER 'Martin Postranecky / Dominic A Hayes';
#COMPANY  'University College London';
#COMMENT  '';
"==============================================================================
"$Log: pld6.src,v $
"Revision 1.20  2002/05/22 11:36:05  warren
"Added TTCready gating, set nenTTCClk to 0
"
"Revision 1.19  2002/03/22 17:46:59  warren
"new reg clocking
"
"Revision 1.18  2002/02/11 18:34:05  warren
"Added clock sync sparebus signals from stat reg
"
"Revision 1.17  2002/01/16 16:52:12  warren
"tidied tabs
"
"Revision 1.16  2001/11/20 16:54:43  warren
"removed all sgb assignments
"
"Revision 1.15  2001/11/14 20:12:03  warren
"minor layout
"
"Revision 1.14  2001/08/30 12:20:47  warren
"Tidied, Capitalization
"
"Revision 1.13  2001/08/08 18:42:04  warren
"new stm outline
"and signal names case names
"
"Revision 1.12  2001/07/23 11:18:41  warren
"renamed signals with proper polarity n prefixes and removed LOW_TRUEs
"
"Revision 1.11  2001/07/19 10:45:01  warren
"removed unused Spare bus lines
"
"Revision 1.10  2001/06/15 17:01:50  warren
"Cleaned up code organisation
"
"Revision   1.9  2001/04/03 15:45:14  warren "OA_rst stuff
"




"==============================================================================
"MODS
"14jan00 nLEb2 -> /nLEb2.
"23mar00 reg_enttc reg_test --> reg18 reg0E
"        reg0E split between pld5 and pld6. entailed db split into dbh and dbl.
"        wr0E and rst0E nodes created.
"        test_register contains mapped nTTCout data, not input data.
"10may00 vreset replaced by nOA_rst.
"23MAY00 added idTRIG, idBCR, idECR o/ps
"24may00 new i/p RunMode.
"05jun00 enRodBusy added to register18 and o/p to pld2.
"06jun00 o/p enBCClk added in Reg18.
"05jul00 Reg0E changed to Reg24 (so Reg0E no longer split).
"        wr0E and rst0E changed to 24 versions.
"11jul00 dbh/l renamed db and pins refitted to defaults.  same for dbh/loe.
"14jul00 nTTCout id &   tt o/ps clocked as eclID/eclTT (these are input to PLD7)
"11sep00 Regxx, nLEb2, bReadb,   bWriteb now HIGH_TRUE.
"29Sep00 Reduced the enttc_reg. = [...] to [...] = enttc_reg.
"         This solved reg  read problem.
"01Nov00 changed order of component bits in enTTC_Register (..ECR then ..BCR)
"29nov00 added DEFAULT_To 0 to wr24 - MRMW/JBL
"16Feb01 renamed all sigs for Register 24 TO Register 30"
"16Mar01 Removed LOW_TRUE from nOA_rst, and fixed all assos. nOA_rst
"16Mar01 Changes ttc_out to low_true, and moded implicated code.
"21Mar01 Added OA_rst ( = /nOA_rst) and replaced instances of /nOA_rst
"31Jan02 Adding logic to for pld2 sync clock enables
"        Renamed BCCLK to TTCClk
"01Feb02 Some new signals sent to pld2 via spare bus lines
"08Feb02 Added enExtRodBusy_in to En_TTC_reg (repl. enL1ID)
"        enExtRodBusy_in sent to pld2 via s2_6[6]
"        renamed enBCID to enID (enBCId, enL1ID both = enID now)
"20Feb02 reworked idTRIG etc clocking to be on the pin (was just = to eclL1A)
"27Feb02 Changed to new register clocking scheme - with special pld6ness
"24Mar02 Fixed missing OUTPUT on enTTCClk (was a NODE only)...
"17May02 Added input from pld9 via pld2 of TTCready to gate L1Ain, ECRin, BCRin
"22May02 Set nenTTCClk=0 to ensure buffers worked properly with clock sync-sel

"==============================================================================
"                      SIGNAL DECLARATIONS
"==============================================================================

INPUT    nOA_rst;                   "low_true Board reset.
NODE     OA_rst;
         OA_rst = /nOA_rst;
INPUT    RunMode;

INPUT    clk6;                      "sync clock for ecl o/ps.
INPUT    bReadb;                    "buffered VME read.
INPUT    bWriteb;                   "buffered VME write.
INPUT    reg30, Reg18;              "Register enable.
INPUT    nLEb2;                      "VME register clock.

BIPUT    db[15..0]               "databus.
            ENABLED_BY dboe;
NODE     dboe;                "db output enable.





"SIGNALS
"--------
INPUT    SATRIG,
         SABCR1,
         SACAL,
         SAECR1,
         SAFER,
         SASpare;   "Sync'd inputs.
         
INPUT    SABCR2,     "counter rollover signals
         SAECR2;     "                                  
         
INPUT    L1Ain,      "from TTCrx
         BCRin,      "from TTCrx
         ECRin,      "from TTCrx
         CALin,      "from pld9
         FERin,      "from pld9
         Sparein;    "from pld9
         
INPUT    TTin,
         IDin;                                  "Serialised data inputs.

NODE     enL1A,
         enBCR,
         enECR,
         enCAL,
         enFER,
         enSpare;

OUTPUT   enRodBusy,
         enTType,
         enL1ID,
         enBCID,
         enSABCR2,
         enSAECR2,
         enTTCClk,
         nenTTCClk;      "Inverted o/p for /en on clock buffer
                        

         nenTTCCLK = 0; "was = /enTTCClk, but clock select circuit does this now (TIM2);
                        "(and /SAMODE is used in TIM1,0)

NODE     enID;
         enL1ID = enID;
         enBCID = enID;
         
         
        
"==============================================================================
"CODE
"==============================================================================


INPUT    seqTRIG,             "Sequencer inputs.
         seqCAL,
         seqBCR,
         seqECR,
         seqFER,
         seqSpare,
         seqTT,
         seqID;

NODE     L1A,                 "or'd internal signals.
         BCR,
         ECR,
         CAL,
         FER,
         Spare,
         TT,
         ID;

         L1A    = SATRIG  OR           (L1Ain AND enL1A)   OR seqTRIG; "*** en on everything maybe
         BCR    = SABCR1  OR SABCR2 OR (BCRin AND enBCR)   OR seqBCR;  "*** or just on the TTCout
         ECR    = SAECR1  OR SAECR2 OR (ECRin AND enECR)   OR seqECR;
         CAL    = SACAL   OR           (CALin AND enCAL)   OR seqCAL;
         FER    = SAFER   OR           (FERin AND enFER)   OR seqFER;
         Spare  = SASpare OR         (Sparein AND enSpare) OR seqSpare;
         TT     = TTin    OR                                  seqTT;
         ID     = IDin    OR                                  seqID;


"----------------------------------------------------------
"Signal OUTPUTS
"-----------------
OUTPUT   eclL1A,              "
         eclBCR,              "
         eclECR,              "outputs to ECL buffers.
         eclCAL,              "
         eclFER,              "
         eclSpare,            "
         eclID,               "
         eclTT                "
            CLOCKED_BY clk6
            RESET_BY OA_rst;

         eclL1A   = L1A;
         eclBCR   = BCR;
         eclECR   = ECR;
         eclCAL   = CAL;
         eclFER   = FER;
         eclSpare = Spare;
         eclID    = ID;      "addition
         eclTT    = TT;      "addition


OUTPUT   idTRIG, 
         idBCR,       " to pld4 (same as ecl version)
         idECR						
         	CLOCKED_BY clk6
         	RESET_BY OA_rst;

         idTRIG =  L1A;
         idBCR  =  BCR;
         idECR  =  ECR;

"-------------------------------------------------------------------------------
"TTC_OUT
"-------


OUTPUT   nTTCout[7..0];       "outputs to buffer FFs.


"### MODIFY THIS TO CHANGE BACKPLANE MAPPING ###

         nTTCout[7] = /Spare;
         nTTCout[6] = /FER;
         nTTCout[5] = /TT;
         nTTCout[4] = /ID;
         nTTCout[3] = /CAL;
         nTTCout[2] = /BCR;
         nTTCout[1] = /ECR;
         nTTCout[0] = /L1A;

"###############################################


"=============================================================================
"REGISTERS
"=============================================================================


" Reg30 - TEST_REGISTER   (reset by VME write) 
"--------------------------------------------
"One-time/one-way (0->1) latch with reset
"Created without  F/F to overcome limits on multple clock sources for FFs in PLD


NODE     test_register[7..0],  "Reg30
         reg_TTCout[7..0];

         test_register[7..0] = reg_TTCout[7..0];

NODE     rst30,
         wr30;

         reg_TTCout[7] = /rst30 AND (/nTTCout[7] OR reg_TTCout[7]);
         reg_TTCout[6] = /rst30 AND (/nTTCout[6] OR reg_TTCout[6]);
         reg_TTCout[5] = /rst30 AND (/nTTCout[5] OR reg_TTCout[5]);
         reg_TTCout[4] = /rst30 AND (/nTTCout[4] OR reg_TTCout[4]);
         reg_TTCout[3] = /rst30 AND (/nTTCout[3] OR reg_TTCout[3]);
         reg_TTCout[2] = /rst30 AND (/nTTCout[2] OR reg_TTCout[2]);
         reg_TTCout[1] = /rst30 AND (/nTTCout[1] OR reg_TTCout[1]);
         reg_TTCout[0] = /rst30 AND (/nTTCout[0] OR reg_TTCout[0]);

         rst30 = (bWriteb AND Reg30) OR OA_rst;



" EnTTCRegister         (Reg18)
"---------------------------------------------

NODE     enTTC_Register[15..0]
            CLOCKED_BY nLEb2
            RESET_BY OA_rst
            DEFAULT_TO LAST_VALUE;
            
			IF (Reg18 AND bWriteb) THEN
            enTTC_Register[15..0] = db[15..0];
         END IF;


INPUT    TTC_ready2_6;    "from pld2 "was s2_6[5]
         
OUTPUT   enExtRodBusy_in; "via s2_6[6]

         enSABCR2        = enTTC_Register[15];
         enSAECR2        = enTTC_Register[14];

         enTType         = enTTC_Register[10];
         enID            = enTTC_Register[ 9]; "*** new combined IDs, was enBCID
         enExtRodBusy_in = enTTC_Register[ 8]; "*** new for FP input, was enL1ID
         enRodBusy       = enTTC_Register[ 7]; "*** enables output to BP
         enSpare         = enTTC_Register[ 6];
         enFER           = enTTC_Register[ 5];
         enCAL           = enTTC_Register[ 4];
         enBCR           = enTTC_Register[ 3] AND TTC_ready2_6; "*** new 
         enECR           = enTTC_Register[ 2] AND TTC_ready2_6; "*** new
         enL1A           = enTTC_Register[ 1] AND TTC_ready2_6; "*** new
         enTTCClk        = enTTC_Register[ 0];



"==============================================================================
"VME Reads
"=========
         
         IF (Reg30) THEN
            db[15..8] = 0;
            db[7..0]  = test_register;  "VME READs test_register.
         
         ELSIF (Reg18) THEN
            db = enTTC_Register;
           
         END IF;

         dboe = bReadb AND (Reg30 OR Reg18);         "databus output enable.


"==============================================================================
"Spare I/O
"=========


"testing ECR sources
"OUTPUT  sgbB[7..0];    "Spare global bus B

"        sgbB[7] = SAECR1;
"        sgbB[6] = SAECR2;
"        sgbB[5] = ECRin;
"        sgbB[4] = enECR;
"        sgbB[3] = seqECR;
"        sgbB[2] = ECR;
"        sgbB[1] = eclECR;
"        sgbB[0] = idECR;


INPUT    sgbA[7..0];    "Spare global bus A
INPUT    sgbB[7..0];    "Spare global bus B


INPUT    s5_6[7..0];    "Spare local bus
INPUT    s6_7[7..0];    "Spare local bus

INPUT    s2_6[4..0];    "Spare local bus

        "s2_6[5] now = TTC_ready2_6
        "s2_6[6] now = enExtRODBusy_in (OUTPUT)
        "s2_6[7] now = enTTCClk



"==============================================================================
