
	DATE:     Wed May 22 11:46:26 2002

	DESIGN:   pld6
	DEVICE:   M4-256/128:1

	TITLE:    ATLAS TIM PLD6: Backplane Mapping
	ENGINEER: Martin Postranecky / Dominic A Hayes
	COMPANY:  University College London

	Product:     MACHXL
	             Copyright MINC Incorporated 1987-1998
	             Patent 5,140,526 and 5,499,191
	Version:     A6.2.1.11


           M4-256/128 SUCCEEDED FOR 62 FUNCTIONS
           ---------------------------------

 EFFORT_LEVEL: 5
 EFFETIVE UTILIZATION: 100

PARTITIONER REPORT:

	Notes: '@' flags nodes with fanouts within partition group.
	       '#' flags nodes with fanouts beyond partition group.

	Partition A;	Group-type MERGIBLE_GROUP;
	   0 Clocks;   0 Enables;   0 Register Sets
	    0 Functions
	    0 Signals

	Partition B;	Group-type MERGIBLE_GROUP;
	   0 Clocks;   0 Enables;   0 Register Sets
	    0 Functions
	    0 Signals

	Partition D;
	   0 Clocks;   1 Enables;   0 Register Sets
	    8 Functions
	       db[7]          db[6]          db[5]          db[4]         
	      @reg_TTCout[7] @reg_TTCout[6] @reg_TTCout[5] @reg_TTCout[4] 
	    16 Signals
	       nOA_rst            bWriteb            reg30              
	       dboe               enRodBusy          nTTCout[6]         
	       nTTCout[7]         nTTCout[5]         nTTCout[4]         
	       reg_TTCout[7]      reg_TTCout[6]      reg_TTCout[5]      
	       reg_TTCout[4]      enTTC_Register[6]  enTTC_Register[5]  
	       enTTC_Register[4]  

	Partition C;
	   0 Clocks;   1 Enables;   0 Register Sets
	    4 Functions
	       db[3]  db[2]  db[1]  db[0] 
	    10 Signals
	       reg30              dboe               enTTCClk           
	       reg_TTCout[3]      reg_TTCout[2]      reg_TTCout[1]      
	       reg_TTCout[0]      enTTC_Register[3]  enTTC_Register[2]  
	       enTTC_Register[1]  

	Partition E;
	   0 Clocks;   1 Enables;   0 Register Sets
	    4 Functions
	       db[11]  db[10]  db[9]   db[8]  
	    6 Signals
	       reg30               dboe                enTType             
	       enL1ID              enTTC_Register[11]  enExtRodBusy_in     

	Partition F;
	   0 Clocks;   1 Enables;   0 Register Sets
	    4 Functions
	       db[15]  db[14]  db[13]  db[12] 
	    6 Signals
	       reg30               dboe                enSABCR2            
	       enSAECR2            enTTC_Register[13]  enTTC_Register[12]  

	Partition H;
	   2 Clocks;   0 Enables;   1 Register Sets
	    10 Functions
	       enRodBusy      enTType        enL1ID         enBCID        
	       nenTTCClk      idTRIG         idBCR          idECR         
	      #reg_TTCout[2] #reg_TTCout[0] 
	    15 Signals
	       nOA_rst        bWriteb        reg30          Reg18          
	       db[10]         db[9]          db[7]          enRodBusy      
	       enTType        enL1ID         nTTCout[0]     nTTCout[2]     
	       nTTCout[1]     reg_TTCout[2]  reg_TTCout[0]  

	Partition G;
	   1 Clocks;   0 Enables;   1 Register Sets
	    8 Functions
	       eclL1A    eclBCR    eclECR    eclCAL    eclFER   
	       eclSpare  eclID     eclTT    
	    9 Signals
	       nOA_rst     nTTCout[0]  nTTCout[2]  nTTCout[1]  
	       nTTCout[3]  nTTCout[6]  nTTCout[7]  nTTCout[5]  
	       nTTCout[4]  

	Partition I;
	   1 Clocks;   0 Enables;   1 Register Sets
	    5 Functions
	       enSABCR2    nTTCout[0]  nTTCout[2]  nTTCout[1] 
	       nTTCout[3] 
	    24 Signals
	       nOA_rst            bWriteb            Reg18              
	       db[15]             SATRIG             SABCR1             
	       SACAL              SAECR1             SABCR2             
	       SAECR2             L1Ain              BCRin              
	       ECRin              CALin              enSABCR2           
	       seqTRIG            seqCAL             seqBCR             
	       seqECR             enTTC_Register[4]  enTTC_Register[3]  
	       enTTC_Register[2]  enTTC_Register[1]  TTC_ready2_6       

	Partition J;
	   1 Clocks;   0 Enables;   1 Register Sets
	    9 Functions
	       enSAECR2            nTTCout[6]          nTTCout[7]         
	       nTTCout[5]          nTTCout[4]         #enTTC_Register[12] 
	      #enTTC_Register[6]  #enTTC_Register[5]  #enTTC_Register[2]  
	    23 Signals
	       nOA_rst             bWriteb             Reg18               
	       db[14]              db[12]              db[6]               
	       db[5]               db[2]               SAFER               
	       SASpare             FERin               Sparein             
	       TTin                IDin                enSAECR2            
	       seqFER              seqSpare            seqTT               
	       seqID               enTTC_Register[12]  enTTC_Register[6]   
	       enTTC_Register[5]   enTTC_Register[2]   

	Partition L;	Group-type MERGIBLE_GROUP;
	   0 Clocks;   0 Enables;   0 Register Sets
	    0 Functions
	    0 Signals

	Partition K;
	   1 Clocks;   0 Enables;   1 Register Sets
	    10 Functions
	      #dboe                enTTCClk           #reg_TTCout[3]      
	      #reg_TTCout[1]      #enTTC_Register[13] #enTTC_Register[11] 
	       enExtRodBusy_in    #enTTC_Register[4]  #enTTC_Register[3]  
	      #enTTC_Register[1]  
	    23 Signals
	       nOA_rst             bReadb              bWriteb             
	       reg30               Reg18               db[13]              
	       db[11]              db[8]               db[4]               
	       db[3]               db[1]               db[0]               
	       enTTCClk            nTTCout[1]          nTTCout[3]          
	       reg_TTCout[3]       reg_TTCout[1]       enTTC_Register[13]  
	       enTTC_Register[11]  enExtRodBusy_in     enTTC_Register[4]   
	       enTTC_Register[3]   enTTC_Register[1]   

	Partition M;	Group-type MERGIBLE_GROUP;
	   0 Clocks;   0 Enables;   0 Register Sets
	    0 Functions
	    0 Signals

	Partition N;	Group-type MERGIBLE_GROUP;
	   0 Clocks;   0 Enables;   0 Register Sets
	    0 Functions
	    0 Signals

	Partition P;	Group-type MERGIBLE_GROUP;
	   0 Clocks;   0 Enables;   0 Register Sets
	    0 Functions
	    0 Signals

	Partition O;	Group-type MERGIBLE_GROUP;
	   0 Clocks;   0 Enables;   0 Register Sets
	    0 Functions
	    0 Signals




DEVICE and BLOCK RESOURCE TABLE LEGEND:

    1.  Reserved signifies resources that have been
        set aside by the global MACH_UTILIZATION
        property or by assigning NO_CONNECT to device pins.

    2.  A Set and Reset Group is the largest collection of
        functions that have both a preset and a reset signal
        such that every function in the group has both the same
        preset signal and the same reset signal.

    3.  A Set or Reset Group is the largest collection of
        functions that all have a preset signal or all have
        a reset signal but none have both. Also, every function
        in the group has either the same preset signal, if
        the functions have presets or the same reset signal, if
        the functions have resets.

    4.  Product terms are split into two types.  Equation Pterms
        and Asynchronous Pterms. Equation pterms are product terms 
        used for an equation. Asynchronous pterms are product terms  
        used for control functions in the asynchronous mode

    5.  Clusters are groups of product terms allocated
        to macrocells. Cluster pterms are pterms in all
        clusters steered to a macrocell regardless of whether
        all of the pterms are used by the function.


  M4-256/128 DEVICE RESOURCE UTILIZATION:

           Resource           Device Capacity   Used     Remaining  Utilization
     :==========================================================================:
     : Clock Pins                    4           2                              :
     :    Reserved Clock Pins                    0                              :
     :    ------------------------------------------------------------------    :
     :    Total Clock Pins           4           2            2         50%     :
     :==========================================================================:
     : Input Pins                   14           0                              :
     :    Reserved Input Pins                    0                              :
     :    ------------------------------------------------------------------    :
     :    Total Input Pins          14           0           14          0%     :
     :==========================================================================:
     : I/O Pins                    128                                          :
     :    Inputs                                68                              :
     :    Non-Tri-state Outputs                 28                              :
     :    Tri-state Outputs                     16                              :
     :    Reserved I/O Pins                      0                              :
     :    ------------------------------------------------------------------    :
WARN :    Total I/O Pins           128         112           16         88%     :
     :==========================================================================:
     : Input Registers             128                                          :
     :    D-Latches                              0                              :
     :    D-Flops                                0                              :
     :    ------------------------------------------------------------------    :
     :    Total Input Registers    128           0          128          0%     :
     :==========================================================================:
     : Macrocells                  256                                          :
     :    Combinatorial                         35                              :
     :    D-Latches                              0                              :
     :    D-Flops                               11                              :
     :    T-Flops                               16                              :
     :    Reserved Macrocells                    0                              :
     :    ------------------------------------------------------------------    :
     :    Total Macrocells         256          62          194         24%     :
     :==========================================================================:
     : Macrocell Mode                                                           :
     :    Synchronous                           62                              :
     :    Asynchronous                           0                              :
     :==========================================================================:
     : Nodes                       384          18          366          5%     :
     :==========================================================================:
     : Output Enables              128                                          :
     :    Enables                               16                              :
     :    Enables only for Test                  0                              :
     :    ------------------------------------------------------------------    :
     :    Total Output Enables     128          16          112         13%     :
     :==========================================================================:
     : XORs                        256           0          256          0%     :
     :==========================================================================:
     : Cluster Pterms             1280         237         1043         19%     :
     :==========================================================================:
     : Product Terms              1280                                          :
     :    Equation Pterms                      112                              :
     :    Async Pterms                           0                              :
     :    ------------------------------------------------------------------    :
     :    Total Pterms            1280         112         1168          9%     :
     :==========================================================================:
     : Product Term Clocks         256           0          256          0%     :
     :==========================================================================:
     : Central SM Inputs           384                                          :
     :    Pin Feedback                          46                              :
     :    Internal Feedback                     33                              :
     :    ------------------------------------------------------------------    :
     :    Total CSM Inputs         384          79          305         21%     :
     :==========================================================================:
     : Central SM Fanouts          544         132          412         24%     :
     :==========================================================================:
     : Set Groups                                                               :
     :    Set or Reset Groups      256           1          255          0%     :
     :    Set and Reset Groups      16           0           16          0%     :
     :==========================================================================:


BLOCK RESOURCE SUMMARY:

     :==========================================================================:
     :PAL       BLK   PT    I/O   IN                   CLST  EQN   SIGNAL ARRAY :
     :BLOCK     CLKS  CLKS  PINS  REG   MC  OES  XORS  PT    PTS   FANOUT INPUT :
     :==========================================================================:
     :AVAILABLE  4    16    8     8     16   8    16   80    80    24      34   :
     :==========================================================================:
     :USED                                                                      :
     :A          0    0     8     0     0    0    0    0     0     8       0    :
     :B          0    0     5     0     0    0    0    0     0     4       0    :
     :D          0    0     8     0     8    4    0    40    20    8       16   :
     :C          0    0     8     0     4    4    0    20    8     4       10   :
     :E          0    0     8     0     4    4    0    8     4     4       6    :
     :F          0    0     8     0     4    4    0    8     4     4       6    :
     :H          2    0     8     0     10   0    0    29    17    5       15   :
     :G          1    0     8     0     8    0    0    20    8     0       9    :
     :I          1    0     5     0     5    0    0    25    13    5       24   :
     :J          1    0     5     0     9    0    0    37    16    9       23   :
     :L          0    0     8     0     0    0    0    0     0     8       0    :
     :K          1    0     8     0     10   0    0    50    22    11      23   :
     :M          0    0     8     0     0    0    0    0     0     8       0    :
     :N          0    0     1     0     0    0    0    0     0     1       0    :
     :P          0    0     8     0     0    0    0    0     0     0       0    :
     :O          0    0     8     0     0    0    0    0     0     0       0    :
     :==========================================================================:


     BLK CLKS       - Block Clocks 
     PT CLKS        - Product Term Clocks
     I/O Pins       - I/O pins (Inputs + Non-Tristate + Tristate + Reserved) 
     IN REG         - Input Registers (D-Latches + D-FLops) 
     MC             - Macrocells (Comb + D-Latches + D-Flops + T-Flops + Reserved)
     OES            - Output Enables
     XOR            - Exclusive ORs
     CLST PTS       - Maximum of Asynchronous, equation and single Cluster Product Terms 
     EQN PTS        - Product Terms used in the pal block
     SIGNAL FANOUT  - Block Fanout to Central Switch Matrix
     ARRAY INPUTS   - Block Fanin from Central Switch Matrix


POWER SUMMARY:

Number of blocks with power set to LOW is 7
Number of blocks with power set to HIGH is 9

CLOCK ASSIGNMENTS:

    Notes: block usage 'H' indicates used in TRUE sense.
           block usage 'L' indicates used in INVERSE sense.

    clock signal        [ 64] clk6
    pin                 74
    block usage           ,   ,   ,   ,   ,   , H , H , 
                          ,   ,   ,   ,   ,   ,   ,   

    clock signal        [ 69] nLEb2
    pin                 83
    block usage           ,   ,   ,   ,   ,   , H ,   , 
                        H , H ,   , H ,   ,   ,   ,   


SIGNAL DIRECTORY:

    LEGEND: The first line has the Signal Index, Signal Type and Signal name.
            The Signal Type is one of {Input | Reg.Input | Reg.Feedback | Node|
            Tri.State | Output}. The Second line contains the assignment
            information for the signal. If the signal appears on a pin, the pin
            number and type is provided. Functions provide macrocell assignment
            information along with specifics on how the function is fit.This
            includes the number of pterms required, the register type used to 
            implement the function, and notes if the function implementation has
            any notable characteristics.

    Notes: Register type suffix '_X' indicates XOR used;
           Register type suffix '_A' indicates Asynchronous mode used;
           Register type suffix '_LT' indicates function is LOW_TRUE.
           'RS_SWAP' flags functions which are preset at power-on.
           'OE' flags tri-state functions.

  [000]  Tri-state:     db[15]
         Tri-internal:  $NONE$
         Pin 45 (I/O)  Block F  Macrocell_F08 1 Pterm COMB           OE

  [001]  Tri-state:     db[14]
         Tri-internal:  $NONE$
         Pin 44 (I/O)  Block F  Macrocell_F05 1 Pterm COMB           OE

  [002]  Tri-state:     db[13]
         Tri-internal:  $NONE$
         Pin 43 (I/O)  Block F  Macrocell_F03 1 Pterm COMB           OE

  [003]  Tri-state:     db[12]
         Tri-internal:  $NONE$
         Pin 42 (I/O)  Block F  Macrocell_F00 1 Pterm COMB           OE

  [004]  Tri-state:     db[11]
         Tri-internal:  $NONE$
         Pin 35 (I/O)  Block E  Macrocell_E08 1 Pterm COMB           OE

  [005]  Tri-state:     db[10]
         Tri-internal:  $NONE$
         Pin 34 (I/O)  Block E  Macrocell_E05 1 Pterm COMB           OE

  [006]  Tri-state:     db[9]
         Tri-internal:  $NONE$
         Pin 33 (I/O)  Block E  Macrocell_E03 1 Pterm COMB           OE

  [007]  Tri-state:     db[8]
         Tri-internal:  $NONE$
         Pin 32 (I/O)  Block E  Macrocell_E00 1 Pterm COMB           OE

  [008]  Tri-state:     db[7]
         Tri-internal:  $NONE$
         Pin 16 (I/O)  Block D  Macrocell_D08 2 Pterm COMB           OE

  [009]  Tri-state:     db[6]
         Tri-internal:  $NONE$
         Pin 15 (I/O)  Block D  Macrocell_D10 2 Pterm COMB           OE

  [010]  Tri-state:     db[5]
         Tri-internal:  $NONE$
         Pin 14 (I/O)  Block D  Macrocell_D00 2 Pterm COMB           OE

  [011]  Tri-state:     db[4]
         Tri-internal:  $NONE$
         Pin 13 (I/O)  Block D  Macrocell_D01 2 Pterm COMB           OE

  [012]  Tri-state:     db[3]
         Tri-internal:  $NONE$
         Pin 6 (I/O)  Block C  Macrocell_C08 2 Pterm COMB           OE

  [013]  Tri-state:     db[2]
         Tri-internal:  $NONE$
         Pin 5 (I/O)  Block C  Macrocell_C10 2 Pterm COMB           OE

  [014]  Tri-state:     db[1]
         Tri-internal:  $NONE$
         Pin 4 (I/O)  Block C  Macrocell_C00 2 Pterm COMB           OE

  [015]  Tri-state:     db[0]
         Tri-internal:  $NONE$
         Pin 3 (I/O)  Block C  Macrocell_C01 2 Pterm COMB           OE

  [016]  Node:          dboe
                        Block K  Macrocell_K14 2 Pterm COMB          

  [017]  Output:        enRodBusy
         Pin 67 (I/O)  Block H  Macrocell_H13 2 Pterm TFF           

  [018]  Output:        enTType
         Pin 66 (I/O)  Block H  Macrocell_H00 2 Pterm TFF           

  [019]  Output:        enL1ID
         Pin 65 (I/O)  Block H  Macrocell_H03 2 Pterm TFF           

  [020]  Output:        enBCID
         Pin 64 (I/O)  Block H  Macrocell_H02 1 Pterm COMB          

  [021]  Output:        enSABCR2
         Pin 90 (I/O)  Block I  Macrocell_I13 2 Pterm TFF           

  [022]  Output:        enSAECR2
         Pin 100 (I/O)  Block J  Macrocell_J13 2 Pterm TFF           

  [023]  Output:        enTTCClk
         Pin 107 (I/O)  Block K  Macrocell_K00 2 Pterm TFF           

  [024]  Output:        nenTTCClk
         Pin 68 (I/O)  Block H  Macrocell_H11 1 Pterm COMB          

  [025]  Output:        nTTCout[0]
         Pin 86 (I/O)  Block I  Macrocell_I00 3 Pterm COMB          

  [026]  Output:        nTTCout[2]
         Pin 88 (I/O)  Block I  Macrocell_I10 3 Pterm COMB          

  [027]  Output:        nTTCout[1]
         Pin 87 (I/O)  Block I  Macrocell_I05 3 Pterm COMB          

  [028]  Output:        nTTCout[3]
         Pin 89 (I/O)  Block I  Macrocell_I11 2 Pterm COMB          

  [029]  Output:        nTTCout[6]
         Pin 98 (I/O)  Block J  Macrocell_J11 2 Pterm COMB          

  [030]  Output:        nTTCout[7]
         Pin 99 (I/O)  Block J  Macrocell_J08 2 Pterm COMB          

  [031]  Output:        nTTCout[5]
         Pin 97 (I/O)  Block J  Macrocell_J05 1 Pterm COMB          

  [032]  Output:        nTTCout[4]
         Pin 96 (I/O)  Block J  Macrocell_J03 1 Pterm COMB          

  [033]  Output:        eclL1A
         Pin 58 (I/O)  Block G  Macrocell_G12 1 Pterm DFF           

  [034]  Output:        eclBCR
         Pin 54 (I/O)  Block G  Macrocell_G05 1 Pterm DFF           

  [035]  Output:        eclECR
         Pin 56 (I/O)  Block G  Macrocell_G00 1 Pterm DFF           

  [036]  Output:        eclCAL
         Pin 55 (I/O)  Block G  Macrocell_G02 1 Pterm DFF           

  [037]  Output:        eclFER
         Pin 57 (I/O)  Block G  Macrocell_G14 1 Pterm DFF           

  [038]  Output:        eclSpare
         Pin 59 (I/O)  Block G  Macrocell_G06 1 Pterm DFF           

  [039]  Output:        eclID
         Pin 60 (I/O)  Block G  Macrocell_G04 1 Pterm DFF           

  [040]  Output:        eclTT
         Pin 61 (I/O)  Block G  Macrocell_G01 1 Pterm DFF           

  [041]  Output:        idTRIG
         Pin 69 (I/O)  Block H  Macrocell_H04 1 Pterm DFF           

  [042]  Output:        idBCR
         Pin 70 (I/O)  Block H  Macrocell_H09 1 Pterm DFF           

  [043]  Output:        idECR
         Pin 71 (I/O)  Block H  Macrocell_H01 1 Pterm DFF           

  [044]  Node:          reg_TTCout[7]
                        Block D  Macrocell_D06 3 Pterm COMB          

  [045]  Node:          reg_TTCout[6]
                        Block D  Macrocell_D07 3 Pterm COMB          

  [046]  Node:          reg_TTCout[5]
                        Block D  Macrocell_D14 3 Pterm COMB          

  [047]  Node:          reg_TTCout[4]
                        Block D  Macrocell_D05 3 Pterm COMB          

  [048]  Node:          reg_TTCout[3]
                        Block K  Macrocell_K10 3 Pterm COMB          

  [049]  Node:          reg_TTCout[2]
                        Block H  Macrocell_H07 3 Pterm COMB          

  [050]  Node:          reg_TTCout[1]
                        Block K  Macrocell_K13 3 Pterm COMB          

  [051]  Node:          reg_TTCout[0]
                        Block H  Macrocell_H15 3 Pterm COMB          

  [052]  Node:          enTTC_Register[13]
                        Block K  Macrocell_K11 2 Pterm TFF           

  [053]  Node:          enTTC_Register[12]
                        Block J  Macrocell_J15 2 Pterm TFF           

  [054]  Node:          enTTC_Register[11]
                        Block K  Macrocell_K09 2 Pterm TFF           

  [055]  Output:        enExtRodBusy_in
         Pin 108 (I/O)  Block K  Macrocell_K01 2 Pterm TFF           

  [056]  Node:          enTTC_Register[6]
                        Block J  Macrocell_J00 2 Pterm TFF           

  [057]  Node:          enTTC_Register[5]
                        Block J  Macrocell_J14 2 Pterm TFF           

  [058]  Node:          enTTC_Register[4]
                        Block K  Macrocell_K08 2 Pterm TFF           

  [059]  Node:          enTTC_Register[3]
                        Block K  Macrocell_K07 2 Pterm TFF           

  [060]  Node:          enTTC_Register[2]
                        Block J  Macrocell_J01 2 Pterm TFF           

  [061]  Node:          enTTC_Register[1]
                        Block K  Macrocell_K06 2 Pterm TFF           

  [062]  Input:         nOA_rst
         Pin 206 (I/O)  Block B  

  [063]  Input:         RunMode
         Pin 201 (I/O)  Block B  

  [064]  Input:         clk6
         Pin 74 (InClk)

  [065]  Input:         bReadb
         Pin 202 (I/O)  Block B  

  [066]  Input:         bWriteb
         Pin 149 (I/O)  Block N  

  [067]  Input:         reg30
         Pin 204 (I/O)  Block B  

  [068]  Input:         Reg18
         Pin 203 (I/O)  Block B  

  [069]  Input:         nLEb2
         Pin 83 (InClk)

  [070]  Input:         SATRIG
         Pin 143 (I/O)  Block M  

  [071]  Input:         SABCR1
         Pin 136 (I/O)  Block M  

  [072]  Input:         SACAL
         Pin 137 (I/O)  Block M  

  [073]  Input:         SAECR1
         Pin 140 (I/O)  Block M  

  [074]  Input:         SAFER
         Pin 141 (I/O)  Block M  

  [075]  Input:         SASpare
         Pin 142 (I/O)  Block M  

  [076]  Input:         SABCR2
         Pin 138 (I/O)  Block M  

  [077]  Input:         SAECR2
         Pin 139 (I/O)  Block M  

  [078]  Input:         L1Ain
         Pin 194 (I/O)  Block A  

  [079]  Input:         BCRin
         Pin 190 (I/O)  Block A  

  [080]  Input:         ECRin
         Pin 191 (I/O)  Block A  

  [081]  Input:         CALin
         Pin 197 (I/O)  Block A  

  [082]  Input:         FERin
         Pin 192 (I/O)  Block A  

  [083]  Input:         Sparein
         Pin 195 (I/O)  Block A  

  [084]  Input:         TTin
         Pin 196 (I/O)  Block A  

  [085]  Input:         IDin
         Pin 193 (I/O)  Block A  

  [086]  Input:         seqTRIG
         Pin 123 (I/O)  Block L  

  [087]  Input:         seqCAL
         Pin 118 (I/O)  Block L  

  [088]  Input:         seqBCR
         Pin 117 (I/O)  Block L  

  [089]  Input:         seqECR
         Pin 119 (I/O)  Block L  

  [090]  Input:         seqFER
         Pin 120 (I/O)  Block L  

  [091]  Input:         seqSpare
         Pin 122 (I/O)  Block L  

  [092]  Input:         seqTT
         Pin 124 (I/O)  Block L  

  [093]  Input:         seqID
         Pin 121 (I/O)  Block L  

  [094]  Input:         TTC_ready2_6
         Pin 109 (I/O)  Block K  

  [095]  Input:         sgbA[7]
         Pin 168 (I/O)  Block P  

  [096]  Input:         sgbA[6]
         Pin 169 (I/O)  Block P  

  [097]  Input:         sgbA[5]
         Pin 170 (I/O)  Block P  

  [098]  Input:         sgbA[4]
         Pin 171 (I/O)  Block P  

  [099]  Input:         sgbA[3]
         Pin 172 (I/O)  Block P  

  [100]  Input:         sgbA[2]
         Pin 173 (I/O)  Block P  

  [101]  Input:         sgbA[1]
         Pin 174 (I/O)  Block P  

  [102]  Input:         sgbA[0]
         Pin 175 (I/O)  Block P  

  [103]  Input:         sgbB[7]
         Pin 158 (I/O)  Block O  

  [104]  Input:         sgbB[6]
         Pin 159 (I/O)  Block O  

  [105]  Input:         sgbB[5]
         Pin 160 (I/O)  Block O  

  [106]  Input:         sgbB[4]
         Pin 161 (I/O)  Block O  

  [107]  Input:         sgbB[3]
         Pin 162 (I/O)  Block O  

  [108]  Input:         sgbB[2]
         Pin 163 (I/O)  Block O  

  [109]  Input:         sgbB[1]
         Pin 164 (I/O)  Block O  

  [110]  Input:         sgbB[0]
         Pin 165 (I/O)  Block O  

  [111]  Input:         s5_6[7]
         Pin 36 (I/O)  Block E  

  [112]  Input:         s5_6[6]
         Pin 37 (I/O)  Block E  

  [113]  Input:         s5_6[5]
         Pin 38 (I/O)  Block E  

  [114]  Input:         s5_6[4]
         Pin 39 (I/O)  Block E  

  [115]  Input:         s5_6[3]
         Pin 46 (I/O)  Block F  

  [116]  Input:         s5_6[2]
         Pin 47 (I/O)  Block F  

  [117]  Input:         s5_6[1]
         Pin 48 (I/O)  Block F  

  [118]  Input:         s5_6[0]
         Pin 49 (I/O)  Block F  

  [119]  Input:         s6_7[7]
         Pin 7 (I/O)  Block C  

  [120]  Input:         s6_7[6]
         Pin 8 (I/O)  Block C  

  [121]  Input:         s6_7[5]
         Pin 9 (I/O)  Block C  

  [122]  Input:         s6_7[4]
         Pin 10 (I/O)  Block C  

  [123]  Input:         s6_7[3]
         Pin 17 (I/O)  Block D  

  [124]  Input:         s6_7[2]
         Pin 18 (I/O)  Block D  

  [125]  Input:         s6_7[1]
         Pin 19 (I/O)  Block D  

  [126]  Input:         s6_7[0]
         Pin 20 (I/O)  Block D  

  [127]  Input:         s2_6[4]
         Pin 110 (I/O)  Block K  

  [128]  Input:         s2_6[3]
         Pin 111 (I/O)  Block K  

  [129]  Input:         s2_6[2]
         Pin 112 (I/O)  Block K  

  [130]  Input:         s2_6[1]
         Pin 113 (I/O)  Block K  

  [131]  Input:         s2_6[0]
         Pin 114 (I/O)  Block K  

POWER TABLE:

BLOCK   A:    LOW
BLOCK   B:    LOW
BLOCK   D:    HIGH
BLOCK   C:    HIGH
BLOCK   E:    HIGH
BLOCK   F:    HIGH
BLOCK   H:    HIGH
BLOCK   G:    HIGH
BLOCK   I:    HIGH
BLOCK   J:    HIGH
BLOCK   L:    LOW
BLOCK   K:    HIGH
BLOCK   M:    LOW
BLOCK   N:    LOW
BLOCK   P:    LOW
BLOCK   O:    LOW


FANOUT TABLE:

Signal_Src       Fanouts Blk-Mux-------------------------------------


PAL_BLOCK 'A'
[078] Pin   194   I24 
[079] Pin   190   I30 
[080] Pin   191   I15 
[081] Pin   197   I17 
[082] Pin   192   J08 
[083] Pin   195   J17 
[084] Pin   196   J00 
[085] Pin   193   J19 

PAL_BLOCK 'B'
[062] Pin   206   D12 H08 G08 I12 J18 K12 
[063] Pin   201   
[065] Pin   202   K25 
[067] Pin   204   D14 C14 E22 F22 H14 K22 
[068] Pin   203   H06 I09 J09 K09 

PAL_BLOCK 'D'
[008] Pin   16   H07 
[009] Pin   15   J20 
[010] Pin   14   J04 
[011] Pin   13   K23 
[044] Mcell D06  D21 
[045] Mcell D07  D17 
[046] Mcell D14  D09 
[047] Mcell D05  D24 
[123] Pin   17   
[124] Pin   18   
[125] Pin   19   
[126] Pin   20   

PAL_BLOCK 'C'
[012] Pin   6   K19 
[013] Pin   5   J07 
[014] Pin   4   K15 
[015] Pin   3   K27 
[119] Pin   7   
[120] Pin   8   
[121] Pin   9   
[122] Pin   10   

PAL_BLOCK 'E'
[004] Pin   35   K08 
[005] Pin   34   H33 
[006] Pin   33   H22 
[007] Pin   32   K14 
[111] Pin   36   
[112] Pin   37   
[113] Pin   38   
[114] Pin   39   

PAL_BLOCK 'F'
[000] Pin   45   I31 
[001] Pin   44   J03 
[002] Pin   43   K02 
[003] Pin   42   J24 
[115] Pin   46   
[116] Pin   47   
[117] Pin   48   
[118] Pin   49   

PAL_BLOCK 'H'
[017] Mcell H13  D23 H01 
[018] Mcell H00  E17 H17 
[019] Mcell H03  E14 H05 
[049] Mcell H07  C00 H00 
[051] Mcell H15  C10 H10 

PAL_BLOCK 'I'
[021] Mcell I13  F00 I23 
[025] Mcell I00  H24 G13 
[026] Mcell I10  H04 G00 
[027] Mcell I05  H20 G25 K20 
[028] Mcell I11  G03 K24 

PAL_BLOCK 'J'
[022] Mcell J13  F02 J05 
[029] Mcell J11  D27 G26 
[030] Mcell J08  D22 G02 
[031] Mcell J05  D20 G01 
[032] Mcell J03  D07 G07 
[053] Mcell J15  F21 J21 
[056] Mcell J00  D15 J28 
[057] Mcell J14  D08 J06 
[060] Mcell J01  C02 I02 J16 

PAL_BLOCK 'L'
[086] Pin   123   I19 
[087] Pin   118   I28 
[088] Pin   117   I27 
[089] Pin   119   I18 
[090] Pin   120   J10 
[091] Pin   122   J01 
[092] Pin   124   J30 
[093] Pin   121   J12 

PAL_BLOCK 'K'
[016] Mcell K14  D01 C01 E01 F01 
[023] Mcell K00  C06 K04 
[048] Mcell K10  C18 K26 
[050] Mcell K13  C09 K00 
[052] Mcell K11  F06 K01 
[054] Mcell K09  E05 K21 
[055] Mcell K01  E13 K30 
[058] Mcell K08  D10 I06 K06 
[059] Mcell K07  C12 I32 K32 
[061] Mcell K06  C04 I04 K05 
[094] Pin   109   I03 
[127] Pin   110   
[128] Pin   111   
[129] Pin   112   
[130] Pin   113   
[131] Pin   114   

PAL_BLOCK 'M'
[070] Pin   143   I11 
[071] Pin   136   I25 
[072] Pin   137   I22 
[073] Pin   140   I01 
[074] Pin   141   J15 
[075] Pin   142   J25 
[076] Pin   138   I33 
[077] Pin   139   I08 

PAL_BLOCK 'N'
[066] Pin   149   D02 H02 I13 J02 K13 

PAL_BLOCK 'P'
[095] Pin   168   
[096] Pin   169   
[097] Pin   170   
[098] Pin   171   
[099] Pin   172   
[100] Pin   173   
[101] Pin   174   
[102] Pin   175   

PAL_BLOCK 'O'
[103] Pin   158   
[104] Pin   159   
[105] Pin   160   
[106] Pin   161   
[107] Pin   162   
[108] Pin   163   
[109] Pin   164   
[110] Pin   165   




BLOCK CONFIGURATION TABLES:

   Notes: '*' indicates that the pin is bonded-out


BLOCK 'A': UNUSED

BLOCK 'B': UNUSED

BLOCK 'D': POWER=HIGH
   CONTROL PTERMS:
           OE00 = dboe ;


   SIGNALS CROSS REFERENCE:

ARRAY INPUTS:
Input  Sig_ID   Source     Signal Name
-----  ------   ------     -----------
I01    [016]    MC-K14     dboe
I23    [017]    MC-H13     enRodBusy
I27    [029]    MC-J11     nTTCout[6]
I22    [030]    MC-J08     nTTCout[7]
I20    [031]    MC-J05     nTTCout[5]
I07    [032]    MC-J03     nTTCout[4]
I21    [044]    MC-D06     reg_TTCout[7]
I17    [045]    MC-D07     reg_TTCout[6]
I09    [046]    MC-D14     reg_TTCout[5]
I24    [047]    MC-D05     reg_TTCout[4]
I15    [056]    MC-J00     enTTC_Register[6]
I08    [057]    MC-J14     enTTC_Register[5]
I10    [058]    MC-K08     enTTC_Register[4]
I12    [062]    Pin 206    nOA_rst
I02    [066]    Pin 149    bWriteb
I14    [067]    Pin 204    reg30

SIGNAL FANOUTS
TYPE   Sig_ID Signal Name
----   ------ -----------
OUT    [008]  db[7]
OUT    [009]  db[6]
OUT    [010]  db[5]
OUT    [011]  db[4]
NODE   [044]  reg_TTCout[7]
NODE   [045]  reg_TTCout[6]
NODE   [046]  reg_TTCout[5]
NODE   [047]  reg_TTCout[4]

ARRAY INPUTS AND CLUSTER ALLOCATION TABLES                      

   IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII    CCCCCCCCCCCCCCCC      P C S  R  S   
   0000000000111111111122222222223333 ## 0000000000111111 Pts  O L E  S  L   
MC 0123456789012345678901234567890123 AI 0123456789012345 Used L K T  T  W Node  OE   Pin
00 -x------xx----x-------------------  4 05--------------   2  H - -- -- F [---] OE0 [010]
01 -x--------x---x---------x---------  4 50--------------   2  H - -- -- F [---] OE0 [011]
02 ----------------------------------  0 --5-------------   -  - - -- -- - [---] GND [---]
03 ----------------------------------  0 ---5------------   -  - - -- -- - [---] GND [---]
04 ----------------------------------  0 ----0-----------   -  - - -- -- - [---] GND [---]
05 --x----x----x-x---------x---------  5 ----50----------   3  L - -- -- - (047) VCC [047]
06 --x---------x-x------xx-----------  5 -----55---------   3  L - -- -- - (044) VCC [044]
07 --x---------x-x--x---------x------  5 -------5--------   3  L - -- -- - (045) VCC [045]
08 -x------------x------x-x----------  4 --------55------   2  H - -- -- F [---] OE0 [008]
09 ----------------------------------  0 ---------0------   -  - - -- -- - [---] GND [---]
10 -x------------xx-x----------------  4 ----------55----   2  H - -- -- F [---] OE0 [009]
11 ----------------------------------  0 -----------0----   -  - - -- -- - [---] GND [---]
12 ----------------------------------  0 ------------5---   -  - - -- -- - [---] GND [---]
13 ----------------------------------  0 -------------0--   -  - - -- -- - [---] GND [---]
14 --x------x--x-x-----x-------------  5 -------------55-   3  L - -- -- - (046) VCC [046]
15 ----------------------------------  0 ---------------5   -  - - -- -- - [---] GND [---]


BLOCK 'C': POWER=HIGH
   CONTROL PTERMS:
           OE00 = dboe ;


   SIGNALS CROSS REFERENCE:

ARRAY INPUTS:
Input  Sig_ID   Source     Signal Name
-----  ------   ------     -----------
I01    [016]    MC-K14     dboe
I06    [023]    MC-K00     enTTCClk
I18    [048]    MC-K10     reg_TTCout[3]
I00    [049]    MC-H07     reg_TTCout[2]
I09    [050]    MC-K13     reg_TTCout[1]
I10    [051]    MC-H15     reg_TTCout[0]
I12    [059]    MC-K07     enTTC_Register[3]
I02    [060]    MC-J01     enTTC_Register[2]
I04    [061]    MC-K06     enTTC_Register[1]
I14    [067]    Pin 204    reg30

SIGNAL FANOUTS
TYPE   Sig_ID Signal Name
----   ------ -----------
OUT    [012]  db[3]
OUT    [013]  db[2]
OUT    [014]  db[1]
OUT    [015]  db[0]

ARRAY INPUTS AND CLUSTER ALLOCATION TABLES                      

   IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII    CCCCCCCCCCCCCCCC      P C S  R  S   
   0000000000111111111122222222223333 ## 0000000000111111 Pts  O L E  S  L   
MC 0123456789012345678901234567890123 AI 0123456789012345 Used L K T  T  W Node  OE   Pin
00 -x--x----x----x-------------------  4 5---------------   2  H - -- -- F [---] OE0 [014]
01 -x----x---x---x-------------------  4 -5-5------------   2  H - -- -- F [---] OE0 [015]
02 ----------------------------------  0 --5-------------   -  - - -- -- - [---] GND [---]
03 ----------------------------------  0 ---0------------   -  - - -- -- - [---] GND [---]
04 ----------------------------------  0 ----5-----------   -  - - -- -- - [---] GND [---]
05 ----------------------------------  0 -----5----------   -  - - -- -- - [---] GND [---]
06 ----------------------------------  0 ------5---------   -  - - -- -- - [---] GND [---]
07 ----------------------------------  0 -------0--------   -  - - -- -- - [---] GND [---]
08 -x----------x-x---x---------------  4 -------55-------   2  H - -- -- F [---] OE0 [012]
09 ----------------------------------  0 ---------5------   -  - - -- -- - [---] GND [---]
10 xxx-----------x-------------------  4 ----------55----   2  H - -- -- F [---] OE0 [013]
11 ----------------------------------  0 -----------0----   -  - - -- -- - [---] GND [---]
12 ----------------------------------  0 ------------5---   -  - - -- -- - [---] GND [---]
13 ----------------------------------  0 -------------5--   -  - - -- -- - [---] GND [---]
14 ----------------------------------  0 --------------5-   -  - - -- -- - [---] GND [---]
15 ----------------------------------  0 ---------------5   -  - - -- -- - [---] GND [---]


BLOCK 'E': POWER=HIGH
   CONTROL PTERMS:
           OE00 = dboe ;


   SIGNALS CROSS REFERENCE:

ARRAY INPUTS:
Input  Sig_ID   Source     Signal Name
-----  ------   ------     -----------
I01    [016]    MC-K14     dboe
I17    [018]    MC-H00     enTType
I14    [019]    MC-H03     enL1ID
I05    [054]    MC-K09     enTTC_Register[11]
I13    [055]    MC-K01     enExtRodBusy_in
I22    [067]    Pin 204    reg30

SIGNAL FANOUTS
TYPE   Sig_ID Signal Name
----   ------ -----------
OUT    [004]  db[11]
OUT    [005]  db[10]
OUT    [006]  db[9]
OUT    [007]  db[8]

ARRAY INPUTS AND CLUSTER ALLOCATION TABLES                      

   IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII    CCCCCCCCCCCCCCCC      P C S  R  S   
   0000000000111111111122222222223333 ## 0000000000111111 Pts  O L E  S  L   
MC 0123456789012345678901234567890123 AI 0123456789012345 Used L K T  T  W Node  OE   Pin
00 -x-----------x--------x-----------  3 5---------------   1  H - -- -- F [---] OE0 [007]
01 ----------------------------------  0 -5--------------   -  - - -- -- - [---] GND [---]
02 ----------------------------------  0 --5-------------   -  - - -- -- - [---] GND [---]
03 -x------------x-------x-----------  3 ---5------------   1  H - -- -- F [---] OE0 [006]
04 ----------------------------------  0 ----5-----------   -  - - -- -- - [---] GND [---]
05 -x---------------x----x-----------  3 -----5----------   1  H - -- -- F [---] OE0 [005]
06 ----------------------------------  0 ------5---------   -  - - -- -- - [---] GND [---]
07 ----------------------------------  0 -------5--------   -  - - -- -- - [---] GND [---]
08 -x---x----------------x-----------  3 --------5-------   1  H - -- -- F [---] OE0 [004]
09 ----------------------------------  0 ---------5------   -  - - -- -- - [---] GND [---]
10 ----------------------------------  0 ----------5-----   -  - - -- -- - [---] GND [---]
11 ----------------------------------  0 -----------5----   -  - - -- -- - [---] GND [---]
12 ----------------------------------  0 ------------5---   -  - - -- -- - [---] GND [---]
13 ----------------------------------  0 -------------5--   -  - - -- -- - [---] GND [---]
14 ----------------------------------  0 --------------5-   -  - - -- -- - [---] GND [---]
15 ----------------------------------  0 ---------------5   -  - - -- -- - [---] GND [---]


BLOCK 'F': POWER=HIGH
   CONTROL PTERMS:
           OE00 = dboe ;


   SIGNALS CROSS REFERENCE:

ARRAY INPUTS:
Input  Sig_ID   Source     Signal Name
-----  ------   ------     -----------
I01    [016]    MC-K14     dboe
I00    [021]    MC-I13     enSABCR2
I02    [022]    MC-J13     enSAECR2
I06    [052]    MC-K11     enTTC_Register[13]
I21    [053]    MC-J15     enTTC_Register[12]
I22    [067]    Pin 204    reg30

SIGNAL FANOUTS
TYPE   Sig_ID Signal Name
----   ------ -----------
OUT    [000]  db[15]
OUT    [001]  db[14]
OUT    [002]  db[13]
OUT    [003]  db[12]

ARRAY INPUTS AND CLUSTER ALLOCATION TABLES                      

   IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII    CCCCCCCCCCCCCCCC      P C S  R  S   
   0000000000111111111122222222223333 ## 0000000000111111 Pts  O L E  S  L   
MC 0123456789012345678901234567890123 AI 0123456789012345 Used L K T  T  W Node  OE   Pin
00 -x-------------------xx-----------  3 5---------------   1  H - -- -- F [---] OE0 [003]
01 ----------------------------------  0 -5--------------   -  - - -- -- - [---] GND [---]
02 ----------------------------------  0 --5-------------   -  - - -- -- - [---] GND [---]
03 -x----x---------------x-----------  3 ---5------------   1  H - -- -- F [---] OE0 [002]
04 ----------------------------------  0 ----5-----------   -  - - -- -- - [---] GND [---]
05 -xx-------------------x-----------  3 -----5----------   1  H - -- -- F [---] OE0 [001]
06 ----------------------------------  0 ------5---------   -  - - -- -- - [---] GND [---]
07 ----------------------------------  0 -------5--------   -  - - -- -- - [---] GND [---]
08 xx--------------------x-----------  3 --------5-------   1  H - -- -- F [---] OE0 [000]
09 ----------------------------------  0 ---------5------   -  - - -- -- - [---] GND [---]
10 ----------------------------------  0 ----------5-----   -  - - -- -- - [---] GND [---]
11 ----------------------------------  0 -----------5----   -  - - -- -- - [---] GND [---]
12 ----------------------------------  0 ------------5---   -  - - -- -- - [---] GND [---]
13 ----------------------------------  0 -------------5--   -  - - -- -- - [---] GND [---]
14 ----------------------------------  0 --------------5-   -  - - -- -- - [---] GND [---]
15 ----------------------------------  0 ---------------5   -  - - -- -- - [---] GND [---]


BLOCK 'H': POWER=HIGH
   CONTROL PTERMS:
          RST00 = /nOA_rst ;

   BLOCK CLOCKS:
      BLK_CLK 1 (PIN_CLOCK:POL=HIGH) : clk6, pin 74
      BLK_CLK 2 (PIN_CLOCK:POL=HIGH) : nLEb2, pin 83



   SIGNALS CROSS REFERENCE:

ARRAY INPUTS:
Input  Sig_ID   Source     Signal Name
-----  ------   ------     -----------
I33    [005]    Pin 34     db[10]
I22    [006]    Pin 33     db[9]
I07    [008]    Pin 16     db[7]
I01    [017]    MC-H13     enRodBusy
I17    [018]    MC-H00     enTType
I05    [019]    MC-H03     enL1ID
I24    [025]    MC-I00     nTTCout[0]
I04    [026]    MC-I10     nTTCout[2]
I20    [027]    MC-I05     nTTCout[1]
I00    [049]    MC-H07     reg_TTCout[2]
I10    [051]    MC-H15     reg_TTCout[0]
I08    [062]    Pin 206    nOA_rst
I02    [066]    Pin 149    bWriteb
I14    [067]    Pin 204    reg30
I06    [068]    Pin 203    Reg18

SIGNAL FANOUTS
TYPE   Sig_ID Signal Name
----   ------ -----------
OUT    [017]  enRodBusy
OUT    [018]  enTType
OUT    [019]  enL1ID
OUT    [020]  enBCID
OUT    [024]  nenTTCClk
OUT    [041]  idTRIG
OUT    [042]  idBCR
OUT    [043]  idECR
NODE   [049]  reg_TTCout[2]
NODE   [051]  reg_TTCout[0]

ARRAY INPUTS AND CLUSTER ALLOCATION TABLES                      

   IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII    CCCCCCCCCCCCCCCC      P C S  R  S   
   0000000000111111111122222222223333 ## 0000000000111111 Pts  O L E  S  L   
MC 0123456789012345678901234567890123 AI 0123456789012345 Used L K T  T  W Node  OE   Pin
00 --x---x-x--------x---------------x  5 5---------------   2  H 2 -- 00 F (018) VCC [018]
01 --------x-----------x-------------  2 -5--------------   1  H 1 -- 00 F (043) VCC [043]
02 -----x----------------------------  1 --1-------------   1  H - -- -- F (020) VCC [020]
03 --x--xx-x-------------x-----------  5 --45------------   2  H 2 -- 00 F (019) VCC [019]
04 --------x---------------x---------  2 ----5-----------   1  H 1 -- 00 F (041) VCC [041]
05 ----------------------------------  0 -----5----------   -  - - -- -- - [---] GND [---]
06 ----------------------------------  0 ------0---------   -  - - -- -- - [---] GND [---]
07 x-x-x---x-----x-------------------  5 ------55--------   3  L - -- -- - (049) VCC [049]
08 ----------------------------------  0 --------5-------   -  - - -- -- - [---] GND [---]
09 ----x---x-------------------------  2 ---------5------   1  H 1 -- 00 F (042) VCC [042]
10 ----------------------------------  0 ----------5-----   -  - - -- -- - [---] GND [---]
11 ----------------------------------  0 -----------5----   1  H - -- -- F (024) VCC [024]
12 ----------------------------------  0 ------------0---   -  - - -- -- - [---] GND [---]
13 -xx---xxx-------------------------  5 ------------55--   2  H 2 -- 00 F (017) VCC [017]
14 ----------------------------------  0 --------------5-   -  - - -- -- - [---] GND [---]
15 --x-----x-x---x---------x---------  5 ---------------5   3  L - -- -- - (051) VCC [051]


BLOCK 'G': POWER=HIGH
   CONTROL PTERMS:
          RST00 = /nOA_rst ;

   BLOCK CLOCKS:
      BLK_CLK 1 (PIN_CLOCK:POL=HIGH) : clk6, pin 74



   SIGNALS CROSS REFERENCE:

ARRAY INPUTS:
Input  Sig_ID   Source     Signal Name
-----  ------   ------     -----------
I13    [025]    MC-I00     nTTCout[0]
I00    [026]    MC-I10     nTTCout[2]
I25    [027]    MC-I05     nTTCout[1]
I03    [028]    MC-I11     nTTCout[3]
I26    [029]    MC-J11     nTTCout[6]
I02    [030]    MC-J08     nTTCout[7]
I01    [031]    MC-J05     nTTCout[5]
I07    [032]    MC-J03     nTTCout[4]
I08    [062]    Pin 206    nOA_rst

SIGNAL FANOUTS
TYPE   Sig_ID Signal Name
----   ------ -----------
OUT    [033]  eclL1A
OUT    [034]  eclBCR
OUT    [035]  eclECR
OUT    [036]  eclCAL
OUT    [037]  eclFER
OUT    [038]  eclSpare
OUT    [039]  eclID
OUT    [040]  eclTT

ARRAY INPUTS AND CLUSTER ALLOCATION TABLES                      

   IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII    CCCCCCCCCCCCCCCC      P C S  R  S   
   0000000000111111111122222222223333 ## 0000000000111111 Pts  O L E  S  L   
MC 0123456789012345678901234567890123 AI 0123456789012345 Used L K T  T  W Node  OE   Pin
00 --------x----------------x--------  2 1---------------   1  H 1 -- 00 F (035) VCC [035]
01 -x------x-------------------------  2 45--------------   1  H 1 -- 00 F (040) VCC [040]
02 ---x----x-------------------------  2 --5-------------   1  H 1 -- 00 F (036) VCC [036]
03 ----------------------------------  0 ---5------------   -  - - -- -- - [---] GND [---]
04 -------xx-------------------------  2 ----5-----------   1  H 1 -- 00 F (039) VCC [039]
05 x-------x-------------------------  2 -----5----------   1  H 1 -- 00 F (034) VCC [034]
06 --x-----x-------------------------  2 ------5---------   1  H 1 -- 00 F (038) VCC [038]
07 ----------------------------------  0 -------5--------   -  - - -- -- - [---] GND [---]
08 ----------------------------------  0 --------5-------   -  - - -- -- - [---] GND [---]
09 ----------------------------------  0 ---------5------   -  - - -- -- - [---] GND [---]
10 ----------------------------------  0 ----------5-----   -  - - -- -- - [---] GND [---]
11 ----------------------------------  0 -----------5----   -  - - -- -- - [---] GND [---]
12 --------x----x--------------------  2 ------------5---   1  H 1 -- 00 F (033) VCC [033]
13 ----------------------------------  0 -------------5--   -  - - -- -- - [---] GND [---]
14 --------x-----------------x-------  2 --------------5-   1  H 1 -- 00 F (037) VCC [037]
15 ----------------------------------  0 ---------------5   -  - - -- -- - [---] GND [---]


BLOCK 'I': POWER=HIGH
   CONTROL PTERMS:
          RST00 = /nOA_rst ;

   BLOCK CLOCKS:
      BLK_CLK 2 (PIN_CLOCK:POL=HIGH) : nLEb2, pin 83



   SIGNALS CROSS REFERENCE:

ARRAY INPUTS:
Input  Sig_ID   Source     Signal Name
-----  ------   ------     -----------
I31    [000]    Pin 45     db[15]
I23    [021]    MC-I13     enSABCR2
I06    [058]    MC-K08     enTTC_Register[4]
I32    [059]    MC-K07     enTTC_Register[3]
I02    [060]    MC-J01     enTTC_Register[2]
I04    [061]    MC-K06     enTTC_Register[1]
I12    [062]    Pin 206    nOA_rst
I13    [066]    Pin 149    bWriteb
I09    [068]    Pin 203    Reg18
I11    [070]    Pin 143    SATRIG
I25    [071]    Pin 136    SABCR1
I22    [072]    Pin 137    SACAL
I01    [073]    Pin 140    SAECR1
I33    [076]    Pin 138    SABCR2
I08    [077]    Pin 139    SAECR2
I24    [078]    Pin 194    L1Ain
I30    [079]    Pin 190    BCRin
I15    [080]    Pin 191    ECRin
I17    [081]    Pin 197    CALin
I19    [086]    Pin 123    seqTRIG
I28    [087]    Pin 118    seqCAL
I27    [088]    Pin 117    seqBCR
I18    [089]    Pin 119    seqECR
I03    [094]    Pin 109    TTC_ready2_6

SIGNAL FANOUTS
TYPE   Sig_ID Signal Name
----   ------ -----------
OUT    [021]  enSABCR2
OUT    [025]  nTTCout[0]
OUT    [026]  nTTCout[2]
OUT    [027]  nTTCout[1]
OUT    [028]  nTTCout[3]

ARRAY INPUTS AND CLUSTER ALLOCATION TABLES                      

   IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII    CCCCCCCCCCCCCCCC      P C S  R  S   
   0000000000111111111122222222223333 ## 0000000000111111 Pts  O L E  S  L   
MC 0123456789012345678901234567890123 AI 0123456789012345 Used L K T  T  W Node  OE   Pin
00 ---xx------x-------x----x---------  5 5---------------   3  H - -- -- F (025) VCC [025]
01 ----------------------------------  0 -5--------------   -  - - -- -- - [---] GND [---]
02 ----------------------------------  0 --5-------------   -  - - -- -- - [---] GND [---]
03 ----------------------------------  0 ---5------------   -  - - -- -- - [---] GND [---]
04 ----------------------------------  0 ----0-----------   -  - - -- -- - [---] GND [---]
05 -xxx----x------x--x---------------  6 ----55----------   3  H - -- -- F (027) VCC [027]
06 ----------------------------------  0 ------5---------   -  - - -- -- - [---] GND [---]
07 ----------------------------------  0 -------5--------   -  - - -- -- - [---] GND [---]
08 ----------------------------------  0 --------5-------   -  - - -- -- - [---] GND [---]
09 ----------------------------------  0 ---------0------   -  - - -- -- - [---] GND [---]
10 ---x---------------------x-x--x-xx  6 ---------50-----   3  H - -- -- F (026) VCC [026]
11 ------x----------x----x-----x-----  4 ----------55----   2  H - -- -- F (028) VCC [028]
12 ----------------------------------  0 ------------0---   -  - - -- -- - [---] GND [---]
13 ---------x--xx---------x-------x--  5 ------------55--   2  H 2 -- 00 F (021) VCC [021]
14 ----------------------------------  0 --------------5-   -  - - -- -- - [---] GND [---]
15 ----------------------------------  0 ---------------5   -  - - -- -- - [---] GND [---]


BLOCK 'J': POWER=HIGH
   CONTROL PTERMS:
          RST00 = /nOA_rst ;

   BLOCK CLOCKS:
      BLK_CLK 2 (PIN_CLOCK:POL=HIGH) : nLEb2, pin 83



   SIGNALS CROSS REFERENCE:

ARRAY INPUTS:
Input  Sig_ID   Source     Signal Name
-----  ------   ------     -----------
I03    [001]    Pin 44     db[14]
I24    [003]    Pin 42     db[12]
I20    [009]    Pin 15     db[6]
I04    [010]    Pin 14     db[5]
I07    [013]    Pin 5      db[2]
I05    [022]    MC-J13     enSAECR2
I21    [053]    MC-J15     enTTC_Register[12]
I28    [056]    MC-J00     enTTC_Register[6]
I06    [057]    MC-J14     enTTC_Register[5]
I16    [060]    MC-J01     enTTC_Register[2]
I18    [062]    Pin 206    nOA_rst
I02    [066]    Pin 149    bWriteb
I09    [068]    Pin 203    Reg18
I15    [074]    Pin 141    SAFER
I25    [075]    Pin 142    SASpare
I08    [082]    Pin 192    FERin
I17    [083]    Pin 195    Sparein
I00    [084]    Pin 196    TTin
I19    [085]    Pin 193    IDin
I10    [090]    Pin 120    seqFER
I01    [091]    Pin 122    seqSpare
I30    [092]    Pin 124    seqTT
I12    [093]    Pin 121    seqID

SIGNAL FANOUTS
TYPE   Sig_ID Signal Name
----   ------ -----------
OUT    [022]  enSAECR2
OUT    [029]  nTTCout[6]
OUT    [030]  nTTCout[7]
OUT    [031]  nTTCout[5]
OUT    [032]  nTTCout[4]
NODE   [053]  enTTC_Register[12]
NODE   [056]  enTTC_Register[6]
NODE   [057]  enTTC_Register[5]
NODE   [060]  enTTC_Register[2]

ARRAY INPUTS AND CLUSTER ALLOCATION TABLES                      

   IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII    CCCCCCCCCCCCCCCC      P C S  R  S   
   0000000000111111111122222222223333 ## 0000000000111111 Pts  O L E  S  L   
MC 0123456789012345678901234567890123 AI 0123456789012345 Used L K T  T  W Node  OE   Pin
00 --x------x--------x-x-------x-----  5 5---------------   2  H 2 -- 00 - (056) VCC [056]
01 --x----x-x------x-x---------------  5 -5--------------   2  H 2 -- 00 - (060) VCC [060]
02 ----------------------------------  0 --5-------------   -  - - -- -- - [---] GND [---]
03 ------------x------x--------------  2 ---5------------   1  H - -- -- F (032) VCC [032]
04 ----------------------------------  0 ----5-----------   -  - - -- -- - [---] GND [---]
05 x-----------------------------x---  2 -----5----------   1  H - -- -- F (031) VCC [031]
06 ----------------------------------  0 ------5---------   -  - - -- -- - [---] GND [---]
07 ----------------------------------  0 -------0--------   -  - - -- -- - [---] GND [---]
08 -x---------------x-------x--x-----  4 -------55-------   2  H - -- -- F (030) VCC [030]
09 ----------------------------------  0 ---------5------   -  - - -- -- - [---] GND [---]
10 ----------------------------------  0 ----------0-----   -  - - -- -- - [---] GND [---]
11 ------x-x-x----x------------------  4 ----------55----   2  H - -- -- F (029) VCC [029]
12 ----------------------------------  0 ------------0---   -  - - -- -- - [---] GND [---]
13 --xx-x---x--------x---------------  5 ------------50--   2  H 2 -- 00 F (022) VCC [022]
14 --x-x-x--x--------x---------------  5 -------------50-   2  H 2 -- 00 - (057) VCC [057]
15 --x------x--------x--x--x---------  5 --------------55   2  H 2 -- 00 - (053) VCC [053]


BLOCK 'L': UNUSED

BLOCK 'K': POWER=HIGH
   CONTROL PTERMS:
          RST00 = /nOA_rst ;

   BLOCK CLOCKS:
      BLK_CLK 2 (PIN_CLOCK:POL=HIGH) : nLEb2, pin 83



   SIGNALS CROSS REFERENCE:

ARRAY INPUTS:
Input  Sig_ID   Source     Signal Name
-----  ------   ------     -----------
I02    [002]    Pin 43     db[13]
I08    [004]    Pin 35     db[11]
I14    [007]    Pin 32     db[8]
I23    [011]    Pin 13     db[4]
I19    [012]    Pin 6      db[3]
I15    [014]    Pin 4      db[1]
I27    [015]    Pin 3      db[0]
I04    [023]    MC-K00     enTTCClk
I20    [027]    MC-I05     nTTCout[1]
I24    [028]    MC-I11     nTTCout[3]
I26    [048]    MC-K10     reg_TTCout[3]
I00    [050]    MC-K13     reg_TTCout[1]
I01    [052]    MC-K11     enTTC_Register[13]
I21    [054]    MC-K09     enTTC_Register[11]
I30    [055]    MC-K01     enExtRodBusy_in
I06    [058]    MC-K08     enTTC_Register[4]
I32    [059]    MC-K07     enTTC_Register[3]
I05    [061]    MC-K06     enTTC_Register[1]
I12    [062]    Pin 206    nOA_rst
I25    [065]    Pin 202    bReadb
I13    [066]    Pin 149    bWriteb
I22    [067]    Pin 204    reg30
I09    [068]    Pin 203    Reg18

SIGNAL FANOUTS
TYPE   Sig_ID Signal Name
----   ------ -----------
NODE   [016]  dboe
OUT    [023]  enTTCClk
NODE   [048]  reg_TTCout[3]
NODE   [050]  reg_TTCout[1]
NODE   [052]  enTTC_Register[13]
NODE   [054]  enTTC_Register[11]
OUT    [055]  enExtRodBusy_in
NODE   [058]  enTTC_Register[4]
NODE   [059]  enTTC_Register[3]
NODE   [061]  enTTC_Register[1]

ARRAY INPUTS AND CLUSTER ALLOCATION TABLES                      

   IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII    CCCCCCCCCCCCCCCC      P C S  R  S   
   0000000000111111111122222222223333 ## 0000000000111111 Pts  O L E  S  L   
MC 0123456789012345678901234567890123 AI 0123456789012345 Used L K T  T  W Node  OE   Pin
00 ----x----x--xx-------------x------  5 0-5-------------   2  H 2 -- 00 F (023) VCC [023]
01 ---------x--xxx---------------x---  5 55--------------   2  H 2 -- 00 F (055) VCC [055]
02 ----------------------------------  0 --0-------------   -  - - -- -- - [---] GND [---]
03 ----------------------------------  0 ---5------------   -  - - -- -- - [---] GND [---]
04 ----------------------------------  0 ----5-----------   -  - - -- -- - [---] GND [---]
05 ----------------------------------  0 -----0----------   -  - - -- -- - [---] GND [---]
06 -----x---x--xx-x------------------  5 -----50---------   2  H 2 -- 00 - (061) VCC [061]
07 ---------x--xx-----x------------x-  5 ------50--------   2  H 2 -- 00 - (059) VCC [059]
08 ------x--x--xx---------x----------  5 -------50-------   2  H 2 -- 00 - (058) VCC [058]
09 --------xx--xx-------x------------  5 --------50------   2  H 2 -- 00 - (054) VCC [054]
10 ------------xx--------x-x-x-------  5 ---------55-----   3  L - -- -- - (048) VCC [048]
11 -xx------x--xx--------------------  5 -----------55---   2  H 2 -- 00 - (052) VCC [052]
12 ----------------------------------  0 ------------0---   -  - - -- -- - [---] GND [---]
13 x-----------xx------x-x-----------  5 -------------5--   3  L - -- -- - (050) VCC [050]
14 ---------x------------x--x--------  3 --------------5-   2  H - -- -- - (016) VCC [016]
15 ----------------------------------  0 ---------------5   -  - - -- -- - [---] GND [---]


BLOCK 'M': UNUSED

BLOCK 'N': UNUSED

BLOCK 'P': UNUSED

BLOCK 'O': UNUSED



M4-256/128 SUCCEEDED FOR 62 FUNCTIONS

