TIM-2C PROTOTYPE MODULE SETTING-UP : ==================================== MP-UCL, 03 June 2005 NOTE 1: Default setup is indicated by '#' ======= NOTE 2: IC numbers ( Uxx ) refer to the nearest IC receiving the ======= signal selected by the link/switch etc. NOTE 3: Diagram numbers refer to the TIM-2 circuit schematics page with ======= the relevant link/switch etc - see PC3162M dated 28-02-2002 1) Set VME Base Address switches : ------------------------------- ( Diag.07 ) SW3 : sets A16 - A19 # default : SW3 = 0 SW4 : sets A20 - A23 SW4 = F SW5 : sets A24 - A27 SW5 = D SW6 : sets A28 - A31 SW6 = 0 ( this default sets the A24-A28 = 13 ie. the ROD Crate TIM Slot Geographical Address GA(4-0)* = 10010 ) 2) Set various Delay Switches : ---------------------------- NOTE 4: Note that the LEAST SIGNIFICANT DELAY BIT "A0" is the top slide ======= of the DIL switch, with the edge marked WHITE to the right. ( ie. nearest the TOP edge of the TIM-2 PCB ) The MOST SIGNIFICANT DELAY BIT "A5" is the bottom slide with the edge marked WHITE to the right. The "ON" position ( "ON" = 1 ) is with the relevant slide towards the switch edge marked marked WHITE ( ie. towards the BACKPLANE CONNECTORs of the TIM-2 PCB ). The "OFF" position ( "OFF" = 0 ) is with the relevant slide towards the unmarked ( black ) edge ( ie. towards the FRONT PANEL of the TIM-2 PCB ). Ignore any other lever markings or numbers on actual switch bodies ( eg. switches are marked 1-6 instead of 0-5 ). ( Diag.08/U57 ) SW8: TIM Setup delay DL4 # 100011 (23hex) ( Diag.08/U55 ) SW9: ROD Setup delay DL2 # 011111 ( 1f ) ( Diag.09/U66 ) SW10: Trig. Window Delay Setup(*): # 101100 ( 2c ) ( Diag.09/U67 ) SW11: Trig. Window Size Comp.(*) : # 111100 ( 3c ) (*) NOTE that the "Trigger Window" has been calibrated with respect to the clock "PCLKB" on Test Point PL126. With the above default setting of ROD SETUP delay, this "PCLKB" clock is about 11 nsec earlier then the "NIMCLKOUT" clock output on the front panel socket SK11. ( See below for calibrating to different clocks ) /cont: - 2 - "TRIGGER WINDOW" CALIBRATION PROCEDURE : ---------------------------------------- The "Trigger Window" allows you to select only those external triggers with selected timing relationship with respect to selected clock. This is useful for random triggers ( eg. from cosmics ). Please note that this feature operates on EXTERNAL TRIGGERs only. - To calibrate this feature for any particular clock, pre-select the Trigger Window and the NIM/ECL external trigger ( Register 0 Bits 6 and 9 'on' = 240 hex ). Decide to which clock and at which point of the clock chain you want to calibrate this feature - this could be outside the TIM module. Hook-up one scope probe to this point. - To observe the Trigger Window pulse, hook-up the second scope probe to U68 pin 5 on the TIM module ( see diag. 09 ). - Set WINDOW SIZE = 2 ( Register 4 Bit 1 'on' = address 8, write 2 ). Set SW11 ( Trigger Window Size Compensation ) so there is only a sharp short +ve spike on U68 pin 5. This spike must disappear when Reg.4 =0. - Set WINDOW SIZE = 10 ( Reg.4 Bit 4 'on' = address 8, write 10 ) and set SW10 ( Trigger Window Delay Setup ) so that the +ve edge of the window pulse output is coincident with the +ve edge of the selected clock. The WINDOW SIZE is valid between 0 and ~24 in steps of 0.5 nsec. This window can then be scanned over the whole of the 25 nsec clock period by the WINDOW DELAY setting ( Reg.4 Bits 8-13 = address 8, write 100 - 3000 ) /cont: - 3 - 3) 2-pin Links : ------------- ( Diag.07/U79 ) PL37 in # bypasses VME interrupt IACK daisychain out enables VME interrupt IACK daisy-chain ( Diag.07/U32 ) PL42 out # spare VME address link ( Diag.07/U32 ) PL84 in selects switch-set VME Base Address ( see par. 1 ) out # VME Base address set to VME GA(4-0)* = 10010 ( Diag.01/U78 ) PL175 in disables -5V2 DC converter out # enables -5V2 DC converter ( Diag.14/U75 ) PL173 in enables TIM_BUSY_OUT onto P3 b/plane out # disables TIM_BUSY_OUT output ( Diag.14/U75 ) PL174 in overrides P3 b/plane drivers disable by ROD_SENSE out # P3 b/plane drivers only enabled by correct ROD_SENSE ( Diag.14/U99 ) PL180 in # enables TIM-OK output onto P3 b/plane out disables TIM-OK output to P3 b/plane ( Diag.13/U98 ) PL181 in connects input clock onto the test point PL197/A out # isolates input clock from the test point PL197/A ( Diag.07/U12 ) SB1-SB10 VME Clocking Delay Line DL0 setup ==== THESE LINKS ARE ALREADY PROGRAMMED ON PCB ==== =================================================== /cont: - 4 - 4) 3-pin Links : ------------- ( Diag.15/U16 ) LK3 pins 1+2 # NIMTRIGINOUT = true 2+3 NIMTRIGINOUT = inverted LK4 pins 1+2 # NIMBUSYOUT = true 2+3 NIMBUSYOUT = inverted LK5 pins 1+2 # NIMTRIGOUT = true 2+3 NIMTRIGOUT = inverted LK6 pins 1+2 # NIMCLKOUT = true 2+3 NIMCLKOUT = inverted ( Diag.15/U24 ) LK7 pins 1+2 # RODBUSYOUT = true 2+3 RODBUSYOUT = inverted ( Diag.15/SK15) LK1 pins 2+3 # RODBUSYOUT = NIM standard 1+2 RODBUSYOUT = TTL standard ( Diag.16/U20 ) PL20 pins 2+3 # ECLBUSYOUT = BUSYOUTB 1+2 ECLBUSYOUT = MEXTBUSYOUT ( Diag.02/U39 ) PL121 pins 2+3 # sets stand-alone, internal FER = ECR pins 1+2 sets stand-alone, internal FER independent from ECR,& sets int.ECR=0 ( Diag.14/U75 ) PL172 pins 2+3 NTIMOUTEN, which enables P3 b/plane outputs, is always enabled 1+2 # NTIMOUTEN is enabled only in the correct TIM slot ( by VME GA(4-0)* = 10010 ) 5) 4-pin Links : ------------- ( Diag.15/U3 ) LK2 pins 2+3 NIMEXTBUSYIN -> EXTRODBUSYIN 1+2 # NIMEXTBUSYIN -> NIMEXTBUSY & 3+4 # plus EXTRODBUSYIN = 0 /cont: - 5 - 6) NOTE 6: The following links are DIAGNOSTIC TEST POINTS ONLY, ======= with EVERY PIN "B" CONNECTED TO GND ==== DO NOT PUT ANY LINKS BETWEEN PINS "A" and "B" ! ==== ========================================================= ( Diag.04/U54 ) PL141 - PL170 PLDs spare bus test points ( Diag.13/U98 ) PL188, PL189, PL197 Input Clock test points ( Diag.16/U19+U20 ) PL10-15 & PL47-50 TTC(x) output test points 7) NOTE 7: The following TEST POINTS can be used to set-up ======= correct timing relationships ( Diag.05/U59 ) PL132 SEQUBUSY ( SEQUENCER ) PL133 XSEQCLK1 PL134 XSEQTRIG ( Diag.12/U65 ) PL127 FIFO_L1ID_LOW(0) ( FIFO ) PL128 IDENB PL129 IDCLKB ( Diag.13/U61 ) PL126 PCLKB ( BACKPLANE ) PL185 TTCCLKB PL186 NTTCOUT(7) This version : MP-UCL, 03 Jun. 2005 Previous versions : 03 Jun. 2005 26 May 2005 01 Apr. 2005 05 Aug. 2004 16 Jul. 2004 17 Oct. 2003 29 Jul. 2003 24 Jun. 2002 10 Jun. 2002 21 Mar. 2002 30 Jan. 2002 22 Jan. 2002 07 Dec. 2001 18 Sep. 2001