"$Id: pld8.src,v 1.19 2002/07/31 20:14:04 warren Exp $
"===============================================================================
#TITLE      'ATLAS TIM  PLD8: ROD BUSY' ;
#ENGINEER   'Martin  Postranecky / Dominic A Hayes / John Lane / Matthew Warren';
#COMPANY    'University College London';
#COMMENT    '';
"===============================================================================

"$Log: pld8.src,v $
"Revision 1.19  2002/07/31 20:14:04  warren
"cosmetic
"
"Revision 1.18  2002/03/22 17:47:14  warren
"new reg clocking
"
"Revision 1.17  2002/02/11 18:34:42  warren
"Improved Rodbusy with enextrodbusy, added clock sync sparebus signals
"
"Revision 1.16  2002/01/16 16:52:27  warren
"tidied tabs
"
"Revision 1.15  2001/12/12 18:18:54  warren
"fixed changes reg reads for reg22,24
"
"Revision 1.14  2001/08/30 12:20:56  warren
"Tidied, Capitalization
"
"Revision 1.13  2001/08/08 18:42:27  warren
"and signal names case names
"
"Revision 1.12  2001/08/03 09:15:22  warren
"layout and sim
"temporarily removed extRodBusy as not impimented on TIM0
"
"Revision 1.11  2001/08/01 12:08:19  warren
"code, re-org tidy and NODE rename for legi
"stm vastly improved - continuing
"
"Revision 1.10  2001/07/23 11:18:45  warren
"renamed signals with proper polarity n prefixes and removed LOW_TRUEs
"
"Revision 1.9  2001/07/16 13:13:31  warren
"*** empty log message ***
"
"Revision 1.8  2001/06/02 13:10:44  warren
"Added extRodBusy pin and logic
"
"Revision 1.7  2001/04/25 19:04:33  warren
"Changed the logic in the self clock Regs - needs more testing!
"
"Revision 1.6  2001/04/03 15:46:02  warren
"OA_rst stuff
"



"==============================================================================
"MODS
"        yes, they are expected!
"06jun00 input RunMode added NC at moment.
"05jul00 new input vRodBusy OR'd in with the Fn AND_OR.
"Reg24 removed from this pld, and put on pld6
"21jul00 clk8 added (not used)
"11sep00 lv_recieve now low_true.
"12sep00 Regxx, nLEb2, bReadb, bWriteb now HIGH_TRUE.
"26sep00 Modified VME write structure using CLOCK_ENABLED_BY - Reg1E.
"16feb01 renamed (already commented out) Reg24 ro Reg30 - MRMW
"21Mar01 Cleaned up nOA_rst legibity (added OA_rst = /nOA_rst)
"31May01 Added extRodBusy I/P for FP daisy-chaining ROD crate BUSYs
"01Jun01 Updated Rod_Busyout to include extRodBusy.
"        Removed and or func and tidied logic
"20Jul01 Removed low trues and relabelled lv_revieve to nRodBusyb
"12Dec01 Fixed polarity problem with Reg22, Reg24 resets (they were = 0)
"        Removed extraneous(all) DEFAULT_TO 0s
"08Jan02 Added enExtRODBusy from pld6 (via pld2) 
"11Jan02 Added /runmode to rod_crate_busy_out
"25Feb02 Added new CEB leb2 logic to RegisterRodBusyMask for testing ...
"27Feb02 Added changes for new register clocking - although reg not in use

"==============================================================================
" SIGNAL DECLARATIONS
"==============================================================================

INPUT    nOA_rst;       "low_true Board reset.
NODE     OA_rst;
         OA_rst = /nOA_rst;

INPUT    clk8;          "25ns clock.

INPUT    nLEb2;         "VME Register clock.
INPUT    RunMode;


"-----------------------------------------------------------------------------
"VME
"---

INPUT    bWriteb,          "buffered VME write.
         bReadb;           "buffered VME read.


INPUT    Reg20,            "RodBusy RegSelect bit
         Reg1E;            "RodBusyMask RegSelect bit


BIPUT    db[15..0]         "VME data bus.
            ENABLED_BY dboe;

NODE     dboe;



"=============================================================================
"REGISTERS
"=============================================================================

"-----------------------------------------------------------------------------
" RegisterRodBusy with RegisterRodBusyMask
"-----------------------------------------

INPUT    nRodBusyb[21..5];    "NOTE: nRodBusyb[13] is only needed for
                              "      keeping a one name array, but is not used
                              "      it disapears at fitting

NODE     RodBusy[15..0];
         RodBusy[15..0] = [/nRodBusyb[21..14],/nRodBusyb[12..5]];

NODE     nRodBusy[15..0];
         nRodBusy[15..0] = [nRodBusyb[21..14],nRodBusyb[12..5]];

NODE     RegisterRodBusy[15..0];          "Reg20 - RodBusy Register


"*** should this be renamed? causes confusion with RodBusyModule

NODE     RegisterRodBusyMask[15..0]       "Reg1E - RodBusyMask Register
            CLOCKED_BY clk8      
            CLOCK_ENABLED_BY (Reg1E AND /nLEb2)  "*** this is a test
            RESET_BY OA_rst;

         RegisterRodBusyMask[15..0] = db[15..0];
         RegisterRodBusy[15..0] = RodBusy[15..0];



"-----------------------------------------------------------------------------
" Register 22 - RodBusyLatch - Reset by Write
"--------------------------------------------

INPUT    Reg22;

NODE     RegisterRodBusyLatch[15..0]; "ROD Busy Latch Register
NODE     reg22_rst[15..0];
NODE     r22;


         r22 = (Reg22 AND bWriteb) OR OA_rst;
         reg22_rst = [  r22, r22, r22, r22, r22, r22, r22, r22,
                        r22, r22, r22, r22, r22, r22, r22, r22 ];

         " self clocking register
         RegisterRodBusyLatch = /reg22_rst AND (RodBusy OR RegisterRodBusyLatch);



"-----------------------------------------------------------------------------
"Register 24 -- RodBusyMonitor - Reset by Write
"----------------------------------------------
"Confirms is RodBusy stays high for more than 16-31 clocks


INPUT    Reg24;

NODE     RegisterRodBusyMon[15..0]; "ROD Busy Monitor Register
                                    "Self clocking

NODE     r24;
         r24         = (reg24 AND bWriteb) OR OA_rst;

NODE     reg24_rst[15..0];
         reg24_rst = [  r24, r24, r24, r24, r24, r24, r24, r24,
                        r24, r24, r24, r24, r24, r24, r24, r24 ];


"-------------------------------------------------------------------------------

NODE     clk_div16;

NODE     clk_divider[4]
            CLOCKED_BY  clk8
            RESET_BY    OA_rst;

         clk_divider = clk_divider .+. 1;

         IF (clk_divider = 15) THEN
            clk_div16 = 1;
         ELSE
            clk_div16 = 0;
         END IF;


NODE     RBStore[15..0]
            CLOCKED_BY  clk_div16
            RESET_BY    OA_rst;

         RBStore = RodBusy;

         RegisterRodBusyMon = /reg24_rst AND (RBStore OR RegisterRodBusyMon);


NODE     RBhld15  CLOCKED_BY  clk_div16 RESET_BY nRodBusy[15] OR OA_rst;
NODE     RBhld14  CLOCKED_BY  clk_div16 RESET_BY nRodBusy[14] OR OA_rst;
NODE     RBhld13  CLOCKED_BY  clk_div16 RESET_BY nRodBusy[13] OR OA_rst;
NODE     RBhld12  CLOCKED_BY  clk_div16 RESET_BY nRodBusy[12] OR OA_rst;
NODE     RBhld11  CLOCKED_BY  clk_div16 RESET_BY nRodBusy[11] OR OA_rst;
NODE     RBhld10  CLOCKED_BY  clk_div16 RESET_BY nRodBusy[10] OR OA_rst;
NODE     RBhld09  CLOCKED_BY  clk_div16 RESET_BY nRodBusy[09] OR OA_rst;
NODE     RBhld08  CLOCKED_BY  clk_div16 RESET_BY nRodBusy[08] OR OA_rst;
NODE     RBhld07  CLOCKED_BY  clk_div16 RESET_BY nRodBusy[07] OR OA_rst;
NODE     RBhld06  CLOCKED_BY  clk_div16 RESET_BY nRodBusy[06] OR OA_rst;
NODE     RBhld05  CLOCKED_BY  clk_div16 RESET_BY nRodBusy[05] OR OA_rst;
NODE     RBhld04  CLOCKED_BY  clk_div16 RESET_BY nRodBusy[04] OR OA_rst;
NODE     RBhld03  CLOCKED_BY  clk_div16 RESET_BY nRodBusy[03] OR OA_rst;
NODE     RBhld02  CLOCKED_BY  clk_div16 RESET_BY nRodBusy[02] OR OA_rst;
NODE     RBhld01  CLOCKED_BY  clk_div16 RESET_BY nRodBusy[01] OR OA_rst;
NODE     RBhld00  CLOCKED_BY  clk_div16 RESET_BY nRodBusy[00] OR OA_rst;



   [  RBhld15, RBhld14, RBhld13, RBhld12, RBhld11, RBhld10, RBhld09, RBhld08,
      RBhld07, RBhld06, RBhld05, RBhld04, RBhld03, RBhld02, RBhld01, RBhld00
   ] = RodBusy;



"-----------------------------------------------------------------------------
"VME Reads
"---------

   IF (bReadb) THEN

      IF (Reg1E) THEN
         db[15..0]= RegisterRodBusyMask[15..0];
      ELSIF (Reg20) THEN
         db[15..0]= RegisterRodBusy[15..0];
      ELSIF (Reg22) THEN
         db[15..0]= RegisterRodBusyLatch[15..0];
      ELSIF (Reg24) THEN
         db[15..0]= RegisterRodBusyMon[15..0];
      END IF;

   END IF;

   dboe = bReadb AND (reg1E OR Reg20 OR Reg22 or Reg24);



"=============================================================================
" BUSYs
"=============================================================================


INPUT    vRodBusy;
INPUT    extRodBusyIn;
OUTPUT   fp_rod_crate_busyout,
         rod_crate_busyout;
         
INPUT    enExtRODBusy; "was sgbD[5] from pld6 via pld2


NODE     BO[15..0]; " Short for BusyOut
         BO[15..0] = RodBusy AND RegisterRodBusyMask;


OUTPUT   oa_rod_busy;  "was sgbd[4]
			oa_rod_busy = 	BO[15] OR BO[14] OR BO[13] OR BO[12] OR
                     	BO[11] OR BO[10] OR BO[09] OR BO[08] OR
                     	BO[07] OR BO[06] OR BO[05] OR BO[04] OR
                     	BO[03] OR BO[02] OR BO[01] OR BO[00];


rod_crate_busyout =  	oa_rod_busy 
							OR vRodBusy 
							OR (extRodBusyIn AND enExtRodBusy)
							;
							"OR  /runmode; -- removed for now - to allow better use at cern

fp_rod_crate_busyout = rod_crate_busyout;


"=============================================================================
"ROD Busy Module (not implimented ... may never be)
"--------------------------------------------------

OUTPUT   RBM[15..0];
NODE     RegXX;

NODE     RegisterRodBusyModule[15..0] "RodBusyModule Register, UNDEFINED yet
            CLOCKED_BY clk8
            CLOCK_ENABLED_BY ( RegXX AND /nLEb2)
            RESET_BY OA_rst;
            
         RegisterRodBusyModule[15..0] = db; 


"-----------------------------------------------------------------------------
"SPARE I/O
"---------

INPUT    sgbA[7..0];
INPUT    sgbB[7..0];
INPUT    sgbC[7..0];
INPUT    sgbD[4..2];
         "sgbD[5] now = enExtRODBusy; from pld2 declared above
         
INPUT    TIM_OK_OUT;     "was sgbD[0]
INPUT    TTC_ready_in;   "was sgbD[1]

INPUT    s7_8[7..0];
INPUT    s8_9[7..0];


"=============================================================================