"$Id: pld3.src,v 1.22 2002/05/22 11:34:43 warren Exp $
"===============================================================================
#TITLE    'TIM PLD3';
#ENGINEER 'Martin Postranecky / Dominic A Hayes / Matt Warren';
#COMPANY  'University College London';
#COMMENT  '';
"===============================================================================
"$Log: pld3.src,v $
"Revision 1.22  2002/05/22 11:34:43  warren
"nothing
"
"Revision 1.21  2002/03/22 17:40:19  warren
"new reg clocking
"
"Revision 1.20  2002/02/11 18:33:28  warren
"Added clock sync - req'd new sparebus signals
"
"Revision 1.19  2002/01/16 16:51:12  warren
"tidied up tabs, unused pins
"
"Revision 1.18  2002/01/15 10:30:52  warren
"sync: rewrote burst counter system to be much more syncronous (state
"machine added too)
"
"Revision 1.17  2001/11/27 16:47:35  warren
"added async reset of burst system by /vburstmode and tidied
"
"Revision 1.16  2001/11/14 20:11:14  warren
"minor layout
"
"Revision 1.15  2001/08/30 12:20:32  warren
"Tidied, Capitalization
"
"Revision 1.14  2001/08/08 18:40:27  warren
"signal name upper/lower case standardization
"
"Revision 1.13  2001/08/03 09:12:49  warren
"layout
"
"Revision 1.12  2001/07/27 17:40:49  warren
"fixed burst counter and assos sigs
"
"Revision 1.11  2001/07/26 15:10:03  warren
"new additions to our happy family
"
"Revision 1.10  2001/07/23 11:18:33  warren
"renamed signals with proper polarity n prefixes and removed LOW_TRUEs
"
"Revision 1.9  2001/07/19 10:44:19  warren
"removed unused spare bus lines
"
"Revision 1.8  2001/06/06 10:01:27  warren
"converted LF to CR/LF
"
"Revision 1.7  2001/05/31 17:14:55  jbl
"Remove dboe output
"
"Revision 1.6  2001/04/03 15:43:27  warren
"Changed from nOA_rst to OA_rst
"


"===============================================================================
"MODIFICATIONS
"-------------
"05apr00 intIna -> intInaBCR, intIn_c1 -> intIncRan
"        enCALBurst o/p.
"24may00 laser_inlck_state, SAClkOn i/ps added
"        RodBusyOut -> rod_crate_BusyOut, SequencerBusy -> SeqBusy,
"        MaskedExtBusy -> MExtBusyOut
"01jun00 clkInb -> clkInB1.
"05jun00 Burst_Ready connected   to BurstEnd internally. still o/p to pld2.
"        Reg22 i/p added to facilitate "TIM version" ID stored on pld.
"03jul00 SinkBusy i/p added.
"05jul00 ExtBusy now a NODE fed by OR of new i/ps Nim/eclExtBusy.
"12sep00 bWriteb and bReadb now defined HIGH TRUE like the rest of the PLDs.
"14sep00 nLEb2 clocking removed from Registers 0C, 22.
"15sep00 Reg22 -> /Reg22 because shared with LOW_TRUE enabled external register.
"20sep00 dboe sent to o/p pin for debugging.
"        db defaults to .z. instead of using dboe to .z. o/ps.
"           can't do that, so removed.
"        Can't solve without spliTTing db bus; Reg22 access removed.
"03oct00 Added CLK_EN_BY (and tidied bWriteb logic) for regs 04/06/08 - MRMW
"01Nov00 Changed BurstEnd to BurstBusy (status register bit) - JBL
"02Nov00 Tidied nOA_rst - MRMW
"06Nov00 Moved Reg22 to pld5 - MRMW
"Changed Name and address of ALL sigs etc of Reg 22 --> Reg 32. Comments below
"           too!
"21Mar01 Remove LOW_TRUE from nOA_rst, added OA_rst = /nOA_rst and replaced in
"           code
"25May01 dboe removed from o/p pin
"24Jul01 Rearanged code for legi.
"25Jul01 Removed in-out tb_clk and renamed to enBurstCnt_clk
"        Renamed nvBurstBusy to qvBurstBusy
"        Removed qvBurstBusy -- it stoped bursts if vBurstMode not reset
"27Jul01 Added  level to pulse FF on vBurstGo sync-FF train
"23Nov01 Used /vBurstMode to hold the burst-system in reset .. needs tidying
"08Jan02 Added SYNC function
"        Reworked Burst counter control for syncronicity
"        Reworked BCR gen procedure for neatness
"01Feb02 Used spare bussed to move signals to pld2 for sync-clock-selection
"08Feb02 Updated Status register with bit 13=TIM-OK
"27Feb02 Changed to new register clocking scheme

"-----------------------------------------------------------------------------


"------------------------------------------------------------------------------
"PROCEDURE SYNC
"------------------------------------------------------------------------------
"Uses a set of 3 flip-flops used to synchronise the input clock signals
"------------------------------------------------------------------------------

FUNCTION SYNC  ( INPUT signal, clk, rst);

   NODE     q1
               CLOCKED_BY clk
               RESET_BY rst;

   NODE     q2
               CLOCKED_BY clk
               RESET_BY rst;

            q1 = signal;
            q2 = q1;

   RETURN   q2;

END SYNC;



"-------------------------------------------------------------------------------
"pseudo-random binary sequence generator, kicks in when repeat trigger selected.
"CALled by Main Body.

PROCEDURE pseudo_random_generator

  (   INPUT  intTRIG_, enRandom_, OA_rst_;
      OUTPUT intInRan_  );

      NODE     sr_in,
               shift_reg_clk;

      shift_reg_clk = intTRIG_ AND enRandom_;


      NODE     sr[1..39]
                  CLOCKED_BY shift_reg_clk
                  PRESET_BY OA_rst_;

      sr_in     = sr[39] (+) sr[35]; "XOR
      sr        = [sr_in,sr[1..38]];

      intInRan_ = sr[39];

END pseudo_random_generator;



"-------------------------------------------------------------------------------
PROCEDURE BCR_generator
"synchronous 11.2456kHz generator

  (INPUT  clkInB1_, OA_rst_;
   OUTPUT intInBCR_);

   NODE   count12[12]
            CLOCKED_BY  clkInB1_
            RESET_BY    OA_rst_;

   IF (count12 = 3564) THEN  "### set rollover here (should be 3564?)
      intInBCR_ = 1;
      count12 = 0;

   ELSE
      count12 = count12 .+. 1;
      intInBCR_ = 0;

   END IF;

END BCR_generator;





"===============================================================================
"CODE
"===============================================================================


INPUT    nOA_rst;                   "Low_True Board reset.
NODE     OA_rst;
         OA_rst = /nOA_rst;

INPUT    bWriteb, bReadb;
INPUT    nLEb2, clk3;

INPUT    Reg04, Reg06,  Reg08, Reg0C; "reg32;

"INPUT    intTRIG, enint_c1,  intIn_c2, vBurstGo, vBurstMode;   "From pld2


INPUT    SinkBusy;      "from PLD7


BIPUT    db[15..0]               "VME databus
            ENABLED_BY dboe;

NODE     dboe;                   "db output enable



"Reg06 - Repeat Frequency
"--------------------------------------------------

NODE     Register06[15..0]       "Repeat Frequency
            CLOCKED_BY clk3
            CLOCK_ENABLED_BY (Reg06 AND /nLEb2)
            RESET_BY OA_rst;

OUTPUT   r[5..1],                "IntTRIG trigger freq range
         s[5..1];                "IntFER/ECR repeat frequency


"Reg08 - Window Size
"--------------------------------------------------

NODE     Register08[15..0]       "TRIG Window Size and Delay
            CLOCKED_BY clk3
            CLOCK_ENABLED_BY (Reg08 AND /nLEb2)
            RESET_BY OA_rst;


OUTPUT   ws[5..0],                  "window size
         wd[5..0];                  "window delay




"----------------------------------------------------------------

INPUT    laser_intlck_state,
         SAMode,
         RunMode,
         SAClkOn,
         TTCClkOn,
         rod_crate_BusyOut,
         TestBusyON,
         SeqBusy,
         BusyOut,
         intBusy,
         MExtBusyOut,
         eclExtBusy,
         NimExtBusy;
         
OUTPUT   SAClkON_out,
         TTCClkON_out;
         
         SAClkON_out  = SAClkON;
         TTCClkON_out = TTCClkON;
         

NODE     ExtBusy;   "also on pld2, built the same way
         ExtBusy  = NimExtBusy OR eclExtBusy;

NODE     Register0C[15..0];         "Busys & State - Read Only (no clocking)

"NODE   Register32[15..8];         "TIM VERSION. - Read Only (no clocking)




"===============================================================================
"MAIN BODY
"---------




"==============================================================================
" Burst Counter etc
"==============================================================================

NODE     Register04[15..0]       "Burst Count
            CLOCKED_BY clk3 
            CLOCK_ENABLED_BY (Reg04 AND /nLEb2)
            RESET_BY OA_rst;

         Register04[15..0] = db[15..0];



"----- Burst Counter --------------------------------------

"Generates Disable_TRIG which stops SATRIGs being emitted from PLD2.
"Includes a counter that counts SATRIGs during burst mode.


INPUT    SATRIG;     "from PLD2

INPUT    vBurstMode, "from PLD2
         vBurstGo;   "from PLD2

NODE     syncBurstGo;
         syncBurstGo = SYNC(vBurstGo, clk3, OA_rst);


NODE     enBurstCnt,
         loadBurstCnt
            DEFAULT_TO 0;

NODE     BurstCnt[15..0]
            CLOCKED_BY BurstCnt_clk
            RESET_BY OA_rst;

NODE     BurstCnt_clk;



         STATE_MACHINE  runBurst_machine
            CLOCKED_BY clk3
            RESET_BY /vBurstMode OR OA_rst;

         STATE Wait_BurstGo:
            IF syncBurstGo = 1 THEN
               GOTO Load_Counter;
            ELSE
               GOTO Wait_BurstGo;
            END IF;


         STATE Load_Counter:
            loadBurstCnt = 1;
            GOTO Start_Counter;


         STATE Start_Counter:
            enBurstCnt = 1;
            GOTO Wait_Count_Zero;


         STATE Wait_Count_Zero:
            enBurstCnt = 1;
            IF (BurstCnt = 0) THEN
               GOTO Wait_Not_BurstGo;
            ELSE
               GOTO Wait_Count_Zero;
            END IF;

         STATE Wait_Not_BurstGo:
            IF /syncBurstGo THEN
               GOTO Wait_BurstGo;
            ELSE
               GOTO Wait_Not_BurstGo;
            END IF;

         END runBurst_machine;


         IF enBurstCnt THEN
            BurstCnt = BurstCnt .-. 1; "count down
            BurstCnt_clk = SATRIG;

         ELSE
            BurstCnt = Register04;
            BurstCnt_clk = loadBurstCnt;

         END IF;


"---------------------------------------------------------
"Burst_Ready/Disable_TRIG etc


OUTPUT   Disable_TRIG;  "to PLD2
OUTPUT   enCALBurst;    "to PLD2
OUTPUT   Burst_Ready ;  "to PLD2
NODE     BurstBusy;     "Stat reg bit


         Burst_Ready  = vBurstMode AND /enBurstCnt; "busy signal to PLD2
         Disable_TRIG = Burst_Ready;   "to PLD2, Disable SATRIG.

         BurstBusy    = enBurstCnt;    "BurstBusy  bit of the Status reg
         enCALBurst   = enBurstCnt;



"===============================================================================
"Random Trigger Generator

"PLD2 signals
INPUT    intTRIG, enRandom;
OUTPUT   intInRan;

         pseudo_random_generator
           (intTRIG, enRandom, OA_rst,
            intInRan);


"===============================================================================
"TIMED BCR GENERATOR

INPUT    clkInB1; "*** may not need this is an undelayed ClkIn, why not clk3?

OUTPUT   intInBCR;   "to PLD2

         BCR_generator
           (clkInB1, OA_rst,
            intInBCR);


"----------------------------------------------------------------------
"VME access
"----------


         Register06 = db;  
         Register08 = db;  
         
         IF (bReadb) THEN         "VME READS the Registers.

            IF (Reg04) THEN
               db = Register04;

            ELSIF (Reg06) THEN
               db = Register06;

            ELSIF (Reg08) THEN
               db = Register08;

            ELSIF (Reg0C) THEN
               db = Register0C;

            END IF;
         END IF;

         dboe = bReadb AND (Reg04 OR Reg06 OR Reg08 OR Reg0C);


"--------------------------------------------------------------------------
"REPEAT FREQ SELECT OUTPUTS to programmable oscillators
"------------------------------------------------------
r[5..1] = Register06[4..0];
s[5..1] = Register06[12..8];



"--------------------------------------------------------------------------
"TRIGWIN OUTPUTS to programmable delay lines?
"--------------------------------------------
ws[5..0] = Register08[5..0];
wd[5..0] = Register08[13..8];


"--------------------------------------------------------------------------
"Status Register
"------------------------

INPUT    TIM_OK_OUT; "from pld2 via old sgbD[0]


         Register0C[15] = laser_intlck_state;
         Register0C[14] = TestBusyON;
         Register0C[13] = TIM_OK_out; "*** new
         Register0C[12] = 0;
         Register0C[11] = SAMode;
         Register0C[10] = RunMode;
         Register0C[ 9] = SAClkOn;
         Register0C[ 8] = TTCClkOn;
         Register0C[ 7] = rod_crate_BusyOut;
         Register0C[ 6] = SinkBusy;
         Register0C[ 5] = SeqBusy;
         Register0C[ 4] = BurstBusy;
         Register0C[ 3] = BusyOut;
         Register0C[ 2] = intBusy;
         Register0C[ 1] = MExtBusyOut;
         Register0C[ 0] = ExtBusy;


"-------------------------------------------------------------------------------
"SPARE I/O
"---------

"OUTPUT sgbA[7..0];
"       sgbA[0..7] = [ Disable_TRIG,  "to PLD2
"                      Burst_Ready,   "to PLD2
"                      BurstBusy,     "Stat reg bit
"                      loadBurstCnt,
"                      enBurstCnt,
"                      BurstCnt_clk,
"                      vBurstGo,
"                      syncBurstGo ];

INPUT    sgbA[7..0];     "Spare global bus A
INPUT    sgbB[7..0];     "Spare global bus B
INPUT    sgbC[7..0];     "Spare global bus C
INPUT    sgbD[4..2];
INPUT    enExtRodBusy;   "was sgbD[5]
INPUT    TTC_ready_in;   "was sgbD[1]
          "sgbD[0] now = TIM_OK_OUT defined above

INPUT    s2_3[5..0];
        "s2_3[6] now = SAClkON
        "s2_3[7] now = TTCClkON

INPUT    s3_9[7..0];     "Spare local bus


"=============================================================================== 