"$Id: pld4b.src,v 1.23 2002/10/24 15:09:41 warren Exp $
"==============================================================================
#TITLE    'ATLAS SCT TIM, PLD4b: BCID & TTID Registers';
#ENGINEER 'Martin Postranecky / Dominic A Hayes';
#COMPANY  'University College London';
#COMMENT  '';

"==============================================================================
"CVS Update Log
"==============================================================================

"$Log: pld4b.src,v $
"Revision 1.23  2002/10/24 15:09:41  warren
"Removed direct link between BCntIn and BC counter
"
"Revision 1.22  2002/10/14 15:53:44  warren
"Modified Run-mode BCntIn strobe timing -- no fix though
"
"Revision 1.21  2002/03/22 17:45:50  warren
"rework of BCID counter
"
"Revision 1.20  2002/02/11 18:33:47  warren
"Added clock sync sparebus signals
"
"Revision 1.19  2002/01/16 16:51:42  warren
"tidied tabs
"
"Revision 1.18  2001/12/19 19:40:00  warren
"Tidied
"
"Revision 1.17  2001/12/18 13:52:15  warren
"Figed timing on IDs - now use clk4
"
"Revision 1.16  2001/11/14 20:11:50  warren
"Improved timing and BCID counter rollover change
"
"Revision 1.15  2001/09/14 15:55:35  warren
"Improved timing of strobes
"
"Revision 1.14  2001/09/10 17:51:39  warren
"clocking now o idTRIG, BCID
"
"Revision 1.13  2001/08/30 12:20:42  warren
"Tidied, Capitalization
"
"Revision 1.12  2001/08/08 18:40:45  warren
"signal name upper/lower case standardization
"
"Revision 1.11  2001/08/03 09:14:05  warren
"fixed timing problems with delayedBCID and counter
"
"Revision 1.10  2001/07/23 11:18:38  warren
"renamed signals with proper polarity n prefixes and removed LOW_TRUEs
"
"Revision 1.9  2001/07/19 10:44:51  warren
"removed unused spare bus lines
"added SA mode strobes
"
"Revision 1.8  2001/06/22 13:07:48  warren
"Work on sim and func - may work!  -- questions on strobes none the less
"
"Revision 1.7  2001/06/15 17:01:42  warren
"Cleaned up code organisation
"  "Revision 1.6  2001/04/03 15:44:22  warren
"OA_rst  stuff "



"==============================================================================
"Mods Log
"==============================================================================

"14jan00 nLEb2 -> /nLEb2.
"22Mar00 regC, regD --> reg14, reg16.
"        added 4 extra bits to RegTTID.  BCID_offset as o/ps.
"16may00 removed BCID_offset register and o/ps.
"18may00 name: run -> RunMode.
"        name: TTypein -> TTIDin
"        BCntin[12] i/p inplace of BCID[12] decoding now done by pld4a/b.
"           ** NB ** clocking and enabling not complete yet.
"26may00 o/ps BC/TT_Strobe added.
"30May00 new i/p StrobeRst; where from I don't know.
"        counter clocking now IF-THEN structure.
"05jun00 Added   INPUT    idbcr, enBCID, enttype, enSABCR2;  "??? not used yet
"                OUTPUT   sabcr2;
"08jun00 name: clkC -> clk4.
"29jun00 StrobeResets FF NODEs added.
"30jun00 RegisterOffsetBCID[11..0] and OffsetBCID[11..0] deleted.
"        BCID_offset a register again (Reg14 [15..12]).
"        BCIDcounter no longer pre-loaded.
"        qxidBCR reinstated (from delayAB2)
"05jul00 Register2ATTC_BCID fed  by BCntin.
"11sep00 Regxx, nLEb2, bReadb,   bWriteb now HIGH_TRUE.
"27sep00 Default_to added to Register 2A.
"01Nov00 BCID_offset is now writable in both run/vme modes - JBL
"21Mar01 Removed LOW_TRUE from noa_rst, added oa_rst = /noa_rst & repl in code
"14Jun01 Re-organised layout and bWriteb logic
"        Register2A renamed to RegTTC_BCID
"20Jun01 Reworked BCIDcounter to ensure free running in both modes (VME/RUN)
"21Jun01 Removed most DEFAULT_TO's
"14Aug01 Renamed counterC to BCIDcounter
"10Sep01 Added clocking to idTRIG (=qidTRIG) and BCID output.
"13Sep01 BCID now clocked by /clk4
"23Oct01 Added clocking to TTC Strobes (BCntStrove, TTypeStrobe), removed
"         redundant code
"        Improved TTID_reg clocking by removing undefined states
"        Added clocking to TT_Strobe and BC_Strobe OUTPUTS
"09Nov01 Changed BCID counter wrap-around to FFFh
"20Feb02 Reworked to use single register for counter and r/wr
"25Feb02 removed bwriteb from reg write logic: It is already included in on pld1 
"15Mar02 Synced up entire idTRIG chain to ensure the output Strobes are with
"        Valid data
"        Reworked counter so that it is always on and readable via the BCID reg
"28Aug02 removed all clocking in of strobes and Data from TTCrx = it is done
"        by the registers anyway.

"==============================================================================
"CODE
"==============================================================================

INPUT    nOA_rst;          "Low_True Board reset.
VIRTUAL
NODE     OA_rst;
         OA_rst = /nOA_rst;

INPUT    clk4;

INPUT    RunMode;                   "Run mode = 1, vme mode = 0;

INPUT    bReadb;                    "Buffered VME read.
INPUT    bWriteb;                   "Buffered VME write.
INPUT    Reg14, Reg16, Reg2A;       "Register enables.
INPUT    nLEb2;                        "VME register clock.

BIPUT    db[15..0]                                 "VME databus.
            ENABLED_BY dboe;
NODE     dboe;

"------------------------------------------------------------------------------
"BCR
"----------------------------------------------

INPUT    idBCR;


"----------------------------------------------
"BCR delay (via BCID offset)

NODE     BCID_offset[3..0]
            CLOCKED_BY clk4
            CLOCK_ENABLED_BY (Reg14 AND /nLEb2)
            RESET_BY OA_rst;
         BCID_offset[3..0] = db[15..12];
         

         " delay shift register
         "----------------------
NODE     shiftidBCR[15..1]
            CLOCKED_BY clk4
            RESET_BY OA_rst;

         shiftidBCR[15..1] = [shiftidBCR[14..1], idBCR];


NODE     qxidBCR                   "delayed idBCR
            CLOCKED_BY clk4
            RESET_BY OA_rst;

         CASE (BCID_offset)
            WHEN 0  => qxidBCR = idBCR;
            WHEN 1  => qxidBCR = shiftidBCR[ 1];
            WHEN 2  => qxidBCR = shiftidBCR[ 2];
            WHEN 3  => qxidBCR = shiftidBCR[ 3];
            WHEN 4  => qxidBCR = shiftidBCR[ 4];
            WHEN 5  => qxidBCR = shiftidBCR[ 5];
            WHEN 6  => qxidBCR = shiftidBCR[ 6];
            WHEN 7  => qxidBCR = shiftidBCR[ 7];
            WHEN 8  => qxidBCR = shiftidBCR[ 8];
            WHEN 9  => qxidBCR = shiftidBCR[ 9];
            WHEN 10 => qxidBCR = shiftidBCR[10];
            WHEN 11 => qxidBCR = shiftidBCR[11];
            WHEN 12 => qxidBCR = shiftidBCR[12];
            WHEN 13 => qxidBCR = shiftidBCR[13];
            WHEN 14 => qxidBCR = shiftidBCR[14];
            WHEN 15 => qxidBCR = shiftidBCR[15];
         END CASE;



"-----------------------------------------------------
"STROBES
"-----------------------------------------------------

"Run Mode
"--------

INPUT    BCntStrobe;

NODE     qBCntStrobe
            CLOCKED_BY clk4
            RESET_BY OA_rst;
         qBCntStrobe = BCntStrobe;


"Stand-Alone Mode
"----------------

INPUT    idTRIG;

NODE     qidTRIG,
         q2idTRIG
         	CLOCKED_BY clk4
         	RESET_BY OA_rst;
         	
		 	 qidTRIG = idTRIG;
			q2idTRIG = qidTRIG; "Extra delay for BC_Strobe timing


"Both
"----
INPUT    enBCID; "from pld6

OUTPUT   BC_Strobe
            CLOCKED_BY clk4
            RESET_BY OA_rst;

         IF (RunMode) THEN
            BC_Strobe = qBCntStrobe AND enBCID;

         ELSE
            BC_Strobe = q2idTRIG AND enBCID;

         END IF;


"------------------------------------------------------------------------------
"The BCID Counter AND FIFO Output
"------------------------------------------------------------------------------


NODE     BCIDcounter[11..0]            "Reg14
            CLOCKED_BY clk4
            RESET_BY OA_rst;
            
NODE     BCIDCountMax
				DEFAULT_TO 0;
         
         
         IF (qxidBCR) THEN
         	BCIDcounter = 0;

        	ELSIF (BCIDcounter = 0fffh) THEN  "#### SET rollover here - 3563 ####
            BCIDcounter = 0;
            BCIDCountMax = 1;
            
         ELSE
            BCIDcounter = BCIDcounter .+. 1;
            
         END IF;   



"FIFO Output FF assignment
"-------------------------

INPUT    BCntIn[11..0];


OUTPUT   BCID[11..0]                         
            CLOCKED_BY clk4
            CLOCK_ENABLED_BY qidTRIG
            RESET_BY OA_rst;
                          
			BCID = BCIDcounter;


"------------------------------------------------------------------------------
"BCID Register -- Reg14
"----------------------
"reflects BCID counter at last L1A

NODE     RegBCID[11..0] "Reg2A
            CLOCKED_BY clk4
            CLOCK_ENABLED_BY qidTRIG
            RESET_BY OA_rst;
            
         RegBCID[11..0] = BCIDcounter[11..0];
       

"------------------------------------------------------------------------------
"TTC_BCID -- Reg2A
"-----------------
"reflects last BCID from TTC

NODE     RegTTC_BCID[11..0] "Reg2A
            CLOCKED_BY clk4
            CLOCK_ENABLED_BY BCntStrobe
            RESET_BY OA_rst;
            
         RegTTC_BCID[11..0] = BCntIn[11..0];


"------------------------------------------------------------------------------
"SABCR2 outputs
"------------


INPUT    enSABCR2;
OUTPUT   SABCR2;     "*** should this reset happen when the counter is FFF or 000???
         SABCR2 = BCIDCountMax AND enSABCR2;


"------------------------------------------------------------------------------
"TTID -- Reg16
"-------------

"STROBES
"------------------------------------------------------------

"Run Mode
"--------

INPUT    TTypeStrobe;


"Stand-Alone Mode
"----------------
"Done in BC section


"Both
"----
INPUT    enTType;

OUTPUT   TT_Strobe
            CLOCKED_BY clk4
            RESET_BY OA_rst;

         IF (RunMode) THEN
            TT_Strobe = TTypeStrobe AND enTType;  "clocked TTypeStrobe

         ELSE
            TT_Strobe = q2idTRIG AND enTType; "don't need q2idTRIG 
                                              " but good for uniformarty

         END IF;

"------------------------------------------------------------------------------
"The Trigger Type Register
"-----------------------------------

INPUT    TTIDin[9..0];

OUTPUT   TTID[9..0]     "Also Reg16
            CLOCKED_BY clk4
            CLOCK_ENABLED_BY ceTTID
            RESET_BY OA_rst;
            
NODE     ceTTID;


         IF (RunMode) THEN  
            TTID      = TTIDin;
            ceTTID    = TTypeStrobe;

         ELSE
            TTID      = db[9..0]; "RegTTID;
            ceTTID    = Reg16 AND /nLEb2;
         
         END IF;



"------------------------------------------------------------------------------
"VME I/O
"-------


         IF (Reg14) THEN
            db[15..12] = BCID_offset[3..0];
            db[11..0]  = RegBCID[11..0];

         ELSIF (Reg16) THEN
            db[15..10] = 0;
            db[9..0]   = TTID[9..0];

         ELSIF (Reg2A) THEN
            db[15..12] = 0;
            db[11..0]  = RegTTC_BCID[11..0]; 
            
         END IF;

         dboe = bReadb AND (Reg14 OR Reg16 OR Reg2A);


"------------------------------------------------------------------------------
" SPARE I/O
"----------

         INPUT    sgbA[7..0];    "Spare global  bus A
         INPUT    sgbB[7..0];    "Spare global  bus B
         INPUT    sgbC[7..0];    "Spare global  bus C
         INPUT    sgbD[4..2];    "Spare global  bus D
         INPUT    enExtRodBusy;  "was sgbD[5]
         INPUT    TIM_OK_OUT;    "was sgbD[0]
         INPUT    TTC_ready_in;  "was sgbD[1]

         INPUT    s4b_5[7..0];      "Spare local bus no pld3 so connect bus from
                                 "pld2 to 4a instead.
         INPUT    s4a_4b[7..0];     "Spare local bus

"==============================================================================
