TIM-3C MODULE SETTING-UP :
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MP-UCL, 09 June 2005
TIM-3C MODULE SETTING-UP :
==========================
MP-UCL, 09 June 2005
NOTE 1: Default setup is indicated by '#' ======= NOTE 2: IC numbers ( Uxx ) refer to the nearest IC receiving the ======= signal selected by the link/switch etc. NOTE 3: Diagram numbers refer to the TIM-3C version of circuit schematics ======= page with the relevant link/switch/etc-see PC3216M dated 09-11-2004
1) Set VME Base Address switches : ------------------------------- ( Diag.05 ) SW3 : sets A16 - A19 # default : SW3 = 0 SW4 : sets A20 - A23 SW4 = F SW5 : sets A24 - A27 SW5 = D SW6 : sets A28 - A31 SW6 = 0 ( this default sets the A24-A28 = 13 ie. the ROD Crate TIM Slot Geographical Address GA(4-0)* = 10010 )
2) Set various Delay Switches : ---------------------------- NOTE 4: Note that the LEAST SIGNIFICANT DELAY BIT "A0" is the top slide ======= of the DIL switch ( with the edge marked WHITE to the right ). The MOST SIGNIFICANT DELAY BIT "A5" is the bottom slide ( with the edge marked WHITE to the right ). The "ON" position ( 'ON' = 1 ) is with the relevant slide towards the switch edge marked WHITE. The "OFF" position ( 'OFF' = 0 ) is with the relevant slide towards the unmarked ( black ) edge. Ignore any other lever markings or numbers on actual switch bodies ( eg. switches are marked 1-6 instead of 0-5 ). ( Diag.07/U47 ) SW7: TIM Setup delay DL4 # 011111 ( 1f ) ( Diag.07/U46 ) SW8: ROD Setup delay DL2 # 011000 ( 18 ) ( Diag.08/U61 ) SW9: Trig. Window Setup (*): # 001000 ( 8 ) ( Diag.08/U62 ) SW10: Trig. Window Size Comp.(*) : # 001001 ( 9 ) (*) NOTE that the "Trigger Window" has been calibrated with respect to the clock "MCLK1" on Test Point PL117. With the above default setting of ROD SETUP delay, this "MCLK1" clock is about 13 nsec earlier then the "NIMCLKOUT" clock output on the front panel socket SK10. ( See below for calibrating to different clocks ).
"TRIGGER WINDOW" CALIBRATION PROCEDURE : ---------------------------------------- The "Trigger Window" allows you to select only those external triggers with selected timing relationship with respect to selected clock. This is useful for random triggers ( eg. from cosmics ). Please note that this feature operates on EXTERNAL TRIGGERs only. - To calibrate this feature for any particular clock, pre-select the Trigger Window and the NIM/ECL external trigger ( Register 0, Bits 6 and 9 'on' = 240hex ). Decide to which clock and at which point of the clock chain you want to calibrate this feature - this could be outside the TIM-3 module. Hook-up one scope probe to this point. - To observe the Trigger Window pulse, hook-up the second scope probe to U64 pin 8 on the TIM-3 module ( signal "NTRIG_WIN" - see diag.08 ). - Set WINDOW SIZE = 2 ( Register 4 Bit 1 'on' = address 8, write 2). Set SW10 ( Trigger Window Size Compensation ) so there is only a sharp short -ve spike on U64 pin 8. This spike must disappear when Reg.4 = 0. - Set WINDOW SIZE = 10 ( Reg.4 Bit 4 'on' = address 8, write 10) and set SW9 ( Trigger Window Setup ) so that the -ve edge of the window pulse output is coincident with the +ve edge of the selected clock. The WINDOW SIZE is valid between 0 and ~26 in steps of 0.5 nsec. This window can then be scanned over the whole of the 25 nsec clock period by the WINDOW DELAY setting ( Reg 4, Bits 8-13 = address 8, write 100 - 3000 ).
3) 2-pin Links : ------------- ( Diag.05/U86 ) PL164 in # bypasses VME interrupt IACK daisychain out enables VME interrupt IACK daisy-chain ( Diag.05 ) PL160 out # "B_SELECT" : spare VME Addressing link to U76 ( FPGA-1 ) pin P19 ( Diag.05 ) PL154 in selects switch-set VME Base Address ( see par. 1 ) out # VME Base address set to VME GA(4-0)* = 10010 ( Diag.01/U83 ) PL158 in disables -5V2 DC converter out # enables -5V2 DC converter ( Diag.13/U85 ) PL167 in enables TIM_BUSY_OUT onto P3 b/plane out # disables TIM_BUSY_OUT output ( Diag.13/U85 ) PL168 in overrides P3 b/plane drivers disable by ROD_SENSE out # P3 b/plane drivers only enabled by correct ROD_SENSE ( Diag.13/U89 ) PL170 in # enables TIM-OK output onto P3 b/plane out disables TIM-OK output to P3 b/plane ( Diag.12/U107) PL176 in connects input clock onto the test point PL197/A out # isolates input clock from the test point PL197/A ( Diag.05/U72 ) SB3-SB7 VME Clocking Delay Line DL0 setup
==== THESE LINKS ARE ALREADY PROGRAMMED ON PCB - DO NOT CHANGE ==== ==================================================================== ( Diag.04/U72 ) PL139 } in JTAG chain individual by-pass links ( Diag.04/U76 ) PL141 } ( Diag.04/U59 ) PL119 } out # DO NOT INSERT ANY OF THESE LINKS !! ( Diag.04/U67 ) PL123 } =================================== ( Diag.06/U67 ) PL163 in # all LV input buffers enabled out will disable all LV Input buffers for JTAG Boundary-scan testing only ( Diag.02/U76 ) PL180 in # program mode pins M0,M1, M2 of FPGA-1 PL181 in # ( default is M0=M1=M2=GND ) PL182 in # ( Diag.03/U67 ) PL183 in # program mode pins M0,M1, M2 of FPGA-2 PL184 in # ( default is M0=M1=M2=GND ) PL185 in # ( Diag.03 ) PL202 out # "F2_SPARE_LINK" : spare link to U67 ( FPGA-2 ) pin N19 ( Diag.03 ) PL203 out # "Repetitive Trigger Veto" functional in "Repetitive Trigger Veto" can be by-passed in Register 9c
4) 3-pin Links : ------------- ( Diag.14/U31 ) LK3 pins 1+2 # NIMTRIGINOUT = true 2+3 NIMTRIGINOUT = inverted LK6 pins 1+2 # NIMBUSYOUT = true 2+3 NIMBUSYOUT = inverted LK2 pins 1+2 # NIMTRIGOUT = true 2+3 NIMTRIGOUT = inverted LK5 pins 1+2 # NIMCLKOUT = true 2+3 NIMCLKOUT = inverted ( Diag.14/U32 ) LK4 pins 1+2 # RODBUSYOUT = true 2+3 RODBUSYOUT = inverted ( Diag.14/SK14) LK1 pins 2+3 # RODBUSYOUT = NIM standard 1+2 RODBUSYOUT = TTL o/c standard ( Diag.14/SK13) LK91 pins 2+3 # NIMBUSYOUT = TIM Busy Out ( NIM ) 1+2 NIMBUSYOUT = RODBUSYOUT ( NIM ) ( Diag.15/U1 ) PL41 pins 2+3 # ECLBUSYOUT = BUSYOUTB 1+2 ECLBUSYOUT = MEXTBUSYOUT ( Diag.06/U60 ) PL122 pins 2+3 # sets stand-alone, internal FER = ECR pins 1+2 sets stand-alone, internal FER independent from ECR,& sets int.ECR=0 ( Diag.13/U85 ) PL166 pins 2+3 NTIMOUTEN, which enables P3 b/plane outputs, is always enabled 1+2 # NTIMOUTEN is enabled only in the correct TIM slot ( by VME GA(4-0)* = 10010 ) ( Diag.04/U55 ) PL118 pins 2+3 selects JTAGX for loading from VME 1+2 # selects standard JTAG loading
5) 4-pin Links : ------------- ( Diag.14/U17 ) LK7 pins 2+3 NIMEXTBUSYIN -> EXTRODBUSYIN 1+2 # NIMEXTBUSYIN -> NIMEXTBUSY & 3+4 # plus EXTRODBUSYIN = 0
6) NOTE 6: The following links are DIAGNOSTIC TEST POINTS ONLY, ======= with EVERY PIN "B" CONNECTED TO GND ==== DO NOT PUT ANY LINKS BETWEEN PINS "A" and "B" ! ==== ========================================================= ( Diag.02/U76 ) PL143 - PL162 FPGA-1 debug bus test points PL186 - PL201 FPGA-1 spare bus test points ( Diag.03/U67 ) PL124 - PL140 FPGA-2 debug bus test points ( Diag.12/U107 ) PL177, PL178, PL175 Input Clock test points ( Diag.15/U1+U4 ) PL2,7,16,25,30-32,50-52 TTC(x) test points
7) NOTE 7: The following TEST POINTS can be used to set-up ======= correct timing relationships ( Diag.02/U76 ) LK45 TIMCLK1L ( FPGA-1 ) LK46 VMECLK LK47 SIGCLK ( Diag.03/U67 ) LK48 TIMCLK2L ( FPGA-2 ) LK49 TTCCLK2L LK50 VMECLK ( Diag.04/U72 ) TP1 F1_CCLK ( PROM-1 ) ( Diag.04/U59 ) TP2 F2_CCLK ( PROM-2 ) ( Diag.11/U52 ) TP3 TIMCLK3L TP4 SPARECLK2 TP5 SPARECLK1 ( Diag.12/U54 ) PL117 MCLK1 ( BACKPLANE ) ( Diag.12/U98 ) PL172 TTCCLKB PL173 NTTCOUT(7)
This version : MP-UCL, 09 Jun. 2005 Previous versions : 09 Jun. 2005 26 May 2005 29 Apr. 2005 28 Feb. 2005 25 Feb. 2005 11 Oct. 2004 05 Aug. 2004 17 Oct. 2003 21 Aug. 2003 29 Jul. 2003 25 Jul. 2003