+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Quick netlist/.ucf diff'r by Paul Mealor (mostly) compares a Cadence netlist with a Xilinx ucf +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Parms: U67 tim3c_netlist.rpt dummy.txt Comparing Cadence Netlist with Xilinx User Constraints File ----------------------------------------------------------- Checking that all pins are in both lists... Pins in Netlist missing from UCF: 1V8 - D19 D4 E18 E5 F17 F6 G15 G16 G7 G8 H16 H7 R16 R7 T15 T16 T7 T8 U17 U6 V18 V5 W19 W4 3V3 - F15 F16 F7 F8 G10 G13 G14 G17 G6 G9 H17 H6 J16 J7 K16 K7 N16 N7 P16 P7 R17 R6 T10 T13 T14 T17 T6 T9 U15 U16 U7 U8 ABL0 - Y1 ABL1 - V11 ABL10 - AB15 ABL11 - V13 ABL12 - AA14 ABL13 - V6 ABL14 - AA6 ABL15 - W6 ABL2 - W13 ABL3 - AA11 ABL4 - U13 ABL5 - AA13 ABL6 - Y13 ABL7 - Y11 ABL8 - V12 ABL9 - AB14 BCNT0 - E13 BCNT1 - A14 BCNT10 - A9 BCNT11 - A8 BCNT2 - E14 BCNT3 - C14 BCNT4 - A15 BCNT5 - B15 BCNT6 - B14 BCNT7 - D14 BCNT8 - C15 BCNT9 - F14 BCNTRES - E11 BCNTSTR - C9 BOC_LASER_STATEL - R1 BRCST2 - E9 BRCST3 - B8 BRCST4 - C8 BRCST5 - A7 BRCST6 - D8 BRCST7 - B7 BRCSTSTR1 - F10 BRCSTSTR2 - D9 BUSYOUT - C1 CLOCKL1ACCEPT - AB11 CT0 - B17 CT1 - C17 CT2 - A18 CT3 - B18 CT4 - C18 CT5 - B19 DBERRSTR - C10 DBL0 - W10 DBL1 - W11 DBL10 - V9 DBL11 - U9 DBL12 - AA9 DBL13 - AB9 DBL14 - Y7 DBL15 - AB8 DBL16 - AB6 DBL17 - Y17 DBL18 - W14 DBL19 - AA15 DBL2 - U10 DBL20 - W15 DBL21 - AB16 DBL22 - AB17 DBL23 - AA3 DBL24 - AB18 DBL25 - W5 DBL26 - AA5 DBL27 - AB5 DBL28 - Y15 DBL29 - Y5 DBL3 - Y10 DBL30 - AB4 DBL31 - AB3 DBL4 - W17 DBL5 - AB13 DBL6 - AA10 DBL7 - V10 DBL8 - Y9 DBL9 - W9 DEBUG2_BUS0 - H5 DEBUG2_BUS1 - H4 DEBUG2_BUS10 - K1 DEBUG2_BUS11 - L5 DEBUG2_BUS12 - L4 DEBUG2_BUS13 - L3 DEBUG2_BUS14 - L2 DEBUG2_BUS15 - L1 DEBUG2_BUS2 - H3 DEBUG2_BUS3 - J5 DEBUG2_BUS4 - J4 DEBUG2_BUS5 - J3 DEBUG2_BUS6 - K5 DEBUG2_BUS7 - K4 DEBUG2_BUS8 - K3 DEBUG2_BUS9 - K2 DEBUG_MODE0 - V4 DEBUG_MODE1 - V3 DEBUG_MODE2 - U3 DEBUG_MODE3 - W3 DOUT0 - F11 DOUT1 - B10 DOUT2 - D11 DOUT3 - B16 DOUT4 - C16 DOUT5 - F12 DOUT6 - E12 DOUT7 - D12 DOUTSTR - D10 DQ0 - B9 DQ1 - E10 DQ2 - A6 DQ3 - E8 ECLBCR - C4 ECLCAL - A4 ECLECR - C5 ECLEXTBUSYL - J21 ECLFER - A5 ECLL1A - D6 ECLSPARE - B5 ENINTCLK - K18 ENINTFER - T18 ENINTTRIG - V17 ENSACLK - J22 ENWINDOW - M17 EVCNTHSTR - A16 EVCNTLSTR - D15 EVCNTRES - F9 EXTCLKONL - F22 EXTINBCRECLL - H2 EXTINBCRNIML - H1 EXTINCALECLL - J2 EXTINCALNIML - J1 EXTINECRECLL - F2 EXTINECRNIML - G2 EXTINFERECLL - F1 EXTINFERNIML - G1 EXTINSPAREECLL - F4 EXTINSPARENIML - G4 EXTINTRIGECLL - F3 EXTINTRIGNIML - G3 EXTRODBUSYINL - K20 F2_CCLK - B22 F2_D0 - C22 F2_D1 - H19 F2_D2 - H20 F2_D3 - K19 F2_D4 - N17 F2_D5 - P22 F2_D6 - R19 F2_D7 - Y22 F2_DONE - W20 F2_INIT - W21 F2_PROGRAM - Y21 F2_SPARE_INL - U2 F2_SPARE_LINK - N19 F2_TCKSLR - E6 F2_TDIR - C19 F2_TDOR - A21 F2_TMSSLR - E4 FPGA2OK - V16 FPGA2_TP1 - C2 FPGA2_TP10 - Y19 FPGA2_TP11 - Y2 FPGA2_TP12 - W2 FPGA2_TP13 - W1 FPGA2_TP14 - V2 FPGA2_TP15 - E1 FPGA2_TP16 - D1 FPGA2_TP2 - D5 FPGA2_TP3 - A17 FPGA2_TP4 - A19 FPGA2_TP5 - E22 FPGA2_TP6 - F19 FPGA2_TP7 - AA20 FPGA2_TP8 - AB21 FPGA2_TP9 - AB19 GND - A1 A2 A22 AA2 AA21 AA22 AA4 AB1 AB22 B1 B2 B21 C20 C3 G11 G12 J10 J11 J12 J13 J14 J9 K10 K11 K12 K13 K14 K9 L10 L11 L12 L13 L14 L16 L7 L9 M10 M11 M12 M13 M14 M16 M7 M9 N10 N11 N12 N13 N14 N9 P10 P11 P12 P13 P14 P9 T11 T12 Y20 Y3 Y4 INTINECRL - D3 INTINFERL - D2 INTINTRIGL - E2 L1ACCEPT - C7 LASER_INTLCK_STATEL - G21 MEXTBUSYOUT - C6 NFFTV_DISABLE - P19 NIMEXTBUSYL - L20 NLED_RODBUSY10 - H21 NLED_RODBUSY11 - H18 NLED_RODBUSY12 - G20 NLED_RODBUSY13 - G18 NLED_RODBUSY14 - F18 NLED_RODBUSY15 - G22 NLED_RODBUSY16 - F20 NLED_RODBUSY17 - F21 NLED_RODBUSY18 - E19 NLED_RODBUSY19 - E20 NLED_RODBUSY20 - D20 NLED_RODBUSY21 - D21 NLED_RODBUSY5 - L19 NLED_RODBUSY6 - L18 NLED_RODBUSY7 - K17 NLED_RODBUSY8 - J19 NLED_RODBUSY9 - J20 NOA_RSTL - K21 NRODBUSYB10 - P3 NRODBUSYB11 - M5 NRODBUSYB12 - M3 NRODBUSYB13 - U4 NRODBUSYB14 - T4 NRODBUSYB15 - T3 NRODBUSYB16 - N2 NRODBUSYB17 - N1 NRODBUSYB18 - N3 NRODBUSYB19 - P1 NRODBUSYB20 - T5 NRODBUSYB21 - U1 NRODBUSYB5 - M4 NRODBUSYB6 - M2 NRODBUSYB7 - T2 NRODBUSYB8 - R3 NRODBUSYB9 - P5 NSTOP_CLK - M19 NTTCOUT0 - T1 NTTCOUT1 - N5 NTTCOUT2 - R5 NTTCOUT3 - P2 NTTCOUT4 - N4 NTTCOUT5 - N6 NTTCOUT6 - M6 NTTCOUT7 - R2 OUTTRIG - B4 PO_RESET - L17 QPLL_AUTORESTART - E17 QPLL_ERROR - J6 QPLL_EXTCONTROL - E3 QPLL_F0_SELECT0 - D16 QPLL_F0_SELECT1 - D17 QPLL_F0_SELECT2 - D18 QPLL_F0_SELECT3 - E15 QPLL_LOCKED - G5 QPLL_LVDS40_N - B11 QPLL_LVDS40_P - A12 QPLL_MODE - E16 QPLL_NRESET - F5 R1 - AB20 R2 - AA19 R3 - AA18 R4 - Y18 R5 - W18 RESETB - E7 ROD_CRATE_BUSYOUT - AB10 RUNMODE - J18 S1 - V22 S2 - W22 S3 - V21 S4 - V20 S5 - V19 SACLKONL - E21 SAMODE - J17 SCL - B3 SDA - B6 SINERRSTR - D7 SPARECLK2L - AA12 SPARE_BUS0 - Y14 SPARE_BUS1 - AA17 SPARE_BUS10 - U19 SPARE_BUS11 - T20 SPARE_BUS12 - U18 SPARE_BUS13 - T22 SPARE_BUS14 - T19 SPARE_BUS15 - T21 SPARE_BUS2 - U14 SPARE_BUS3 - Y16 SPARE_BUS4 - AA16 SPARE_BUS5 - V14 SPARE_BUS6 - V15 SPARE_BUS7 - W16 SPARE_BUS8 - U21 SPARE_BUS9 - U20 STOP_CLK - M18 SUBADDR0 - A10 SUBADDR1 - B12 SUBADDR2 - C12 SUBADDR3 - F13 SUBADDR4 - A13 SUBADDR5 - B13 SUBADDR6 - C13 SUBADDR7 - D13 TEST_SWL - K22 TIMCLK2L - A11 TIM_IDL0 - Y8 TIM_IDL1 - AA8 TIM_IDL2 - W8 TIM_IDL3 - V8 TIM_IDL4 - AA7 TIM_IDL5 - V7 TIM_IDL6 - W7 TIM_IDL7 - U11 TIM_OK_OUT - V1 TRIG_WINL - H22 TTCCLK2L - C11 TTCCLKONL - D22 TTCREADY - A3 TTC_OK - G19 UNNAMED_3_HEADER2X1_I145_B - AA1 UNNAMED_3_HEADER2X1_I146_B - U5 UNNAMED_3_HEADER2X1_I147_B - AB2 VMEBDSEL - U12 VMECLK - AB12 VMERD - N18 VMEWR - W12 WD0 - P20 WD1 - P21 WD2 - R20 WD3 - R21 WD4 - R22 WD5 - U22 WS0 - M20 WS1 - M21 WS2 - M22 WS3 - N20 WS4 - N21 WS5 - N22 Pins in UCF missing from Netlist: Checking that all pins are attached to the same net... Done!