//File: TimDefine.h #ifndef SCTPIXELROD_TIMDEFINE_H #define SCTPIXELROD_TIMDEFINE_H /*! \file * \brief TimDefine.h: An incomplete prototype definition of a TIM. * * NB define eg I_AM_LINUX_HOST for processor.h (eg typedef UINT32) * * Contributors: John Lane - originator * * $Id: TimDefine.h,v 1.5 2004/10/01 22:44:33 jbl Exp $ * * $Log: TimDefine.h,v $ * Revision 1.5 2004/10/01 22:44:33 jbl * TimModule new methods * * Revision 1.4 2003/06/04 15:04:32 tmeyer * Removed explicit directory structure from includes * * Revision 1.3 2002/12/11 21:30:49 jbl * TimModule major update * * * * Reference: http://www.hep.ucl.ac.uk/~jbl/SCT/TIM_registers.html */ namespace SctPixelRod { #include "processor.h" //! Define timing in clock cycles for SCT, Pixel is different enum TimTimingSCT { TIM_L1A_DEADTIME = 3, TIM_ECR_DEADTIME = 7, TIM_BCR_DEADTIME = 7, TIM_CAL_DEADTIME = 27, TIM_BCID_OFFSET = 6 }; const INT32 TIM_L1ID_FIRST = 0; //!< triggers /*! Sequencer RAM is 16K bytes for both source and sink memory. * They are accessed together as 16K 16-bit words. */ const INT32 TIM_SEQ_SIZE = 0x4000; //!< bytes const INT32 TIM_SEQ_ADDR = 0x8000; //!< bytes //! Define register offsets in bytes enum TimRegister { TIM_REG_ENABLES = 0x00, TIM_REG_COMMAND = 0x02, TIM_REG_BURST_COUNT = 0x04, TIM_REG_FREQUENCY = 0x06, TIM_REG_WINDOW = 0x08, TIM_REG_DELAY = 0x0A, TIM_REG_STATUS = 0x0C, TIM_REG_FIFO_STATUS = 0x0E, TIM_REG_TRIGGER_IDLO = 0x10, TIM_REG_TRIGGER_IDHI = 0x12, TIM_REG_TRIGGER_BCID = 0x14, TIM_REG_TRIGGER_TYPE = 0x16, TIM_REG_RUN_ENABLES = 0x18, TIM_REG_SEQ_CONTROL = 0x1A, TIM_REG_SEQ_END = 0x1C, TIM_REG_ROD_MASK = 0x1E, TIM_REG_ROD_BUSY = 0x20, TIM_REG_ROD_LATCH = 0x22, TIM_REG_ROD_MONITOR = 0x24, TIM_REG_TTC_DATA = 0x26, TIM_REG_TTC_SELECT = 0x28, TIM_REG_TTC_BCID = 0x2A, TIM_REG_TTC_RX = 0x2C, TIM_REG_TTC_STATUS = 0x2E, TIM_REG_OUTPUT = 0x30, TIM_REG_TIM_ID = 0x32 }; //! Define register bits as masks enum TimBitEnables { TIM_BIT_EN_INT_TRIG = 0x0002, //!< Enable internal repetitive Trigger TIM_BIT_EN_INT_ECR = 0x0004, //!< Enable internal repetitive ECReset TIM_BIT_EN_INT_BCR = 0x0008, //!< Enable internal repetitive BCReset TIM_BIT_EN_RANDOM = 0x0010, //!< Enable internal trigger randomizer TIM_BIT_EN_INT_FER = 0x0020, //!< Enable internal repetitive FEReset TIM_BIT_EN_WINDOW = 0x0040, //!< Enable trigger window TIM_BIT_EN_INT_BUSY = 0x0080, //!< Enable internal Busy TIM_BIT_EN_EXT_CLK = 0x0100, //!< Enable external inputs: clock TIM_BIT_EN_EXT_TRIG = 0x0200, //!< Enable external inputs: trigger TIM_BIT_EN_EXT_ECR = 0x0400, //!< Enable external inputs: ECReset TIM_BIT_EN_EXT_BCR = 0x0800, //!< Enable external inputs: BCReset TIM_BIT_EN_EXT_CAL = 0x1000, //!< Enable external inputs: Calibrate TIM_BIT_EN_EXT_FER = 0x2000, //!< Enable external inputs: FEReset TIM_BIT_EN_EXT_SEQ = 0x4000, //!< Enable external inputs: Sequencer Go TIM_BIT_EN_EXT_BUSY = 0x8000 //!< Enable external inputs: Busy }; //! Applies to Sequencer and Output enum TimBitBackplane { TIM_L1A = 0x01, //!< Level-1 Accept trigger TIM_ECR = 0x02, //!< Event Counter Reset TIM_BCR = 0x04, //!< Bunch Counter Reset TIM_CAL = 0x08, //!< Calibrate strobe TIM_SID = 0x10, //!< Serial event ID TIM_STT = 0x20, //!< Serial Trigger Type TIM_CMD = 0xCF, //!< Commands available TIM_RES = 0xC0, //!< Commands reserved TIM_FER = 0x40, //!< Front-End Reset - reserved TIM_SPA = 0x80, //!< Spare command - reserved TIM_TRG = 0x31 //!< Trigger and serial streams }; //! Applies to Command register enum TimBitCommand { TIM_VTRG = 0x02, //!< Single VME Trigger TIM_VECR = 0x04, //!< Single VME ECR TIM_VBCR = 0x08, //!< Single VME BCR TIM_VCAL = 0x10, //!< Single VME CAL TIM_VFER = 0x20, //!< Single VME FER TIM_VSPA = 0x40, //!< Single VME SPA TIM_BIT_EN_TTC = 0x1000, //!< Enable TTC Run Mode TIM_BIT_VRESET = 0x8000 }; enum TimBitRunEnables { TIM_BIT_EN_ID = 0x0200, TIM_BIT_EN_TYPE = 0x0400 }; enum TimBitSeqControl { TIM_BIT_SEQ_EN_ALL = 0x00FF, TIM_BIT_SEQ_RESET = 0x0200, TIM_BIT_SEQ_GO = 0x0400, TIM_BIT_EN_CYCLIC = 0x0800 }; enum TimBitTTCStatus { TIM_BIT_TTC_READY = 0x4000 }; //! Define register values as masks enum TimMaskFrequency { TIM_MASK_TRIG_600_KHZ = 0x0000, TIM_MASK_TRIG_300_KHZ = 0x0002, TIM_MASK_TRIG_200_KHZ = 0x0003, TIM_MASK_TRIG_150_KHZ = 0x0004, TIM_MASK_TRIG_120_KHZ = 0x0005, TIM_MASK_TRIG_100_KHZ = 0x0006, TIM_MASK_TRIG_60_0KHZ = 0x0001, TIM_MASK_TRIG_50_0KHZ = 0x0007, TIM_MASK_TRIG_30_0KHZ = 0x000A, TIM_MASK_TRIG_20_0KHZ = 0x000B, TIM_MASK_TRIG_15_0KHZ = 0x000C, TIM_MASK_TRIG_12_0KHZ = 0x000D, TIM_MASK_TRIG_10_0KHZ = 0x000E, TIM_MASK_TRIG_6_00KHZ = 0x0009, TIM_MASK_TRIG_5_00KHZ = 0x000F, TIM_MASK_TRIG_3_00KHZ = 0x0012, TIM_MASK_TRIG_2_00KHZ = 0x0013, TIM_MASK_TRIG_1_50KHZ = 0x0014, TIM_MASK_TRIG_1_20KHZ = 0x0015, TIM_MASK_TRIG_1_00KHZ = 0x0016, TIM_MASK_TRIG_0_60KHZ = 0x0011, TIM_MASK_TRIG_0_50KHZ = 0x0017, TIM_MASK_TRIG_0_30KHZ = 0x001A, TIM_MASK_TRIG_0_20KHZ = 0x001B, TIM_MASK_TRIG_0_15KHZ = 0x001C, TIM_MASK_TRIG_0_12KHZ = 0x001D, TIM_MASK_TRIG_0_10KHZ = 0x001E, TIM_MASK_TRIG_0_06KHZ = 0x0019, TIM_MASK_TRIG_0_05KHZ = 0x001F, TIM_MASK_FECR_60_00HZ = 0x0000, TIM_MASK_FECR_30_00HZ = 0x0200, TIM_MASK_FECR_20_00HZ = 0x0300, TIM_MASK_FECR_15_00HZ = 0x0400, TIM_MASK_FECR_12_00HZ = 0x0500, TIM_MASK_FECR_10_00HZ = 0x0600, TIM_MASK_FECR_6_000HZ = 0x0100, TIM_MASK_FECR_5_000HZ = 0x0700, TIM_MASK_FECR_3_000HZ = 0x0A00, TIM_MASK_FECR_2_000HZ = 0x0B00, TIM_MASK_FECR_1_500HZ = 0x0C00, TIM_MASK_FECR_1_200HZ = 0x0D00, TIM_MASK_FECR_1_000HZ = 0x0E00, TIM_MASK_FECR_0_600HZ = 0x0900, TIM_MASK_FECR_0_500HZ = 0x0F00, TIM_MASK_FECR_0_300HZ = 0x1200, TIM_MASK_FECR_0_200HZ = 0x1300, TIM_MASK_FECR_0_150HZ = 0x1400, TIM_MASK_FECR_0_120HZ = 0x1500, TIM_MASK_FECR_0_100HZ = 0x1600, TIM_MASK_FECR_0_060HZ = 0x1100, TIM_MASK_FECR_0_050HZ = 0x1700, TIM_MASK_FECR_0_030HZ = 0x1A00, TIM_MASK_FECR_0_020HZ = 0x1B00, TIM_MASK_FECR_0_015HZ = 0x1C00, TIM_MASK_FECR_0_012HZ = 0x1D00, TIM_MASK_FECR_0_010HZ = 0x1E00, TIM_MASK_FECR_0_006HZ = 0x1900, TIM_MASK_FECR_0_005HZ = 0x1F00 }; const int TIM_FREQ_SIZE = 29; const int TIM_TRIG_FREQUENCY[TIM_FREQ_SIZE][2] = { { TIM_MASK_TRIG_600_KHZ, 600000 }, { TIM_MASK_TRIG_300_KHZ, 300000 }, { TIM_MASK_TRIG_200_KHZ, 200000 }, { TIM_MASK_TRIG_150_KHZ, 150000 }, { TIM_MASK_TRIG_120_KHZ, 120000 }, { TIM_MASK_TRIG_100_KHZ, 100000 }, { TIM_MASK_TRIG_60_0KHZ, 60000 }, { TIM_MASK_TRIG_50_0KHZ, 50000 }, { TIM_MASK_TRIG_30_0KHZ, 30000 }, { TIM_MASK_TRIG_20_0KHZ, 20000 }, { TIM_MASK_TRIG_15_0KHZ, 15000 }, { TIM_MASK_TRIG_12_0KHZ, 12000 }, { TIM_MASK_TRIG_10_0KHZ, 10000 }, { TIM_MASK_TRIG_6_00KHZ, 6000 }, { TIM_MASK_TRIG_5_00KHZ, 5000 }, { TIM_MASK_TRIG_3_00KHZ, 3000 }, { TIM_MASK_TRIG_2_00KHZ, 2000 }, { TIM_MASK_TRIG_1_50KHZ, 1500 }, { TIM_MASK_TRIG_1_20KHZ, 1200 }, { TIM_MASK_TRIG_1_00KHZ, 1000 }, { TIM_MASK_TRIG_0_60KHZ, 600 }, { TIM_MASK_TRIG_0_50KHZ, 500 }, { TIM_MASK_TRIG_0_30KHZ, 300 }, { TIM_MASK_TRIG_0_20KHZ, 200 }, { TIM_MASK_TRIG_0_15KHZ, 150 }, { TIM_MASK_TRIG_0_12KHZ, 120 }, { TIM_MASK_TRIG_0_10KHZ, 100 }, { TIM_MASK_TRIG_0_06KHZ, 60 }, { TIM_MASK_TRIG_0_05KHZ, 50 } }; const int TIM_FECR_FREQUENCY[TIM_FREQ_SIZE][2] = { { TIM_MASK_FECR_60_00HZ, 60000 }, { TIM_MASK_FECR_30_00HZ, 30000 }, { TIM_MASK_FECR_20_00HZ, 20000 }, { TIM_MASK_FECR_15_00HZ, 15000 }, { TIM_MASK_FECR_12_00HZ, 12000 }, { TIM_MASK_FECR_10_00HZ, 10000 }, { TIM_MASK_FECR_6_000HZ, 6000 }, { TIM_MASK_FECR_5_000HZ, 5000 }, { TIM_MASK_FECR_3_000HZ, 3000 }, { TIM_MASK_FECR_2_000HZ, 2000 }, { TIM_MASK_FECR_1_500HZ, 1500 }, { TIM_MASK_FECR_1_200HZ, 1200 }, { TIM_MASK_FECR_1_000HZ, 1000 }, { TIM_MASK_FECR_0_600HZ, 600 }, { TIM_MASK_FECR_0_500HZ, 500 }, { TIM_MASK_FECR_0_300HZ, 300 }, { TIM_MASK_FECR_0_200HZ, 200 }, { TIM_MASK_FECR_0_150HZ, 150 }, { TIM_MASK_FECR_0_120HZ, 120 }, { TIM_MASK_FECR_0_100HZ, 100 }, { TIM_MASK_FECR_0_060HZ, 60 }, { TIM_MASK_FECR_0_050HZ, 50 }, { TIM_MASK_FECR_0_030HZ, 30 }, { TIM_MASK_FECR_0_020HZ, 20 }, { TIM_MASK_FECR_0_015HZ, 15 }, { TIM_MASK_FECR_0_012HZ, 12 }, { TIM_MASK_FECR_0_010HZ, 10 }, { TIM_MASK_FECR_0_006HZ, 6 }, { TIM_MASK_FECR_0_005HZ, 5 } }; } // End namespace SctPixelRod #endif // SCTPIXELROD_TIMDEFINE_H