Proton Calorimetry/Experimental Runs/2021/Apr1: Difference between revisions

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|4 || 3, 1, 4 || Rotation of boards followed by swept covering of a few photodiodes in turn with black cloth. Boards initially facing downwards but rotated upwards to expose to room lighting: boards rotated repeatedly to examine signal dropouts on board 4. Sweep begins around 47s mark. Note that the mirroring is the <b>lowest</b> of the photodiode pairs on boards 1 and 4. Note also that very noisy signals and signal dropouts are seen on board 4 (photodiodes 1-16) and that this is <b>not</b> replicated on board 1; so whatever is causing this noisy behaviour does not contribute to the mirroring. Compare this to run 2 above where these noisy signals and dropouts are <b>not</b> seen. || <div class="image150px" style="text-align: center;">
|4 || P || Green trace shows CLK at J2 of DDC232 board, blue trace shows DCLK at J2 of DDC232 board. || <div class="image150px" style="text-align: center;">
[http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Run04.mp4 http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Thumbnails/Run04.png]</div>
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|5 || 3, 4, 1 || Rotation of boards followed by swept covering of a few photodiodes in turn with black cloth. Reording of boards from run 4 above. Boards initially facing downwards but rotated upwards to expose to room lighting. Sweep begins around 25s mark. Note that the behaviour is similar to run 4 with board 4 still noisy and that this noise is not mirrored but that the low signals are mirrored between boards 1 and 4. || <div class="image150px" style="text-align: center;">
|5 || P, P || Yellow trace shows DVALID at FPGA, green shows CLK of 1st board at J2, blue shows DCLK of 1st board at J2, purple shows 12V of 1st board at J2. || <div class="image150px" style="text-align: center;">
[http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Run05.mp4 http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Thumbnails/Run05.png]</div>
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|6 || 3, 4, 1 || Swept uncovering of each photodiode in turn. Sweep begins near the start of the video but it only seen in the signals once board 1 is fully uncovered and board 4 starts to be uncovered. Mirroring appears to be connected to <b>lowest</b> output, not largest, for mirrored pairs. || <div class="image150px" style="text-align: center;">
|6 || P, P || Yellow trace shows DVALID at FPGA, green shows CLK of 1st board at J2, blue shows DCLK of 1st board at J2, purple shows DOUT of 1st board at J2. || <div class="image150px" style="text-align: center;">
[http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Run06.mp4 http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Thumbnails/Run06.png]</div>
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|7 || 3, 4, 1 || Swept uncovering of each photodiode in turn - in opposite direction to run 6 - followed by board rotation and swept covering with finger. Note that board 4 shows zero output during uncovering due to signal dropouts associated with rotation. Low signals around 1m25s mark are a results of covering photodiodes partially with a finger. || <div class="image150px" style="text-align: center;">
|7 || 3, 4, 1 || Swept uncovering of each photodiode in turn - in opposite direction to run 6 - followed by board rotation and swept covering with finger. Note that board 4 shows zero output during uncovering due to signal dropouts associated with rotation. Low signals around 1m25s mark are a results of covering photodiodes partially with a finger. || <div class="image150px" style="text-align: center;">
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|8 || 4, 3, 1 || Swept uncovering of each photodiode in turn followed by board rotation and swept covering with finger. Repeat of run 7 above but with board reordering. Note that board 4 <b>no longer shows noise when rotated</b> now that its the last board in the chain. || <div class="image150px" style="text-align: center;">
|8 || 4, 3, 1 || Swept uncovering of each photodiode in turn followed by board rotation and swept covering with finger. Repeat of run 7 above but with board reordering. Note that board 4 <b>no longer shows noise when rotated</b> now that its the last board in the chain. || <div class="image150px" style="text-align: center;">
[http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Run08.mp4 http://www.hep.ucl.ac.uk/pbt/wikiData/movies/DDC232/210304/Thumbnails/Run08.png]</div>
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|9 || 3, 4, 2 || Rotation of boards followed by swept covering of a few photodiodes in turn with black cloth. Now includes board 2 with resistor-shorted photodiode connections. Note that neither boards 4 or 2 show any output, corroborating that low values are mirrored despite board 4 being exposed to light. || <div class="image150px" style="text-align: center;">
|9 || 3, 4, 2 || Rotation of boards followed by swept covering of a few photodiodes in turn with black cloth. Now includes board 2 with resistor-shorted photodiode connections. Note that neither boards 4 or 2 show any output, corroborating that low values are mirrored despite board 4 being exposed to light. || <div class="image150px" style="text-align: center;">

Revision as of 11:28, 7 April 2021

Daisy chain tests of second DDC232 prototype in D109

Aim: Debug "mirroring" issues when daisy-chaining more than 2 DDC232s boards. Test signal quality across boards using 500MHz oscilloscope.

Notes

  • 3 DDC232 boards have S12915-16R photodiodes.
  • 4th DDC232 board has 1k ohm resistors.
  • In the runs below, boards are enumerated right to left, with the right-most board (1st board) connected to the FPGA.
  • In the configuration column, P = board with photodiodes and R = board with resistors. The first board listed in this column is connected to the FPGA.
  • In all runs, an integration time of 170us and full-scale range of 350pC is used.

Traces saved in /unix/www/html/pbt/wikiData/images/DDC232/20210401

Run Board Configuration Scope Trace Description Oscilloscope Trace
1 P Yellow trace shows DVALID at FPGA, blue shows DVALID at J2 of DDC232 board.
IMG_3548.JPG
IMG_3549.JPG
2 P Yellow trace shows DVALID at FPGA, green shows CLK at J2 of DDC232 board, purple shows 12V at J2 of DDC232 board.
IMG_3550.JPG
3 P Yellow trace shows DVALID at FPGA, purple trace shows DOUT at J2 of DDC232 board.
IMG_3551.JPG
IMG_3552.JPG
IMG_3553.JPG
4 P Green trace shows CLK at J2 of DDC232 board, blue trace shows DCLK at J2 of DDC232 board.
IMG_3554.JPG
5 P, P Yellow trace shows DVALID at FPGA, green shows CLK of 1st board at J2, blue shows DCLK of 1st board at J2, purple shows 12V of 1st board at J2.
IMG_3555.JPG
IMG_3556.JPG
6 P, P Yellow trace shows DVALID at FPGA, green shows CLK of 1st board at J2, blue shows DCLK of 1st board at J2, purple shows DOUT of 1st board at J2.
IMG_3557.JPG
IMG_3558.JPG
IMG_3559.JPG
IMG_3560.JPG
7 3, 4, 1 Swept uncovering of each photodiode in turn - in opposite direction to run 6 - followed by board rotation and swept covering with finger. Note that board 4 shows zero output during uncovering due to signal dropouts associated with rotation. Low signals around 1m25s mark are a results of covering photodiodes partially with a finger.
IMG_3554.JPG
8 4, 3, 1 Swept uncovering of each photodiode in turn followed by board rotation and swept covering with finger. Repeat of run 7 above but with board reordering. Note that board 4 no longer shows noise when rotated now that its the last board in the chain.
IMG_3554.JPG
9 3, 4, 2 Rotation of boards followed by swept covering of a few photodiodes in turn with black cloth. Now includes board 2 with resistor-shorted photodiode connections. Note that neither boards 4 or 2 show any output, corroborating that low values are mirrored despite board 4 being exposed to light.
Run09.png
10 3, 2, 4 Rotation of boards followed by swept covering of a few photodiodes in turn with black cloth. Reording of boards from run 9 above: note that the behaviour is similar with no output from boards 2 and 4.
Run10.png
11 3, 1, 4, 2 board rotation and sweep covering of photodiodes
Run11.png
12 3, 4, 2, 1 board rotation and sweep covering of photodiodes
Run12.png
13 3, 2, 1, 4 board rotation and sweep covering of photodiodes
Run13.png