Proton Calorimetry/Meetings/2021/01/06: Difference between revisions

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=== [[ELogs/SaadShaikh|Saad Shaikh]] ===
=== [[ELogs/SaadShaikh|Saad Shaikh]] ===
*
*Tested daisy-chaining 2nd DDC232 board prototype, discussed results in [http://www.hep.ucl.ac.uk/pbt/wikiData/presentations/2021/SS210106_DDC232V2.pptx this presentation].
**Daisy-chain works with 2 boards but not 3 or 4. Observe strange correlation/mirroring of readings across 2nd and 3rd boards in the chain. Unclear why this occurs but determined that this is a circuit board issue rather than FPGA/PC issue.
**Will test daisy-chain with slower DCLK and in test mode to see if situation improves. Will also saturate photodiodes one-by-one to better understand which channels are "linked".
**Will likely need to contact Texas Instruments to ask why this might occur before discussing with Marko.
*Debugged USB interface – now correctly sends data.
**Need to optimise speed further: FPGA write timing and C++ read timing. Latter will be more important.
*Laptop should arrive at UCL this week! :)


=== [[ELogs/FernPannell|Fern Pannell]] ===
=== [[ELogs/FernPannell|Fern Pannell]] ===

Revision as of 17:25, 6 January 2021

Minutes for UCL Proton Calorimetry Meetings, 6th January

Present

Raffaella Radogna, Saad Shaikh, Fern Pannell

Raffaella Radogna

Saad Shaikh

  • Tested daisy-chaining 2nd DDC232 board prototype, discussed results in this presentation.
    • Daisy-chain works with 2 boards but not 3 or 4. Observe strange correlation/mirroring of readings across 2nd and 3rd boards in the chain. Unclear why this occurs but determined that this is a circuit board issue rather than FPGA/PC issue.
    • Will test daisy-chain with slower DCLK and in test mode to see if situation improves. Will also saturate photodiodes one-by-one to better understand which channels are "linked".
    • Will likely need to contact Texas Instruments to ask why this might occur before discussing with Marko.
  • Debugged USB interface – now correctly sends data.
    • Need to optimise speed further: FPGA write timing and C++ read timing. Latter will be more important.
  • Laptop should arrive at UCL this week! :)

Fern Pannell