Proton Calorimetry/Meetings/2021/04/14: Difference between revisions
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== Minutes for UCL Proton Calorimetry Meetings, | == Minutes for UCL Proton Calorimetry Meetings, 14th April == | ||
=== Present === | === Present === | ||
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*Tested UCLH beam test setup at UCL with Simon. | *Tested UCLH beam test setup at UCL with Simon. | ||
**Will prepare wiki page ahead of experiment. | **Will prepare wiki page ahead of experiment. | ||
**Will add destination file path/name for FTDI script | |||
**Will prepare script to "replay" previously acquired measurement either by stepping through every measurement at specified frame rate or by averaging a certain number of measurements based on the integration time and refresh rate, like in a real acquisition. | **Will prepare script to "replay" previously acquired measurement either by stepping through every measurement at specified frame rate or by averaging a certain number of measurements based on the integration time and refresh rate, like in a real acquisition. | ||
*Met with Matt Warren who suggested some better practice associated with FPGA signals being used in two clock domains. | *Met with Matt Warren who suggested some better practice associated with FPGA signals being used in two clock domains. | ||
**Will work on this in down-time. | **Will work on this in down-time. | ||
Latest revision as of 13:33, 21 April 2021
Minutes for UCL Proton Calorimetry Meetings, 14th April
Present
Simon Jolly, Raffaella Radogna, Saad Shaikh, Fern Pannell
Saad Shaikh
- Wrote experiment page for tests at UCL on April 1st with DDC232 and oscillscope.
- Standardised file format and location to allow ROOT plotting and web GUI to work at the same time.
- Tested UCLH beam test setup at UCL with Simon.
- Will prepare wiki page ahead of experiment.
- Will add destination file path/name for FTDI script
- Will prepare script to "replay" previously acquired measurement either by stepping through every measurement at specified frame rate or by averaging a certain number of measurements based on the integration time and refresh rate, like in a real acquisition.
- Met with Matt Warren who suggested some better practice associated with FPGA signals being used in two clock domains.
- Will work on this in down-time.