Proton Calorimetry/Meetings/2021/05/12

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(Created page with "== Minutes for UCL Proton Calorimetry Meetings, 12th May == === Present === '''Simon Jolly''', '''Raffaella Radogna''', '''Saad Shaikh''' === Saad Shaikh ...")
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=== [[ELogs/SaadShaikh|Saad Shaikh]] ===
=== [[ELogs/SaadShaikh|Saad Shaikh]] ===
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*Discussed with Marko aspects of design of next DDC232 board: FPGA-DDC232 connection, power supplies, etc.
 +
**Marko making good progress on daisy-chain issues.
 +
**Design of rev. C DDC232 board can start.
 +
**Will ask Matt/Erdem about dual-PMOD vs. FMC connection.
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*Finished analysis of UCLH test beam, uploaded results to [http://www.hep.ucl.ac.uk/pbt/wiki/Proton_Calorimetry/Experimental_Runs/2021/Apr15 experiment page].
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*Added option to replay script to replay measurement with background subtraction and calibration.
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*Consolidating CMOS analysis code to work with both HIT and UCLH with minimal overhead.
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**Porting analysis routines from old Eclipse setup.
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*Updated [http://www.hep.ucl.ac.uk/pbt/wiki/Proton_Calorimetry/Detector_Analysis detector analysis page] with information on current photodiode analysis routines.
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*Will investigate reading from too many boards, compiling FPGA

Revision as of 13:33, 12 May 2021

Minutes for UCL Proton Calorimetry Meetings, 12th May

Present

Simon Jolly, Raffaella Radogna, Saad Shaikh

Saad Shaikh

  • Discussed with Marko aspects of design of next DDC232 board: FPGA-DDC232 connection, power supplies, etc.
    • Marko making good progress on daisy-chain issues.
    • Design of rev. C DDC232 board can start.
    • Will ask Matt/Erdem about dual-PMOD vs. FMC connection.
  • Finished analysis of UCLH test beam, uploaded results to experiment page.
  • Added option to replay script to replay measurement with background subtraction and calibration.
  • Consolidating CMOS analysis code to work with both HIT and UCLH with minimal overhead.
    • Porting analysis routines from old Eclipse setup.
  • Updated detector analysis page with information on current photodiode analysis routines.
  • Will investigate reading from too many boards, compiling FPGA
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