UCL Zeus Z System
Technical contents:
Preface
This note describes the registers of the Local and Master Timing
Controllers (LTC and MTC) for the Z / Trigger system of the ZEUS CTD.
It is based on Martin Postranecky's data sheets (25 March 1991 and updates).
It is still in preparation and is intended as a specification.
The registers are the interface with software running on a
Read Out Controller (ROC).
Introduction
The Timing Controllers have the following functions :
- control the pipeline and buffers of the front-end electronics
- synchronize the system
- interface with the Global First Level Trigger (GFLT)
- interface with data acquisition software and run control.
The readout of the data is done in three stages :
- Data into pipeline memory to await an event trigger decision.
The LTC pipeline address generators are clocked synchronously
every 48 ns (twice every bunch crossing).
The pipeline cycling address is reset to zero by Bunch Crossing
Zero from the GFLT every 220 bunch crossings (440 addresses).
The BUSY is off meaning that the system is ready for a trigger.
The pipeline is in Random Access Memories ('1K' RAMs).
- Data transfer from pipeline to buffer memory.
On receipt of a trigger (FLT Accept) the LTCs 'stop' the pipeline
and copy the relevant window of the pipeline to a buffer.
This pipeline readout is in parallel across all slots in a crate.
Stopping the pipeline means that writing data into the pipeline is
disabled while it is being read, but the pipeline cycling address for
writing continues clocking to maintain Bunch Crossing Number integrity.
The BUSY is on meaning that the system is not ready for a trigger
and incurring deadtime. The event buffers are in Dual Port Memories
(2K DPMs) which are read out by a ROC.
- Data readout from buffers by the readout transputer.
In a normal data-taking run the interaction between the electronics
and the software occurs through the LTC Interrupt register.
Bits are set by the LTC and cleared by the data acquisition software.
Each event buffer is associated with a bit in the Interrupt register.
When an event is validated (i.e. not Aborted) the LTC sets the bit.
This is usually synchronous between all LTCs in the system.
The bit is cleared on each LTC by a ROC when it has read out that
buffer in all slots of its crate. This is asynchronous between LTCs.
If all the buffers become full in any crate the LTC BUSY remains on
until its ROC releases the next buffer.
Buffers are required to reduce the deadtime because synchronization
is lost as control passes to the data acquisition software.
The Z-LTC can buffer 10 events which is the same as the FADC system.
The following is divided into two parts:
summary lists and a detailed description.
The LTC and MTC registers are very similar and they are covered together.
Byte addresses in hexadecimal (HEX) are used throughout.
The standard setting of the switches for normal running is assumed.
System Synchronization
The Z / Trigger system consists of 16 Z / Trigger crates
and 2 RBOX crates containing the MTC, FANOUT and RFLT.
Synchronization is required if the same time-zero
is to be applied throughout the system.
The position of data in memory is the thing to consider
and for overall operation it is the DPM buffers that matter.
The synchronization of the pipeline and the window copied to a buffer
are different questions :
- The window transferred from pipeline to buffer memory
is determined by the arrival time of the Trigger (FLT Accept)
at the LTC pipeline address generators,
and not the GFLT Bunch Crossing Number (GBCN).
- The setting to zero of the pipeline address
is determined by the arrival time of Bunch Crossing Number Zero (BCN0)
at the LTC pipeline address generators.
It follows that synchronization of the system can be seen differently :
- When the pipeline data is written by the ROC
synchronization is seen relative to the pipeline address.
The window copied is determined by the Trigger time
and is seen relative to the pipeline address.
- When the pipeline data is from in-coming pulses
synchronization is seen relative to the arrival time of the pulses.
The window copied is determined by the Trigger time
and is seen relative to the time of the pulses.
Ideally, pipeline addresses and the Trigger Address register
should be the same in all crates. But if they are different,
the correct window may still be copied for normal data-taking,
even though it would be wrong for testing.
Z - LTC and MTC Register Summary
The LTC and MTC registers are very similar and the following covers both.
Byte addresses in HEX are used throughout.
Addr Bits Name Description
LTC MTC
00 R 16 Serial Number Identify each card
04 RW 8 14 Control Status Operation modes & faults
08 RW 14 16 Interrupt Interrupt bits for ROC
0C RW 14 16 Interrupt Mask Enable interrupt bits
10 RW 8 Command Control operation
14 R 4 Buffer Count Current DPM buffer number
18 R 10 Pipeline Count Count 48ns clock pulses
1C R 10 Trigger Address Pipeline address on Trigger
20 R 10 End Copy Address Pipeline address on Copy Complete
24 RW 10 Countdown Clock pulses to trigger
28 R 16 Current State Status information bits
2C RW 10 MINUS Jumpback Pipeline Jumpback to Copy Window
30 RW 10 Window End Copy Window to DPM buffer
34 RW 10 Pipeline End Pipeline wrap round address
38 R - 20 LTC BUSY BUSY bit for each LTC
3C RW - 20 LTC Mask Enable BUSY bits
40 RW 24 DPM info 0 Trigger information for each buffer
44 RW 24 DPM info 1 .
48 RW 24 DPM info 2 .
4C RW 24 DPM info 3 .
50 RW 24 DPM info 4 .
54 RW 24 DPM info 5 .
58 RW 24 DPM info 6 .
5C RW 24 DPM info 7 .
60 RW 24 DPM info 8 .
64 RW 24 DPM info 9 .
- Addr
- Byte address in HEX on the backplane (note that A0 is zero)
- R
- Read access from the ROC
- W
- Write access from the ROC
- Bits
- Number of bits used by LTC / MTC (starting from the LSB)
( - means MTC only register, blank means MTC same as LTC)
- LSB
- Least Significant Bit
Register addressing
The ROC can access the LTC and MTC registers as 16-bit or 32-bit words.
Each register is allocated a 32-bit word of address space,
although in most cases less than 16 bits are used.
Address lines A2 to A6 only are decoded with the following consequences :
- the address space wraps round,
eg. the Serial Number register is also at byte address 3000 as required
- registers with 16 bits or less appear twice as consecutive 16-bit fields.
Address line A1 is used to make two different 16-bit fields for :
- registers with more than 16 bits (address 38 onwards and CSR)
- writing to the Control Status register (CSR).
The byte selector A0 is not on the backplane because it is always zero.
Control Status register bits (address 04)
bit Name Description
LSB 0 R Power Off Loss of +5V supply
1 RSC MTC Control Request by ROC for Control by MTC / GFLT
2 RSC ROC Control Request by ROC for Control by ROC
3 RSC Pause Mode Stop Clock on Trigger
4 RsC ROC Pipeline Freeze 'Freeze' pipeline on Trigger until ROC ready
5 RsC End Of Run Return to Available state when ROC ready
6 R BCN0 Fault Pipeline synchronization mismatch
7 R Clock Fault Clock or counter not running
8 R Command Fault MTC A Command occured in the wrong state
9 R Next Buffer Full MTC An LTC had Next Buffer Full
10 R LTC BCN0 Fault MTC An LTC had BCN0 Fault
11 R LTC Clock Fault MTC An LTC had Clock Fault
12 R LTC Reset MTC An LTC was RESET
13 R PLL Fault MTC A PLL Fault ( Phase Locked Loop output
48NSCK not locked to input
96NSCK )
17 R SW1 A Switch : Pipeline Cycle
18 R SW1 B Switch : Crystal Clock
19 R SW1 C Switch : Data Transfer
20 R SW1 D Switch : Clock Select
22 C BCN0 Fault Clear fault bit
23 C Clock Fault Clear fault bit
24 C Command Fault MTC Clear fault bit
25 C Next Buffer Full MTC Clear fault bit
26 C LTC BCN0 Fault MTC Clear fault bit
27 C LTC Clock Fault MTC Clear fault bit
28 C LTC Reset MTC Clear fault bit
29 C Reserved MTC Clear fault bit
MTC : bit is on MTC only
R : Read access from the ROC
S : Set access from the ROC
C : Clear access from the ROC
This register uses address line A1 for a special purpose :
to create two different 16-bit write fields.
- At address 04
- the ROC can set or clear bits 1 - 5 (except, for the LTC,
bits 4 and 5 cannot be set when it is under MTC Control)
Bits 0 and 6 onwards are read only.
- At address 06
- the ROC can clear, but not set, bits 6 onwards.
Bits 0 - 3 are read only.
Interrupt and Interrupt Mask register bits (addresses 08 and 0C)
Note that the interrupt bits are only cleared by the ROC.
bit Name Description
LSB 0 BUSY Internal BUSY (as under MTC Control)
1 DPM valid 0 Event validation for each buffer
2 DPM valid 1 .
3 DPM valid 2 .
4 DPM valid 3 .
5 DPM valid 4 .
6 DPM valid 5 .
7 DPM valid 6 .
8 DPM valid 7 .
9 DPM valid 8 .
10 DPM valid 9 .
11 Trigger Trigger occured (any source)
12 Copy Complete Pipeline Copy occured
13 Initialise Pipeline initialisation occured
MTC only...
14 Fault Fault bit(s) set in CSR
15 Error Fatal Error sent to GFLT
Interrupt register : the ROC can clear any bit, but cannot set bits.
Interrupt Mask register : the ROC can set or clear any bit.
Command register bits (address 10)
bit Name Description
LSB 0 Initialise Pipeline synchronization
1 Trigger (L-H-L) 'Stop' pipeline and Copy to buffer
2 Test Enable Start calibration sequence
3 Abort Abort Trigger
4 Reset RESET whole card
5 Start Clock Start XTAL clock running
6 Stop Clock Stop XTAL clock running
7 Single Step One XTAL clock pulse only
Not under MTC Control : the ROC can set or clear any bit.
Under MTC Control : the ROC can set or clear bits 4 - 7 only.
Current State register bits (address 28)
bit LTC name MTC name
LSB 0 LTC BUSY MTC BUSY
1 Stand By Stand By
2 Available Available
3 Initialise Initialise
4 Ready Ready
5 Copy pipeline Accept
6 Wait for Buffer MTC BUSY Stand By
7 Wait for Valid MTC BUSY Initialise
8 Wait for ROC MTC BUSY Accept
9 XTAL clock running XTAL clock running
10 MTC clock running GFLT clock running
11 Pipeline running Pipeline running
12 Copy running Copy running
13 ROC in Control ROC in Control
14 MTC in Control GFLT in Control
15 MTC Request LTC BUSY
This register is read only : the ROC cannot set or clear bits.
DPM info register bits (addresses 40 to 64)
bits Description
0 - 7 First Level Trigger Number (FLTN)
8 - 15 GFLT Bunch Crossing Number (GBCN)
16 - 17 Readout Type - system control : value 0 = Normal Trigger
1 = Off Beam Trigger
2 = Test Trigger
3 = Initialise
18 - 19 Readout Type - crossing ambiguity
20 Readout Type - component dependent
21 Readout Type - component dependent
22 Readout Type - component dependent : ROC Pipeline Freeze
23 Empty Bunch Indicator
The ROC can access this register as one 32-bit word or two 16-bit words.
The ROC can set or clear any bit.
The ROC also has read / write access to 24-bit words at addresses 68 - 7C
but the LTC and MTC do not use this memory.
Z - LTC and MTC Register Details
Under MTC Control is used to mean either an LTC being controlled by an MTC,
or an MTC running under the GFLT and controlling the system.
Under ROC Control is used to mean an LTC or MTC being controlled by a ROC.
They are also known as RUN MODE and stand-alone TEST MODE respectively.
The following registers should be downloaded in the Stand By state by the ROC :
Interrupt Mask
MINUS Jumpback (Note: it is pipeline length minus the Jumpback)
Window End
Pipeline End
LTC mask (MTC register only)
In addition the Interrupt register should be zeroed in the Stand By state
by the ROC.
In a normal data-taking run the event related information to be read is :
DPM valid 0 - 9 bits in the Interrupt register
DPM info 0 - 9 registers and associated front-end buffers.
Several events could occur between reads of e.g. Trigger Address.
Also these other registers can change value while being read.
Serial Number register (address 00)
Identify each card by type of module and identification number.
See note SerialNo.TXT by P.D.Shield 11 June 1991.
The Serial Number register is also at byte address 3000 as required.
The data is made up of two bytes :
bits 0 - 7 Module Type
bits 8 - 15 Serial Number
Control Status register (CSR) (address 04)
Controls the mode of operation and indicates faults.
Bits 1 - 5 are control bits set by the ROC
(bits 4 & 5 are set by the MTC in the case of LTC under MTC Control).
The others are status bits. The Fault bits are set when a fault occurs and
once on they stay on until cleared by the ROC (or RESET or start of Run).
Note: Bits 6+ are read only at address 04 and are clearable at address 06
(this is to avoid contention with the MTC). Bit 0 is read only.
bit 0 Power Off
Loss of +5V supply causes backplane to float high from termination.
bit 1 MTC Control
Request by ROC for Control by MTC / GFLT.
Enter Available state (BUSY off).
Clearing this bit is Release to the Stand By state.
Obeyed in the Stand By or Available states.
Under MTC Control (only) the BUSY goes off
when the crate is ready for an FLT Accept.
MTC Control should therefore only be requested after
downloading etc. of the crate has been completed.
bit 2 ROC Control
Request by ROC for Control by ROC.
Enter Available state (BUSY always on).
Clearing this bit is Release to the Stand By state.
Obeyed in the Stand By or Available states.
bit 3 Pause Mode
Stop Clock on Trigger (or countdown).
When a Trigger occurs (or countdown complete) the clocks are stopped.
After Start Clock the current state is Copy Pipeline.
This mode is ignored when under MTC Control.
bit 4 ROC Pipeline Freeze
'Freeze' pipeline on Trigger until the ROC is ready.
When a Trigger occurs the disabling of pipeline writing is extended
until the ROC says it is ready by clearing this bit on its LTC.
This allows the ROC to read the whole pipeline, check the LTC copy
or do what it likes.
The operation of this bit is different between LTC and MTC :
LTC : Clearing the bit re-enables pipeline writing and allows
the BUSY to go off and the Ready state to be entered.
The bit is set by the ROC when under ROC Control and
the bit is set by the MTC when under MTC Control.
MTC : The bit is set and cleared by the ROC to turn this mode
on and off for all LTCs (even when running under the GFLT).
ROC Pipeline Freeze is also activated by the most significant bit
of the Readout Type when running under the GFLT.
bit 5 End Of Run
Return to Available state when ROC ready.
The operation of this bit is different between LTC and MTC :
LTC : Clearing the bit allows the BUSY to go off
and the Available state to be entered.
The bit is set by the ROC when under ROC Control and
the bit is set by the MTC when under MTC Control.
MTC : The bit is set and cleared by the ROC to turn this mode
on and off for all LTCs (even when running under the GFLT).
End Of Run is also activated by the most significant 3 bits
of the Readout Type when running under the GFLT.
bit 6 BCN0 Fault
Pipeline synchronization mismatch has occured.
Cleared by ROC.
bit 7 Clock Fault
Clock or counter not running has occured.
Cleared by ROC.
The following bits are on the MTC only...
bit 8 Command Fault
A Command has occured with the MTC in the wrong state.
The Command Faults are :
- Initialise while BUSY
- Trigger while not Ready
ERROR is set (see Interrupt register).
Cleared by ROC.
bit 9 Next Buffer Full
Next Buffer Full has occured on an LTC.
An LTC sends this when its next buffer is full.
It can accept another Trigger filling its current buffer
and causing it to stay in Wait for Buffer with its BUSY on.
Cleared by ROC.
bit 10 LTC BCN0 Fault
BCN0 Fault has occured on an LTC.
Cleared by ROC.
bit 11 LTC Clock Fault
Clock Fault has occured on an LTC.
Cleared by ROC.
bit 12 LTC Reset
RESET has occured on an LTC.
Cleared by ROC.
bit 13 PLL Fault
Phase Locked Loop 48NSCK clock output not locked to 96NSCK input
Cleared by ROC.
The following bits are on LTCC3s onwards only...
bits 17 - 20 show the switches (1 = off) :
Switch Function ON OFF
SW1 A Pipeline Cycle One shot Continuous
SW1 B Crystal Clock Continuous ROC controls
SW1 C Data Transfer 48 nsec 96 nsec
SW1 D Clock Select ROC selects ROC anti-selects
A) Selects whether the pipeline addresses run through once
or cycle continuously.
Initialise re-enables pipeline cycling.
B) Selects whether the crystal clock runs continuously
or as the ROC commands (e.g. Start Clock).
C) Selects whether the addresses increment every 48 or 96 nsec
while the TRANSFER line is asserted.
ECLCLK is always 48 nsec.
D) Selects the clock source (internal / external) as follows :
ROC selects ROC anti-selects
MTC Control MTC/GFLT clock Crystal clock
not MTC Control Crystal clock MTC/GFLT clock
Interrupt register (address 08)
Source of interrupts to the readout transputer on the ROC.
See the Introduction for some general comments.
N.B. The interrupt bits are only cleared by the ROC.
The ROC has to clear the DPM valid n bits on the LTC to free the buffers.
The ROC cannot set bits, but can clear any bit
by writing the appropriate mask to the Interrupt register.
E.g. writing 0 clears all the bits,
writing FEFE (HEX) clears bits 0 and 8 only.
N.B. It is important that the ROC clears only the bits it intends
otherwise event validations can be lost.
The ROC clearing and the LTC setting the same bit simultaneously
results in the bit being cleared.
There is an important difference between LTC and MTC Interrupt register :
- LTC
- makes use of the clearing of the DPM valid n bits only.
This is for the buffer full logic.
The ROC has to clear the DPM valid n bits.
- MTC
- does not use the clearing of any bit.
There is no buffer full logic.
The ROC can ignore the MTC Interrupt register.
bit 0 BUSY
Set by BUSY such that it can be cleared when under ROC Control
in exactly the same way as under MTC Control.
The bit is immediately set again if the BUSY is still on.
It does not use the BUSY signal that the LTC outputs
which is always on when under ROC Control.
Remember that the bit is only cleared by the ROC and that
clearing it has no effect other than allowing it to be set again.
bits 1
to 10 DPM valid 0 - 9
Event validation for each buffer, showing an event to be read out.
The ROC should read out the buffers in sequence.
The bit should be cleared only when that buffer is no longer needed.
The next bit to be set is shown by the Buffer Count register.
The following table shows the correspondence between the
DPM valid bits and the buffers on the front-end cards.
Buffers on the front-end cards
Bit Bit name Buffer name Start Address
LTC ROC ROC (HEX bytes)
Z TRIG
1 DPM valid 0 DPM buffer 0 000 0000 0000
2 DPM valid 1 DPM buffer 1 080 0200 0100
3 DPM valid 2 DPM buffer 2 100 0400 0200
4 DPM valid 3 DPM buffer 3 180 0600 0300
5 DPM valid 4 DPM buffer 4 200 0800 0400
6 DPM valid 5 DPM buffer 5 280 0A00 0500
7 DPM valid 6 DPM buffer 6 300 0C00 0600
8 DPM valid 7 DPM buffer 7 380 0E00 0700
9 DPM valid 8 DPM buffer 8 400 1000 0800
10 DPM valid 9 DPM buffer 9 480 1200 0900
The Start Address contains the first data in the buffer.
The correspondence between the LTC and ROC address depends on the card.
The LTC start address (DA0 - DA10) of the buffer is equal to
the ROC 32-bit word start address (A2 - A12) of the buffer on Z-cards.
(On Trigger cards it is the ROC 16-bit word address excluding offsets.)
The ROC start address (A0 - A12) of the buffer is shown in the last two columns.
The names in brackets are the backplane lines of the LTC and ROC address bus.
Each LTC pipeline address and DPM address correspond to a 32-bit word
in the ROC address space for Z-cards, and to a 16-bit word for Trigger cards.
The LTC addresses (and transfers) all channels
of the front-end cards at the same time.
In the case of a Z-card its 4 channels are the 4 bytes of the
pipeline and buffer memory when addressed from the ROC.
bit 11 Trigger
Set by a Trigger from any source including Countdown register,
External or push-button Trigger, or Calibration Controller.
bit 12 Copy Complete
Set when the copy from pipeline to buffer is complete.
bit 13 Initialise
Set by Initialise from the ROC or the MTC / GFLT.
The following bits are on the MTC only...
bit 14 Fault
Set when one of the following Fault bits is set in the CSR :
- BCN0 Fault
- Clock Fault
- LTC BCN0 Fault
- LTC Clock Fault
bit 15 Error
Set when Fatal Error is sent to GFLT.
Error is caused by any of the following :
- Command Fault (see MTC CSR bit)
- Timeout (on LTC BUSY going off after Initialise)
- MTC entering the Stand By state (by RESET or Release)
- the ROC (setting both the MTC Control and ROC Control
bits in the MTC CSR)
Interrupt Mask register (address 0C)
To be downloaded in the Stand By state by the ROC.
Determines which bits of the Interrupt register are allowed to assert
the NOTINTERRUPT line on the backplane.
The ROC can have interrupts to the readout transputer enabled or disabled.
Command register (address 10)
The ROC issues a command by setting a bit.
The command is caused by writing a value of 1 to the bit even if the bit
is already set in the Command register, except for the Trigger bit.
The bits are only set by the ROC,
or from the MTC / GFLT when under MTC Control for bits 0 - 3.
The front panel push buttons and the countdown or external triggers
do not set a bit.
When under MTC Control the XTAL clock is not used (bits 5,6,7).
Note: the ROC should only set one bit at at time
(otherwise the action may be undefined).
bit 0 Initialise
Pipeline initialisation and synchronization.
Under MTC Control : zero pipeline address and load Jumpback
on next Bunch Crossing Zero.
Enter Initialise state.
Under ROC Control : zero pipeline address and load Jumpback.
Stop XTAL clock running.
Enter Ready state.
Zero the Buffer Count register if the first Initialise of a run
(i.e. Initialise from the Available state).
The pipeline address is also zeroed every Bunch Crossing Zero.
bit 1 Trigger (Low-High-Low)
Trigger from ROC or MTC / GFLT.
Stop the pipeline writing and Copy the window to current DPM buffer.
Clearing this bit validates the event if there was no Abort.
Enter Copy Pipeline state (MTC enters Accept state).
The following additional trigger sources are enabled when under
ROC Control but do not set the bit (but see Interrupt register) :
- Countdown register Trigger
- External or push-button Trigger
- Calibration Controller Trigger
After one of these additional triggers goes Low there is a delay
(e.g. 600 microseconds) before validating the event and re-enabling.
This allows the pipeline to refill if the clocks are running.
bit 2 Test Enable
Passed to Calibration Controller to start calibration sequence.
The current state is not changed.
bit 3 Abort
Abort Trigger if Trigger bit (FLT Accept) is still High.
The event buffer is not validated.
Enter Ready state.
bit 4 Reset
RESET whole card and enter Stand By state.
RESET is also caused by the following, but the bit is not set :
- pushing the reset button
- switching the power on
- backplane lines NOTRST and NLINE being asserted
The Buffer Counter is reset to zero.
bit 5 Start Clock
Start XTAL clock running.
Pipeline cycling starts at the current address (where it stopped).
bit 6 Stop Clock
Stop XTAL clock running.
Pipeline cycling stops at the current address.
bit 7 Single Step
Issue one XTAL clock pulse only. Only done when clock stopped.
Single Step is also caused by pushing the Single Step button,
but the bit is not set.
Buffer Count register (address 14)
Shows the current DPM buffer number (0 - 9).
It is the 4 most significant bits of the DPM address bus (DA7 - DA10)
during the next (or current) data transfer.
It is set to zero by RESET and the first Initialise of a run
(i.e. Initialise from the Available state).
It is incremented by the event buffer validation when there is no Abort
but is delayed while the buffers are full.
The ROC should not address the buffer shown by the Buffer Count register
when under MTC Control in order to avoid contention.
Pipeline Count register (address 18)
Counts 48 ns clock pulses (while pipeline cycling is enabled).
It is the pipeline cycling address which continues clocking in the
Copy Pipeline state while the pipeline transfer addresses are active.
It is reset to zero by the Pipeline End and also every Bunch Crossing Zero.
Trigger Address register (address 1C)
Pipeline address when the last Trigger occured.
This gives the arrival time at the LTC pipeline address generators
of the Trigger (FLT Accept) with respect to
Bunch Crossing Number Zero (BCN0).
In a normal data-taking run it cannot be read for every event
because several events could occur between reads.
End Copy Address register (address 20)
Pipeline address when the last Copy Complete occured.
This shows the last address copied to the DPM buffer.
Its value should be Trigger Address - Jumpback + Window End.
Countdown register (address 24)
Counts down to a trigger using the 48 ns clock.
When the ROC writes to the Countdown register
the countdown is started from the value written
and when it reaches zero a trigger is caused (when under ROC Control).
The value written is the number of Pipeline Counts to a trigger.
Maximum value is 1023 (3FF HEX).
Current State register (LTC) (address 28)
The LTC and MTC Current State registers have some differences
and so they are described separately.
In the following states the LTC is BUSY because it is waiting for the ROC :
- Stand By
- Wait for Buffer
- Wait for ROC
All the bits are displayed by LEDs.
bit 0 LTC BUSY
BUSY output to MTC. Always on under ROC Control.
BUSY off means ready for FLT Accept (Initialise or Trigger)
from MTC.
bit 1 Stand By
State entered after power on or RESET (or by Release to Stand By).
Ended by Request control.
BUSY is on.
bit 2 Available
This state is available for a run and waiting for Initialise.
Entered by Request control or End Of Run cleared by ROC.
Ended by Initialise or Release to Stand By.
BUSY is off when under MTC Control.
bit 3 Initialise
This state is pipeline initialisation and synchronization.
Entered by Initialise.
Ended by BCN0 under MTC Control (or immediately under ROC Control).
BUSY is on.
bit 4 Ready
This state is ready and waiting for a Trigger.
Entered by Initialise, Abort or from Wait For Valid / ROC.
Ended by Trigger (or Initialise).
BUSY is off when under MTC Control.
bit 5 Copy pipeline
This state is copying the pipeline to a DPM buffer.
Entered from Ready by Trigger. Ended by Copy Complete or Abort.
BUSY is on.
bit 6 Wait for Buffer
This state is BUSY waiting for the next buffer to be freed by the ROC.
Entered from Copy Pipeline. Ended by next buffer free or Abort.
BUSY is on.
Pipeline is write enabled unless ROC Pipeline Freeze is set.
bit 7 Wait for Valid
This state is waiting for the deassertion of FLT Accept / Trigger
(which may already have happened) to validate the event buffer,
or for Abort.
Either end the state. Entered from Wait For Buffer.
If there has been no Abort when the state ends the event buffer is
validated interrupting the ROC and the Buffer Count is incremented.
BUSY is off when under MTC Control
unless ROC Pipeline Freeze or End Of Run is set.
bit 8 Wait for ROC
This state is BUSY waiting for the ROC
to clear End Of Run or ROC Pipeline Freeze.
Entered by event validation if necessary. Ended by the CSR bits
ROC Pipeline Freeze and / or End Of Run being cleared.
BUSY is on.
bit 9 XTAL clock running
The internal XTAL clock is started running by Start Clock
and stopped by Stop Clock, Initialise or Pause mode activated.
Selected if not MTC in Control.
bit 10 MTC clock running
The state of the external MTC clock.
Selected only if MTC in Control.
bit 11 Pipeline running
Pipeline addresses are enabled and running (includes Copy addresses).
bit 12 Copy running
DPM buffer addresses are enabled and running (Copy addresses).
bit 13 ROC in Control
Control is by the ROC.
Internal XTAL clock and ROC commands are used.
bit 14 MTC in Control
Control is by the MTC.
External MTC clock and MTC commands are used.
bit 15 MTC Request
MTC has requested control of the LTC.
This is not used by the LTC and is just information for the ROC.
Current State register (MTC) (address 28)
The LTC and MTC Current State registers have some differences
and so they are described separately.
All the bits are displayed by LEDs.
bit 0 MTC BUSY
BUSY output to GFLT. Always on under ROC Control.
BUSY off means ready for FLT Accept (Initialise or Trigger)
from GFLT.
bit 1 Stand By
State entered after power on or RESET (or by Release to Stand By).
Ended when both Request control has occured and
the LTCs are Ready (LTC BUSY bit off).
BUSY is on.
bit 2 Available
This state is available for a run and waiting for Initialise.
Entered by Request control AND LTCs Ready
or End Of Run has been cleared on the LTCs by their ROCs.
Ended by Initialise or Release to Stand By.
BUSY is off when GFLT in Control.
bit 3 Initialise
This state is pipeline initialisation and synchronization.
Entered by Initialise.
Ended when the LTCs are Ready (LTC BUSY bit off).
BUSY is on.
bit 4 Ready
This state is ready and waiting for a Trigger.
Entered when the LTCs are Ready (LTC BUSY bit off)
after Initialise or Trigger.
Ended by Trigger (or Initialise).
BUSY is off when GFLT in Control.
bit 5 Accept
This state is BUSY while accepting an event after a Trigger.
Entered by Trigger.
Ended when the LTCs are Ready (LTC BUSY bit off).
BUSY is on.
bit 6 MTC BUSY Stand By
This is a sub-state of Stand By. BUSY is on.
Entered after power on or RESET (or by Release to Stand By).
Ended by Request control.
bit 7 MTC BUSY Initialise
This is a sub-state of Initialise. BUSY is on.
Entered by Initialise.
Ended by BCN0 (under ROC Control this implies Start Clock).
bit 8 MTC BUSY Accept
This is a sub-state of Accept. BUSY is on.
Entered by Trigger.
Ended by Copy Complete or Abort.
bit 9 XTAL clock running
The internal XTAL clock is started running by Start Clock
and stopped by Stop Clock, Initialise or Pause mode activated.
Selected if not GFLT in Control.
bit 10 GFLT clock running
The state of the external GFLT clock.
Selected only if GFLT in Control.
bit 11 Pipeline running
Pipeline addresses are enabled and running (includes Copy addresses).
Addresses are only used internally and are not output to the backplane.
bit 12 Copy running
DPM buffer addresses are enabled and running (Copy addresses).
Addresses are only used internally and are not output to the backplane.
bit 13 ROC in Control
Control is by the ROC.
Internal XTAL clock and ROC commands are output to LTCCs.
bit 14 GFLT in Control
Control is by the GFLT.
External GFLT clock and GFLT signals are output to LTCCs.
bit 15 LTC BUSY
An (enabled) LTC is BUSY.
This bit is the OR of the enabled LTC BUSY inputs.
See LTC Mask register.
Enabled but unused BUSY inputs must be pulled down by 50 ohms (or less).
MINUS Jumpback register (address 2C)
To be downloaded in the Stand By state by the ROC.
It is the pipeline length MINUS the Jumpback,
except for a Jumpback of zero when it is zero.
The Jumpback is the number of pipeline addresses to jump back to get to
the first pipeline address of the window to be copied to the DPM buffer.
E.g. for a value of zero (no jump back) the first location copied
is the pipeline address when the trigger arrived (Trigger Address).
The phase between the 96ns clock and the LSB of the pipeline address
is affected by the Jumpback. For even values of Jumpback the phase
changes during Transfer, with odd values it does not change.
In a normal data-taking run it would be about 440 - 90 = 350 (15E HEX).
(including the delay between the GFLT trigger decision
and it arriving at the LTC pipeline address generators).
Maximum value is Pipeline End = pipeline length - 1.
Window End register (address 30)
To be downloaded in the Stand By state by the ROC.
It is the length - 1 of the pipeline window to be copied to the DPM buffer.
In other words the number of locations copied counting from 0 not 1.
In a normal data-taking run it would be about 50 (32 HEX).
(including crossing ambiguity) to cover the whole
CTD FLT processing time of 25 bunch crossings.
Maximum value for normal operation is 127 (7F HEX)
which is the end of the fixed length buffers.
However, to be sure that the buffer spanning logic is not activated
the recommended maximum value is 111 (6F HEX).
Maximum value spanning buffers is 1023 (3FF HEX)
but this cannot be used for normal running because
the buffers full logic does not support buffer spanning.
Pipeline End register (address 34)
To be downloaded in the Stand By state by the ROC.
It is the address at which the pipeline wraps round back to zero,
i.e. the pipeline end address or pipeline length - 1.
Running under the GFLT it should be 439 (1B7 HEX)
to correspond to the GFLT Bunch Crossing Number cycle of 220.
Under GFLT / MTC Control every BCN0 zeros the pipeline address.
Pipeline End should be an odd value under ROC Control.
Maximum value is 1023 (3FF HEX).
LTC BUSY register (MTC only) (address 38)
This register has a bit for each LTC BUSY. The 20 bits correspond to
the 20 BUSY inputs on the MTC front panel and show each BUSY as on (bit set)
or off (bit clear). Unconnected inputs give bit set.
LTC Mask register (MTC only) (address 3C)
To be downloaded in the Stand By state by the ROC.
This register is a mask to enable the bits of the LTC BUSY register.
The enabled bits are used to form an OR of the LTC BUSYs
(LTC BUSY bit of the MTC Current State register).
The LTC Mask register tells the MTC which LTCs are to take part in the run.
DPM info registers (addresses 40 to 64)
These are in DPMs with one side for the ROC and the other for the MTC / GFLT.
Contention occurs if both sides are accessed simultaneously at the same address.
The ROC should not address the buffer shown by the Buffer Count register
when under MTC Control in order to avoid contention.
The buffers on the front-end cards are described with
the DPM valid bits in the Interrupt register.
Z-LTC Operation
RUN MODE : Request = MTC Control
TEST MODE : Request = ROC Control ... BUSY kept ON
+----------+ power on (LTC) or
| STAND BY |<-----------------------------------------------
+----------+ RESET from any state
Release (ROC) /|\ | Request (ROC) =====
======= | | ======= BUSY ON
BUSY ON | | BUSY OFF
| \|/
+-----------+
--->| AVAILABLE |<---------------------------------------------
Request (ROC) | +-----------+ ROC ready AND end_of_run |
======= | | | Initialise ======================== |
BUSY OFF ------ | ========== BUSY OFF |
| start pipeline |
| next buffer = 0 |
\|/ |
+-----------+<------------------------------------------ |
---------------->| READY | ROC ready | |
| +-----------+<--------------------- ========= | |
| Abort | Trigger | BUSY OFF | |
| ===== | ======= | restart pipeline | |
| BUSY OFF | BUSY ON | | |
| stop copy | stop pipeline | | |
| restart pipeline | start copy | | |
| | receive trigger info | | |
| \|/ | | |
| +---------------+ | | |
|-----------------| COPY PIPELINE | | | |
| +---------------+ | | |
| | Copy Complete (LTC) | | |
| | ============= | | |
| | restart pipeline if not | | |
| | ROC_pipeline_freeze | | |
| \|/ | | |
| +-----------------+ | | |
|-----------------| WAIT FOR BUFFER | | | |
| +-----------------+ | | |
| | next buffer free (LTC) | | |
| | ================ | | |
| | BUSY OFF if not | | |
| | ROC_pipeline_freeze | | |
| \|/ | | |
| +----------------+ | | |
-----------------| WAIT FOR VALID |----------------- | |
+----------------+ event valid | |
| =========== | |
| 1) interrupt ROC (set DPM valid n bit) | |
| 2) next buffer = n+1 | |
| +--------------+
------------------------------------>| WAIT FOR ROC |
event valid AND ROC_pipeline_freeze +--------------+
===================================
ditto
Notes
=====
next buffer free = DPM valid n+1 bit is OFF
event valid = stored deassertion of Trigger (FLT Accept)
ROC ready = ROC_pipeline_freeze control bit is OFF
end_of_run implies ROC_pipeline_freeze
Z-LTC Operation
SYNCHRONIZED MODE : active in RUN MODE
|
Initialise |
========== |
BUSY ON |
--------------------|
| |
| \|/
| +------------+
| | INITIALISE |
| +------------+
| | BCN0
| | ====
| | BUSY OFF
| | zero pipeline address
| | load Jumpback
| \|/
| +-----------------+
-----------| WAIT FOR |
| SYNCHRONIZATION |<---------
+-----------------+ | BCN0
| | ====
| | zero pipeline address
------------------- load Jumpback
Z-LTC / MTC Operation
CRYSTAL MODE : active in TEST MODE
|
Initialise |
========== |
zero pipeline address |
load Jumpback |
-----------------| ------
| | | | Single Step
| \|/ | | ===========
| +---------+ |
| | CRYSTAL |<---
|---------------| CLOCK |
| | STOPPED |<-------------
| +---------+ |
| | /|\ |
| Start Clock | | Stop Clock | Pause
| =========== | | ========== | =====
| \|/ | |
| +---------+ |
| | CRYSTAL | |
---------------| CLOCK |--------------
| RUNNING |
+---------+
Z-MTC Operation
RUN MODE : Request = MTC Control ... GFLT
TEST MODE : Request = ROC Control ... BUSY kept ON
power on (MTC) or | RESET from any state
| =====
| BUSY ON
| ERROR
\|/
+------------+
| STAND BY |
+------------+
Release (ROC) /|\ | Request (ROC) AND LTCs ready
======= | | ============================
BUSY ON | | BUSY OFF
ERROR | |
| \|/
+------------+
| AVAILABLE |<-----------------------------------
+------------+ |
| Initialise |
| ========== |
| BUSY ON |
\|/ |
+------------+ |
| INITIALISE | |
+------------+ |
Initialise /|\ | LTCs ready |
========== | | ========== |
BUSY ON | | BUSY OFF |
| \|/ |
+------------+ |
| READY | |
+------------+ |
LTCs ready /|\ | Trigger |
========== | | ======= |
BUSY OFF | | BUSY ON |
| \|/ |
+------------+ |
| ACCEPT |------------------------------------
+------------+ LTCs ready AND end_of_run
=========================
BUSY OFF
Notes
=====
LTCs ready = all enabled LTC BUSYs are OFF
ERROR = Fatal Error issued to GFLT
Pipeline registers and addresses
This example shows the relationship of the pipeline registers and addresses.
The input signals are from the GFLT to the MTC.
The output signals are from the LTC to the backplane.
The effects of time delays in the system are hidden in the Jumpback value
which also determines the position of time-zero in the window.
Inputs : from GFLT
-----------------------------------------------------------------
GBCN | 219 | 0 | 1 | 2 | 3 | 4 | 5 | 6 |
-----------------------------------------------------------------
_______
BCN0 _______| |_______________________________________________
_______________________________
Accept GBCN=3 _______________________________|
Outputs : from LTC
End Copy
Pipeline End (=Size) Trigger Address Address
| | |
----------V-----------------------V-----------------------V------
Pipeline Addr |437|438|439| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |439| 0 | 1 | 2 | 12|
-----------------------------------------------------------------
<-- Jumpback=6 -------->
<-- Window=4 -->
___ ___ ___ ___ ___ ___ ___ ___
NOTCLK2 | |___| |___| |___| |___| |___| |___| |___| |___|
_______________________________________ ___
NOTTRANSFER |___________________|
Window End (=Size)
|
----------------------------------------------------------V------
Window Addr | 7F | 7F| 0 | 1 | 2 | 3 | 7F|
-----------------------------------------------------------------
-----------------------------------------------------------------
Buffer Addr | F | F | Buffer Count | F |
-----------------------------------------------------------------
<------------- pipelining --------------> <- transfering ->
data data
Registers :
Pipeline -----------------------------------------------------------------
Count |437|438|439| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10| 11| 12|
register -----------------------------------------------------------------
(= Fast Clock)
Notes
- The values of the pipeline registers in this example are :
- Pipeline End (=Size) = 439 ( = pipeline length - 1 )
- MINUS Jumpback = 434 ( = Pipeline End (=Size) + 1 - Jumpback )
- Window End (=Size) = 3( = window length - 1 )
- Trigger Address = 5 ( = 2 * GBCN - 1 : always odd under GFLT Control)
- End Copy Address = 2 ( = Trigger Address - Jumpback + Window End (=Size) )
Trigger Address and End Copy Address are set after they occur.
The other three registers are set up in the Stand By state.
- The phase between the 96ns clock and the LSB of Pipeline Address
is affected by the following two registers (the others have no effect) :
- Pipeline End (=Size) must be 439 under GFLT Control,
and odd under ROC Control.
- Under GFLT / MTC Control every BCN0 zeros the pipeline address.
For even values of Jumpback the phase changes during Transfer,
with odd values it does not change.
The usual 48ns Transfer rate is assumed throughout this example.
- Under ROC Control the Trigger Address can be odd or even.
- Pipeline Address is the backplane signals RA0 - RA9.
The DPM Address bus on the backplane is made up of two parts :
Window Address is DA0 - DA6 (the 7 LSBs),
Buffer Address is DA7 - DA10 (the 4 MSBs).
- The address after the Transfer line changes allows the front-end cards
one Transfer clock period to change their memory write enables.
Data may be copied to DPM Address 7FF and may be corrupt (this is OK).
- Pipeline Address is not available in a register but the Pipeline Count
( = Fast Clock ) register is included in the example for completeness.
- Normally the MTC and all LTCs should have the same register values
but other configurations are possible.
Pipeline Registers
The following occam procedure shows the relationship between
the pipeline registers.
PROC check.pipeline.registers ()
SEQ
-- Read LTC pipeline registers
trigger.address := trigger.address.register /\ #03FF
end.copy.address := end.copy.address.register /\ #03FF
pipeline.end := pipeline.end.register /\ #03FF
window.end := window.end.register /\ #03FF
MINUS.jumpback := MINUS.jumpback.register /\ #03FF
-- Calculate Jumpback and expected end.copy.address
pipeline.length := pipeline.end + 1
jumpback := pipeline.length - MINUS.jumpback
expected.end := (trigger.address - jumpback) + window.end
-- Check for wrap around of pipeline address
IF
expected.end > pipeline.end
expected.end := expected.end - pipeline.length
expected.end < 0
expected.end := expected.end + pipeline.length
TRUE
SKIP
-- Check for end.copy.address error
IF
end.copy.address <> expected.end
log.error (E.BAD.COPYLEN)
TRUE
SKIP
:
Example of LTC and MTC registers
This is an example of the operation of the LTCs and MTC.
The system is under GFLT Control and End Of Run has occured.
10 consecutive events are buffered and 12 LTCs are enabled.
The buffers and pipeline are correctly synchronized.
MTC LTC 1 LTC 2
BUSY : BUSY ON, LTCBUSY ON BUSY ON BUSY OFF
End Of Run : EOR LED on EOR pending EOR cleared
Current State : Accept Wait for Buffer Available
DPM valid bit : interrupts disabled DAQ on buffer 0 all cleared
The End Of Run Test Trigger is in buffer 9 with FLTN = 9, GBCN = 0.
MTC Next Buffer Full came on with the ninth event.
The tenth event is buffered on LTC 1 but the next buffer is full
so the DPM valid 9 bit is pending and Buffer Count remains 9.
Trigger Address for last Trigger is 2 * GBCN - 1
End Copy Address for last Trigger is Trigger Address - Jumpback + Window Size
MTC Register Contents
Addr Register DEC HEX BIN
00 Serial Number : 0 0
04 Control Status : 3586 E02 00 1110 0000 0010
08 Interrupt : 65535 FFFF 1111 1111 1111 1111
0C Interrupt Mask : 0 0 0000 0000 0000 0000
10 Command : 0 0 0000 0000
14 Buffer Count : 0 0
18 Pipeline Count : 303 12F
1C Trigger Address : 439 1B7
20 End Copy Address : 364 16C
24 Countdown : 0 0
28 Current State : 52257 CC21 1100 1100 0010 0001
2C MINUS Jumpback : 334 14E
30 Window End : 31 1F
34 Pipeline End : 439 1B7
38 LTC BUSY : 987133 F0FFD 1111 0000 1111 1111 1101
3C LTC Mask : 4095 FFF 0000 0000 1111 1111 1111
40 DPM info 0 : 002200
44 DPM info 1 : 000701
48 DPM info 2 : 004E02
4C DPM info 3 : 003303
50 DPM info 4 : 00B404
54 DPM info 5 : 00A805
58 DPM info 6 : 009506
5C DPM info 7 : 008F07
60 DPM info 8 : 00BD08
64 DPM info 9 : F20009
LTC Register Contents (LTC 1)
Addr Register DEC HEX BIN
00 Serial Number : 0 0
04 Control Status : 226 E2 1110 0010
08 Interrupt : 15359 3BFF 11 1011 1111 1111
0C Interrupt Mask : 2 2 00 0000 0000 0010
10 Command : 0 0 0000 0000
14 Buffer Count : 9 9
18 Pipeline Count : 405 195
1C Trigger Address : 439 1B7
20 End Copy Address : 364 16C
24 Countdown : 0 0
28 Current State : 52801 CE41 1100 1110 0100 0001
2C MINUS Jumpback : 334 14E
30 Window End : 31 1F
34 Pipeline End : 439 1B7
40 DPM info 0 : 002200
44 DPM info 1 : 000701
48 DPM info 2 : 004E02
4C DPM info 3 : 003303
50 DPM info 4 : 00B404
54 DPM info 5 : 00A805
58 DPM info 6 : 009506
5C DPM info 7 : 008F07
60 DPM info 8 : 00BD08
64 DPM info 9 : F20009
LTC Register Contents (LTC 2)
Addr Register DEC HEX BIN
00 Serial Number : 0 0
04 Control Status : 194 C2 1100 0010
08 Interrupt : 14337 3801 11 1000 0000 0001
0C Interrupt Mask : 2 2 00 0000 0000 0010
10 Command : 0 0 0000 0000
14 Buffer Count : 0 0
18 Pipeline Count : 202 CA
1C Trigger Address : 439 1B7
20 End Copy Address : 364 16C
24 Countdown : 0 0
28 Current State : 52740 CE04 1100 1110 0000 0100
2C MINUS Jumpback : 334 14E
30 Window End : 31 1F
34 Pipeline End : 439 1B7
40 DPM info 0 : 002200
44 DPM info 1 : 000701
48 DPM info 2 : 004E02
4C DPM info 3 : 003303
50 DPM info 4 : 00B404
54 DPM info 5 : 00A805
58 DPM info 6 : 009506
5C DPM info 7 : 008F07
60 DPM info 8 : 00BD08
64 DPM info 9 : F20009
Example of a simple run
Sequence of steps to setup and run an LTC or MTC.
Each step is a write to a register.
Triggers are repeated as required.
Note that the LTC Interrupt register has to be cleared
otherwise the LTC will stay in state Wait for Buffer.
Step Register Action Addr Value (HEX)
---- -------- ------ ---- -----
1 Command RESET 10 10
2 Interrupt Zero interrupt bits 08 0
3 Interrupt Mask Setup interrupts 0C (7FE)
4 Pipeline End Setup pipeline 34 (1B7)
5 Window End Setup pipeline 30 ( 32)
6 MINUS Jumpback Setup pipeline 2C (15E)
7 Control Status Set ROC Control bit 04 4
8 Command Set Initialise bit 10 1
9 Command Set Start Clock bit 10 20
10 Command Set Trigger bit 10 2
11 Command Clear Trigger bit 10 0
Notes :
- To run under MTC / GFLT Control replace steps 7 on by :
7 Control Status Set MTC Control bit 04 2
- Values in brackets are to be chosen as required.
The Window End and Jumpback values for a normal data-taking run
need tuning or enlarging as they depend on delays in the system.
- The pipeline address generator only loads the MINUS Jumpback
on an Initialise with the clocks running,
so steps 8 and 9 need repeating in order to use the Jumpback
i.e. a) Initialise, Start Clock, Initialise, Start Clock
or b) Start Clock, Initialise, Start Clock.
This only applies to an LTC under ROC Control.
- To copy from pipeline address zero (or Countdown) use the following
sequence : Initialise, Trigger (or Countdown), Start Clock.
- For the MTC to use the LTC BUSYs, its LTC Mask register should be
setup as required.
Comments
Z - LTC and MTC Registers COMMENTS PLEASE ! Version 1.13 31-Jul-1992 J.B.Lane
========================= UCLVB::disk$U1:[useract.JBL.doc.TC]reg.txt
ZEUS02::disk$online:[Lane.TC]reg.txt