"=================================================================================================== #TITLE 'PROTOTYPE HELIX DRIVER: VME INTERFACE AND BOARD LOGIC'; #ENGINEER 'Gil Nixon / Dominic A Hayes'; #COMPANY 'University College London'; #COMMENT 'VME interface and Logic: V2.0'; "=================================================================================================== " **** THIS VERSION IS USED BY THE 2CH PROTOTYPE **** " ========================================= " " PROTOTYPE HELIX DRIVER BOARD LOGIC " INCORPORATING " D16:A24 VME SLAVE interface. " " *** USES EXTERNAL VME DATA LATCHES (74ALS543) *** " (To simulate convert feedback_in to NODE.) " " 29oct99 a[7..1] clocked by dl1 instead of ds0. " 03nov99 removed registering of wr and rd signals (previously clocked by ds and reset by /ds !). " 15nov99 removed low_true o/p definitions. " 23nov99 v.. signals o/p. " bdsel o/p. " db_clk o/p. " sr_clk o/p. " ack = bdsel AND dl2. " 08dec99 changed VME clocking to /db_clk (from db_clk) => this cures VME access problem. " 14dec99 sr clked by /sr_clk. (/db_clk now db_clk, effect same) => fixes lost first bit. " 16dec99 THIS VERSION USES COUNTER DECODING TO MULTIPLEX THE OUTPUT DATA. " This does not utilise a shift register and the sr register data remains static. " 18apr00 ch0 clocked by /sr_clk instead of sr_clk (same as sr, silly me!) " removed unused count20, count21 nodes. " sr_clk replaced by db_clk as data is no longer SHIFTED out. " 23may00 reset & hreset modified. " "=================================================================================================== " SIGNAL DECLARATIONS "=================================================================================================== " VME " ======= "-------------------------------------------------------------------------------------------------- LOW_TRUE INPUT sreset; "from switch. NODE reset; "vreset. " VME INPUTS "------------ LOW_TRUE INPUT lwordb; "Buffered VME signal. INPUT writeb; "ACTIVE LOW. Buffered VME Data Write. LOW_TRUE INPUT berrb; "Buffered VME Bus ERRor. LOW_TRUE INPUT ds0b, ds1b; "Buffered VME Data Strobes. LOW_TRUE INPUT iackb; "Buffered VME Interupt ACKnowledge. INPUT amb[5..0]; "Buffered VME Address Modifier. INPUT ab[23..1]; "Buffered VME Address bus. ab[15..8] no_connect. "-------------------------------------------------------------------------------------------------- " signals derived from vme "-------------------------- NODE ds; " - "OR'ed" ds0/1b. NODE ssda, snda "Address modifier codes. DEFAULT_TO 0; NODE am_OK "Correct Address Modifier for bread. CLOCKED_BY dl1 RESET_BY /ds; "Falling edge of ds (cycle finished). NODE addr_OK "VME address = base address. CLOCKED_BY dl1 RESET_BY /ds DEFAULT_TO 0; NODE a[7..1] "ab[7..1] Latched. CLOCKED_BY dl1 RESET_BY /ds; NODE bdsel; "BoarD SELect. OUTPUT ack; "Data Transfer ACK (to external Open Collecter gate). "-------------------------------------------------------------------------------------------------- " external delay line signals "----------------------------- "to delay line "------------- OUTPUT dl0; "OR'd ds0/1b, Data Strobe, sent to delay line. "from delay line "--------------- INPUT dl1; "used to clock am_OK and addr_OK. INPUT dl2; "used by oeout and ack (/dl2 used by db_le and db_clk). "-------------------------------------------------------------------------------------------------- " DIP switch base address stuff "------------------------------- INPUT base_addr[23..16]; "selected base address from DIP switch (8bit address). "----------------------------------------------------------------------------------------------- " vme data latch '543 signals "----------------------------- OUTPUT oein, oeout; "ACTIVE LOW. Output Enables for vme data bus '543 latches. OUTPUT db_le; "ACTIVE LOW. latches the vme data (on the '543) onto the board. [le1] NODE db_clk; "clocks db data into register ('996 or pld). [le2] OUTPUT wr; "ACTIVE LOW. WRiteb to '543 vme d[15..0] latches. OUTPUT rd; "ACTIVE LOW. ReaD signal to '543 vme bus d[15..0] latches. "----------------------------------------------------------------------------------------------- " decoded VME address commands (signals) "---------------------------------------- NODE vreset, "VME reset. vsr_low, "low end sequence register addressed vsr_high, "high end sequence register addressed vfb_low, "low end feedback sequence register addressed vfb_high, "high end feedback sequence register addressed vhloaden, "set load (helix registers) enable mode. vstart, "start the sequence output rolling. Yee haa! vhreset "VME generated helix reset DEFAULT_TO 0; "----------------------------------------------------------------------------------------------- OUTPUT errorled; "Bus ERRor when board addressed. "------------------------------------------------------------------------------------------------- " LOGIC INPUT / OUTPUT / NODE declarations " ========================================== "------------------------------------------------------------------------------------------------ " FROM MASTER BOX "----------------- INPUT ck, trig, not_reset; "------------------------------------------------------------------------------------------------ " SIGNALS TO HELIX "------------------ OUTPUT clock; OUTPUT trig_sd CLOCKED_BY /ck RESET_BY reset; OUTPUT load0, load1 CLOCKED_BY /ck RESET_BY reset DEFAULT_TO 0; OUTPUT hreset CLOCKED_BY /ck RESET_BY reset; "-------------------------------------------------------------------------------------------------- " OUTPUT TEST CIRCUITRY "----------------------- NODE feedback[19..0] "feedback shift register, used to check o/p data. CLOCKED_BY ck " NB clocked by out of phase clock, cf trig_sd. RESET_BY reset; " can be read by VME. NODE en_feedback CLOCKED_BY start RESET_BY (count22 OR reset); "-------------------------------------------------------------------------------------------------- " VME DATABUS "------------- BIPUT db[15..0] "bi-directional i/o pins. ENABLED_BY dboe; NODE dboe; "db output enable. "-------------------------------------------------------------------------------------------------- " synchronisation FFs (sync VME commands to external clock, ck) "--------------------------------------------------------------- NODE q1 "sync FF. CLOCKED_BY vstart RESET_BY (count22 OR reset); NODE q2 "sync FF. CLOCKED_BY ck RESET_BY (count22 OR reset); NODE start "sync'd vstart signal. CLOCKED_BY ck RESET_BY (count23 OR reset); NODE hloaden "sync FF (stores load enable mode.) CLOCKED_BY vhloaden RESET_BY reset; "-------------------------------------------------------------------------------------------------- " SHIFT REGISTER AND OUTPUT "--------------------------- NODE sr[19..0] "the sequence register. CLOCKED_BY /db_clk RESET_BY reset; NODE ch0 "helix channel number. CLOCKED_BY /db_clk RESET_BY reset; NODE data "the data stream from sequence register (before o/p MUX) DEFAULT_TO 0; NODE count[5] "sequence length counter. CLOCKED_BY ck CLOCK_ENABLED_BY start RESET_BY (reset OR /start); NODE load "load signal, generated at completion of DEFAULT_TO 0; " data sequence output. NODE count22, count23 "counter o/ps, reset counter and issue load signal. DEFAULT_TO 0; "=================================================================================================== "**************************************************************************** " SIMULATION REQUIREMENTS (allows feedback register to be simulated.) " ------------------------------------------------------------------- " " ** FOR FITTING uncomment the next line. ** INPUT feedback_in; "EXTERNAL feedback trig_sd data into pld " " ** FOR SIMULATION uncomment the next two lines. ** " NODE feedback_in; "INTERNAL feedback. " feedback_in = trig_sd; "**************************************************************************** "=================================================================================================== " EQUATIONS "=================================================================================================== " VME LOGIC "=========== ds = ds0b OR ds1b; " - OR'ed Data Strobes dl0 = ds; a[7..1] = ab[7..1]; "Latched low address signals. wr = writeb; "bwrite signal. low for master write. rd = /writeb; "low for master read. IF (/iackb AND /lwordb) THEN "ADDRESS MODIFIER DECODE CASE amb "======================= WHEN 3Dh => ssda = 1; "Standard supervisory data access. WHEN 39h => snda = 1; "Standard non-privileged data access. END CASE; END IF; am_OK = ssda OR snda; "Either of the A24 data access codes. IF (ab[23..16] = base_addr[23..16]) THEN "VME address matches board address. addr_OK = 1; END IF; bdsel = am_OK AND addr_OK; "BoarD SELected when both asserted. " DECODED ADDRESS LINES (VME ISSUED COMMANDS) "============================================= IF (bdsel) THEN CASE (a) WHEN 0 => vhreset = 1; " issues helix reset. WHEN 1 => vsr_low = 1; " address LSB of s/r. WHEN 2 => vsr_high = 1; " address MSB of s/r. WHEN 3 => vfb_low = 1; " address LSB of o/p feedback s/r. WHEN 4 => vfb_high = 1; " address MSB of o/p feedback s/r. WHEN 5 => vhloaden = 1; " set board to o/p data NOT triggers (NB requires "vreset" to reset). WHEN 6 => vstart = 1; " starts sr output. WHEN 7 => vreset = 1; " resets all PLD registers. END CASE; END IF; " VME CONTROL SIGNALS "===================== db_le = /( bdsel AND /dl2); "ACTIVE LOW. latch vme data (on the '543) onto the board.[le1]. db_clk = (/wr AND bdsel AND /dl2); "clock db data into register (pld). [le2]. oein = /(/wr AND bdsel ); "ACTIVE LOW. Output Enable for VME master WRITEs. oeout = /(/rd AND bdsel AND dl2); "ACTIVE LOW. Output Enable for VME master READs. ack = bdsel AND dl2; "=> DTACK*, end of VME access cycle. errorled = (berrb AND addr_OK); "signal to LED when bus error AND board is addressed. "================================================================================================== "================================================================================================== " NON-VME LOGIC "=============== "--------------------------------------------------------------------------- " CLOCK generation "------------------ clock = ck; "96ns clock from MASTER board. "--------------------------------------------------------------------------- " Start, Load Enable signal registering/synchronization "------------------------------------------------------- q1 = 1; "Sync q2 = q1; " start = q2; "FF's. hloaden = 1; "--------------------------------------------------------------------------- " Counter "--------- count = count .+. 1; "defines inputs to count FF's => counter. CASE count WHEN 21 => count22 = 1; "resets en_feedback, and q1/2 vstart sync FFs. WHEN 22 => count23 = 1; "resets start FF. END CASE; "-------------------------------------------------------------------------- " Register and DATA "------------------- IF (/rd) THEN "ie sr not being loaded (VME read mode). IF (start) THEN CASE count WHEN 1 => data = sr[19]; WHEN 2 => data = sr[18]; WHEN 3 => data = sr[17]; WHEN 4 => data = sr[16]; WHEN 5 => data = sr[15]; WHEN 6 => data = sr[14]; WHEN 7 => data = sr[13]; WHEN 8 => data = sr[12]; WHEN 9 => data = sr[11]; WHEN 10 => data = sr[10]; WHEN 11 => data = sr[9]; WHEN 12 => data = sr[8]; WHEN 13 => data = sr[7]; WHEN 14 => data = sr[6]; WHEN 15 => data = sr[5]; WHEN 16 => data = sr[4]; WHEN 17 => data = sr[3]; WHEN 18 => data = sr[2]; WHEN 19 => data = sr[1]; WHEN 20 => data = sr[0]; WHEN 21 => load = 1; END CASE; ELSE ch0 = ch0; END IF; ELSIF (/wr) THEN "VME write mode IF (vsr_low) THEN "VME WRITEs LSBs of sequence register. sr[15..0] = db[15..0]; sr[19..16] = sr[19..16]; ch0 = ch0; ELSIF (vsr_high) THEN "VME WRITEs MSBs of sequence register. sr[15..0] = sr[15..0]; sr[19..16] = db[3..0]; "preload sr[19..16] from first 4 bits of db word. ch0 = db[4]; "preload ch0 from bit 5 of db word. ELSE sr = sr; ch0 = ch0; END IF; END IF; "--------------------------------------------------------------------------- " LOAD pulse generation "----------------------- IF (load) THEN "ie at end of data sequence out. CASE ch0 "the bit value loaded at same time as MSB's of sr. WHEN 0 => load0 = 1; WHEN 1 => load1 = 1; END CASE; END IF; "--------------------------------------------------------------------------- " Trigger/Serial Data Multiplexer (requires reset to reset FF) "------------------------------------------------------------- IF (hloaden) THEN "helix board in "load helix registers" mode. trig_sd = data; ELSE "normal running, triggers allowed through. trig_sd = trig; END IF; "--------------------------------------------------------------------------- " RESET pulse generation "------------------------ hreset = /(/not_reset OR vhreset OR sreset); "helix (frontend) CHIP reset. reset = (vreset); "helix driver BOARD reset. "---------------------------------------------------------------------------- " Test o/p feedback shift register "---------------------------------- en_feedback = 1; "FF clocked when feedback starts. IF (en_feedback) THEN feedback[19..0] = [ feedback[18..0] , feedback_in ]; "defines feedback shift register. ELSE feedback = feedback; "stationary data in feedback reg. END IF; "------------------------------------------------------------------------------------ " Assign data to the vme databus biput db "------------------------------------------ dboe = /rd AND ( vsr_low "databus output enable. OR vsr_high OR vfb_low OR vfb_high ); IF (/rd AND /start) THEN "ie, if VME reading and board NOT outputing. " VME READ "---------- IF (vsr_low) THEN "VME READs LSBs of sr. db[15..0] = sr[15..0]; ELSIF (vsr_high) THEN "VME READs MSBs of sr. db[4..0] = [ ch0 , sr[19..16] ]; db[15..5] = 0; ELSIF (vfb_low) THEN "VME READs LSBs of feedback register. db[15..0] = feedback[15..0]; ELSIF (vfb_high) THEN "VME READs MSBs of feedback register. db[3..0] = feedback[19..16]; db[15..4] = 0; END IF; END IF; "====================================================================================================