PLDocument: Y:\clock\zeus\slave\pld2\pld2.doc TITLE PAGE Fri Feb 25 17:03:27 2000 A MACHXL6.2.1.11 - (c) Copyright MINC Incorporated 1987-1998 ============================================================================== TITLE : ZEUS C&C SLAVE PLD2 FILE : Y:\clock\zeus\slave\pld2\pld2 DATE : Thu Jun 04 02:36:00 1970 ENGINEER : Martin Postranecky / Dominic A Hayes COMPANY : University College London ============================================================================== MODULES : Document Generator 3.70 File Handler 6.2 Language Compiler 3.83 Architectural Optimizer 3.110 Device Lib Scan 3.2 Device Library 3.17 Device Partition 3.21 Device Fusemap 3.4 SWITCH VALUES : (Value in parenthesis represents batch mode switch value) PLCOMP PRODUCT TERM LIMIT : 128 PLOPT PRODUCT TERM LIMIT : 128 PLOPT REDUCTION : Espresso (1) NODE GENERATION : Procedure Instantiation Arithmetic and Relational Operators (1) PLDocument: Y:\clock\zeus\slave\pld2\pld2.doc EQUATIONS Fri Feb 25 17:03:27 2000 EQUATIONS FOR SYSTEM INPUT SIGNALS (39) : LOW_TRUE reg00 LOW_TRUE reg02 LOW_TRUE reg04 LOW_TRUE reg06 LOW_TRUE reg08 LOW_TRUE bread LOW_TRUE bwrite LOW_TRUE leb2 LOW_TRUE noa_rst sclk_4 mdb[7..0] da[1..0] a_abort a_accept a_reset bplane_accept bplane_abort bplane_reset bplane_error bplane_f_error bplane_busy bplane_empty a_clkon abusy af_error aerror s_rst s12[3..0] OUTPUT SIGNALS (42) : db[15..0] mdbout[7..0] daout[1..0] a_abortout a_acceptout a_resetout vsoa_reset vbusy vf_error verror entestbusy clrtestbusy busy f_error error nerror testbusy oa_reset noa_reset PHYSICAL NODE SIGNALS (69) : dboe gflt_data.1.register00[15..0] gflt_data.1.register02[15..0] gflt_data.1.sync.1.q1 gflt_data.1.sync.2.q1 gflt_data.1.sync.3.q1 gflt_data.1.sync.4.q1 gflt_data.1.sync.5.q1 gflt_data.1.sync.6.q1 gflt_data.1.sync.7.q1 gflt_data.1.sync.8.q1 gflt_data.1.sync.9.q1 gflt_data.1.sync.10.q1 gflt_data.1.sync.11.q1 gflt_data.1.sync.12.q1 gflt_data.1.sync.13.q1 state_and_com_regs.1.register06[13..7] state_and_com_regs.1.register06[5] state_and_com_regs.1.register06[2] state_and_com_regs.1.register06[0] adc_signals.1.q1 adc_signals.1.q3 adc_signals.1.q5 reset_and_test.1.q1_reset reset_and_test.1.q2 reset_and_test.1.q3 reset_and_test.1.q2_clk reset_and_test.1.q_reset reset_and_test.1.level_to_pulse.1.pulse reset_and_test.1.level_to_pulse.1.clr last_abort.1.q1 last_abort.1.q3 last_abort.1.q_reset REDUCED EQUATIONS: dboe.EQN(~) = /bread + /reg00*/reg02*/reg04*/reg06*/reg08 ; "(2 terms, 6 symbols) db[15].EQN = bplane_accept*/reg00*/reg02*reg04 + clrtestbusy*/reg00*/reg02*/reg04* reg06 + gflt_data.1.register00[15]*reg00 + gflt_data.1.register02[15]*/reg00* reg02 + /reg00*/reg02*/reg04*/reg06* testbusy ; "(5 terms, 9 symbols) db[15].OE = dboe ; "(1 term, 1 symbol) db[14].EQN = bplane_abort*/reg00*/reg02*reg04 + gflt_data.1.register00[14]*reg00 + gflt_data.1.register02[14]*/reg00* reg02 + /reg00*/reg02*/reg04*reg06* entestbusy ; "(4 terms, 8 symbols) db[14].OE = dboe ; "(1 term, 1 symbol) db[13].EQN = bplane_reset*/reg00*/reg02*reg04 + gflt_data.1.register00[13]*reg00 + gflt_data.1.register02[13]*/reg00* reg02 + /reg00*/reg02*/reg04*reg06* state_and_com_regs.1.register06[13] ; "(4 terms, 8 symbols) db[13].OE = dboe ; "(1 term, 1 symbol) db[12].EQN = bplane_error*/reg00*/reg02*reg04 + gflt_data.1.register00[12]*reg00 + gflt_data.1.register02[12]*/reg00* reg02 + last_abort.1.q1*/reg00*/reg02* /reg04*/reg06 + /reg00*/reg02*/reg04*reg06* state_and_com_regs.1.register06[12] ; "(5 terms, 9 symbols) db[12].OE = dboe ; "(1 term, 1 symbol) db[11].EQN = bplane_f_error*/reg00*/reg02*reg04 + gflt_data.1.register00[11]*reg00 + gflt_data.1.register02[11]*/reg00* reg02 + a_resetout*/reg00*/reg02*/reg04* /reg06 + /reg00*/reg02*/reg04*reg06* state_and_com_regs.1.register06[11] ; "(5 terms, 9 symbols) db[11].OE = dboe ; "(1 term, 1 symbol) db[10].EQN = bplane_busy*/reg00*/reg02*reg04 + gflt_data.1.register00[10]*reg00 + gflt_data.1.register02[10]*/reg00* reg02 + /reg00*/reg02*/reg04*reg06* state_and_com_regs.1.register06[10] ; "(4 terms, 8 symbols) db[10].OE = dboe ; "(1 term, 1 symbol) db[9].EQN = bplane_empty*/reg00*/reg02*reg04 + gflt_data.1.register00[9]*reg00 + gflt_data.1.register02[9]*/reg00* reg02 + /reg00*/reg02*/reg04*reg06* state_and_com_regs.1.register06[9] ; "(4 terms, 8 symbols) db[9].OE = dboe ; "(1 term, 1 symbol) db[8].EQN = gflt_data.1.register00[8]*reg00 + gflt_data.1.register02[8]*/reg00* reg02 + /reg00*/reg02*/reg04*reg06* state_and_com_regs.1.register06[8] ; "(3 terms, 7 symbols) db[8].OE = dboe ; "(1 term, 1 symbol) db[7].EQN = gflt_data.1.register00[7]*reg00 + gflt_data.1.register02[7]*/reg00* reg02 + /reg00*/reg02*/reg04*reg06* state_and_com_regs.1.register06[7] ; "(3 terms, 7 symbols) db[7].OE = dboe ; "(1 term, 1 symbol) db[6].EQN = error*/reg00*/reg02*reg04 + gflt_data.1.register00[6]*reg00 + gflt_data.1.register02[6]*/reg00* reg02 + /reg00*/reg02*/reg04*reg06*verror ; "(4 terms, 8 symbols) db[6].OE = dboe ; "(1 term, 1 symbol) db[5].EQN = gflt_data.1.register00[5]*reg00 + gflt_data.1.register02[5]*/reg00* reg02 + /reg00*/reg02*/reg04*reg06* state_and_com_regs.1.register06[5] ; "(3 terms, 7 symbols) db[5].OE = dboe ; "(1 term, 1 symbol) db[4].EQN = a_clkon*/reg00*/reg02*/reg04*/reg06 + f_error*/reg00*/reg02*reg04 + gflt_data.1.register00[4]*reg00 + gflt_data.1.register02[4]*/reg00* reg02 + /reg00*/reg02*/reg04*reg06*vf_error ; "(5 terms, 9 symbols) db[4].OE = dboe ; "(1 term, 1 symbol) db[3].EQN = busy*/reg00*/reg02*reg04 + gflt_data.1.register00[3]*reg00 + gflt_data.1.register02[3]*/reg00* reg02 + /reg00*/reg02*/reg04*reg06*vbusy ; "(4 terms, 8 symbols) db[3].OE = dboe ; "(1 term, 1 symbol) db[2].EQN = gflt_data.1.register00[2]*reg00 + gflt_data.1.register02[2]*/reg00* reg02 + /reg00*/reg02*/reg04*reg06* state_and_com_regs.1.register06[2] ; "(3 terms, 7 symbols) db[2].OE = dboe ; "(1 term, 1 symbol) db[1].EQN = gflt_data.1.register00[1]*reg00 + gflt_data.1.register02[1]*/reg00* reg02 + /reg00*/reg02*/reg04*reg06* vsoa_reset ; "(3 terms, 7 symbols) db[1].OE = dboe ; "(1 term, 1 symbol) db[0].EQN = gflt_data.1.register00[0]*reg00 + gflt_data.1.register02[0]*/reg00* reg02 + /reg00*/reg02*/reg04*reg06* state_and_com_regs.1.register06[0] ; "(3 terms, 7 symbols) db[0].OE = dboe ; "(1 term, 1 symbol) mdbout[7].D = gflt_data.1.sync.8.q1 ; "(1 term, 1 symbol) mdbout[7].RESET = noa_rst ; "(1 term, 1 symbol) mdbout[7].CLK(~) = sclk_4 ; "(1 term, 1 symbol) mdbout[6].D = gflt_data.1.sync.7.q1 ; "(1 term, 1 symbol) mdbout[6].RESET = noa_rst ; "(1 term, 1 symbol) mdbout[6].CLK(~) = sclk_4 ; "(1 term, 1 symbol) mdbout[5].D = gflt_data.1.sync.6.q1 ; "(1 term, 1 symbol) mdbout[5].RESET = noa_rst ; "(1 term, 1 symbol) mdbout[5].CLK(~) = sclk_4 ; "(1 term, 1 symbol) mdbout[4].D = gflt_data.1.sync.5.q1 ; "(1 term, 1 symbol) mdbout[4].RESET = noa_rst ; "(1 term, 1 symbol) mdbout[4].CLK(~) = sclk_4 ; "(1 term, 1 symbol) mdbout[3].D = gflt_data.1.sync.4.q1 ; "(1 term, 1 symbol) mdbout[3].RESET = noa_rst ; "(1 term, 1 symbol) mdbout[3].CLK(~) = sclk_4 ; "(1 term, 1 symbol) mdbout[2].D = gflt_data.1.sync.3.q1 ; "(1 term, 1 symbol) mdbout[2].RESET = noa_rst ; "(1 term, 1 symbol) mdbout[2].CLK(~) = sclk_4 ; "(1 term, 1 symbol) mdbout[1].D = gflt_data.1.sync.2.q1 ; "(1 term, 1 symbol) mdbout[1].RESET = noa_rst ; "(1 term, 1 symbol) mdbout[1].CLK(~) = sclk_4 ; "(1 term, 1 symbol) mdbout[0].D = gflt_data.1.sync.1.q1 ; "(1 term, 1 symbol) mdbout[0].RESET = noa_rst ; "(1 term, 1 symbol) mdbout[0].CLK(~) = sclk_4 ; "(1 term, 1 symbol) daout[1].D = gflt_data.1.sync.10.q1 ; "(1 term, 1 symbol) daout[1].RESET = noa_rst ; "(1 term, 1 symbol) daout[1].CLK(~) = sclk_4 ; "(1 term, 1 symbol) daout[0].D = gflt_data.1.sync.9.q1 ; "(1 term, 1 symbol) daout[0].RESET = noa_rst ; "(1 term, 1 symbol) daout[0].CLK(~) = sclk_4 ; "(1 term, 1 symbol) a_abortout.D = gflt_data.1.sync.11.q1 ; "(1 term, 1 symbol) a_abortout.RESET = noa_rst ; "(1 term, 1 symbol) a_abortout.CLK(~) = sclk_4 ; "(1 term, 1 symbol) a_acceptout.D = gflt_data.1.sync.12.q1 ; "(1 term, 1 symbol) a_acceptout.RESET = noa_rst ; "(1 term, 1 symbol) a_acceptout.CLK(~) = sclk_4 ; "(1 term, 1 symbol) a_resetout.D = gflt_data.1.sync.13.q1 ; "(1 term, 1 symbol) a_resetout.RESET = noa_rst ; "(1 term, 1 symbol) a_resetout.CLK(~) = sclk_4 ; "(1 term, 1 symbol) vsoa_reset.D = bwrite*db[1]*reg06 + /bwrite*vsoa_reset + /reg06*vsoa_reset ; "(3 terms, 4 symbols) vsoa_reset.CLK = /leb2 ; "(1 term, 1 symbol) vsoa_reset.RESET = noa_rst ; "(1 term, 1 symbol) vbusy.D = bwrite*db[3]*reg06 + /bwrite*vbusy + /reg06*vbusy ; "(3 terms, 4 symbols) vbusy.CLK = /leb2 ; "(1 term, 1 symbol) vbusy.RESET = noa_rst ; "(1 term, 1 symbol) vf_error.D = bwrite*db[4]*reg06 + /bwrite*vf_error + /reg06*vf_error ; "(3 terms, 4 symbols) vf_error.CLK = /leb2 ; "(1 term, 1 symbol) vf_error.RESET = noa_rst ; "(1 term, 1 symbol) verror.D = bwrite*db[6]*reg06 + /bwrite*verror + /reg06*verror ; "(3 terms, 4 symbols) verror.CLK = /leb2 ; "(1 term, 1 symbol) verror.RESET = noa_rst ; "(1 term, 1 symbol) entestbusy.D = bwrite*db[14]*reg06 + /bwrite*entestbusy + /reg06*entestbusy ; "(3 terms, 4 symbols) entestbusy.CLK = /leb2 ; "(1 term, 1 symbol) entestbusy.RESET = noa_rst ; "(1 term, 1 symbol) clrtestbusy.D = bwrite*db[15]*reg06 + /bwrite*clrtestbusy + /reg06*clrtestbusy ; "(3 terms, 4 symbols) clrtestbusy.CLK = /leb2 ; "(1 term, 1 symbol) clrtestbusy.RESET = noa_rst ; "(1 term, 1 symbol) busy.D = adc_signals.1.q1 ; "(1 term, 1 symbol) busy.CLK = sclk_4 ; "(1 term, 1 symbol) busy.RESET = noa_rst ; "(1 term, 1 symbol) f_error.D = adc_signals.1.q3 ; "(1 term, 1 symbol) f_error.CLK = sclk_4 ; "(1 term, 1 symbol) f_error.RESET = noa_rst ; "(1 term, 1 symbol) error.D = adc_signals.1.q5 ; "(1 term, 1 symbol) error.CLK = sclk_4 ; "(1 term, 1 symbol) error.RESET = noa_rst ; "(1 term, 1 symbol) nerror.EQN = /error ; "(1 term, 1 symbol) testbusy.D = 1 ; "(1 term, 0 symbols) testbusy.CLK = a_acceptout ; "(1 term, 1 symbol) testbusy.RESET = /reset_and_test.1.q1_reset ; "(1 term, 1 symbol) oa_reset.D = reset_and_test.1.q3 ; "(1 term, 1 symbol) oa_reset.CLK = sclk_4 ; "(1 term, 1 symbol) noa_reset.EQN = /oa_reset ; "(1 term, 1 symbol) gflt_data.1.register00[15].D = gflt_data.1.register00[15]*daout[1] + gflt_data.1.register00[15]* /daout[0] + /daout[1]*mdbout[7]*daout[0] ; "(3 terms, 4 symbols) gflt_data.1.register00[15].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register00[15].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register00[14].D = gflt_data.1.register00[14]*daout[1] + gflt_data.1.register00[14]* /daout[0] + /daout[1]*mdbout[6]*daout[0] ; "(3 terms, 4 symbols) gflt_data.1.register00[14].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register00[14].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register00[13].D = gflt_data.1.register00[13]*daout[1] + gflt_data.1.register00[13]* /daout[0] + /daout[1]*mdbout[5]*daout[0] ; "(3 terms, 4 symbols) gflt_data.1.register00[13].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register00[13].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register00[12].D = gflt_data.1.register00[12]*daout[1] + gflt_data.1.register00[12]* /daout[0] + /daout[1]*mdbout[4]*daout[0] ; "(3 terms, 4 symbols) gflt_data.1.register00[12].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register00[12].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register00[11].D = gflt_data.1.register00[11]*daout[1] + gflt_data.1.register00[11]* /daout[0] + /daout[1]*mdbout[3]*daout[0] ; "(3 terms, 4 symbols) gflt_data.1.register00[11].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register00[11].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register00[10].D = gflt_data.1.register00[10]*daout[1] + gflt_data.1.register00[10]* /daout[0] + /daout[1]*mdbout[2]*daout[0] ; "(3 terms, 4 symbols) gflt_data.1.register00[10].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register00[10].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register00[9].D = gflt_data.1.register00[9]*daout[1] + gflt_data.1.register00[9]*/daout[0] + /daout[1]*mdbout[1]*daout[0] ; "(3 terms, 4 symbols) gflt_data.1.register00[9].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register00[9].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register00[8].D = gflt_data.1.register00[8]*daout[1] + gflt_data.1.register00[8]*/daout[0] + mdbout[0]*/daout[1]*daout[0] ; "(3 terms, 4 symbols) gflt_data.1.register00[8].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register00[8].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register00[7].D = gflt_data.1.register00[7]*/daout[1] + gflt_data.1.register00[7]*daout[0] + daout[1]*mdbout[7]*/daout[0] ; "(3 terms, 4 symbols) gflt_data.1.register00[7].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register00[7].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register00[6].D = gflt_data.1.register00[6]*/daout[1] + gflt_data.1.register00[6]*daout[0] + daout[1]*mdbout[6]*/daout[0] ; "(3 terms, 4 symbols) gflt_data.1.register00[6].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register00[6].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register00[5].D = gflt_data.1.register00[5]*/daout[1] + gflt_data.1.register00[5]*daout[0] + daout[1]*mdbout[5]*/daout[0] ; "(3 terms, 4 symbols) gflt_data.1.register00[5].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register00[5].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register00[4].D = gflt_data.1.register00[4]*/daout[1] + gflt_data.1.register00[4]*daout[0] + daout[1]*mdbout[4]*/daout[0] ; "(3 terms, 4 symbols) gflt_data.1.register00[4].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register00[4].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register00[3].D = gflt_data.1.register00[3]*/daout[1] + gflt_data.1.register00[3]*daout[0] + daout[1]*mdbout[3]*/daout[0] ; "(3 terms, 4 symbols) gflt_data.1.register00[3].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register00[3].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register00[2].D = gflt_data.1.register00[2]*/daout[1] + gflt_data.1.register00[2]*daout[0] + daout[1]*mdbout[2]*/daout[0] ; "(3 terms, 4 symbols) gflt_data.1.register00[2].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register00[2].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register00[1].D = gflt_data.1.register00[1]*/daout[1] + gflt_data.1.register00[1]*daout[0] + daout[1]*mdbout[1]*/daout[0] ; "(3 terms, 4 symbols) gflt_data.1.register00[1].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register00[1].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register00[0].D = gflt_data.1.register00[0]*/daout[1] + gflt_data.1.register00[0]*daout[0] + mdbout[0]*daout[1]*/daout[0] ; "(3 terms, 4 symbols) gflt_data.1.register00[0].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register00[0].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register02[15].D = 0 ; "(1 term, 0 symbols) gflt_data.1.register02[15].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register02[15].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register02[14].D = 0 ; "(1 term, 0 symbols) gflt_data.1.register02[14].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register02[14].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register02[13].D = a_acceptout ; "(1 term, 1 symbol) gflt_data.1.register02[13].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register02[13].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register02[12].D = a_abortout ; "(1 term, 1 symbol) gflt_data.1.register02[12].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register02[12].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register02[11].D = gflt_data.1.register02[11]*daout[1] + gflt_data.1.register02[11]*daout[0] + /daout[1]*mdbout[7]*/daout[0] ; "(3 terms, 4 symbols) gflt_data.1.register02[11].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register02[11].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register02[10].D = gflt_data.1.register02[10]*daout[1] + gflt_data.1.register02[10]*daout[0] + /daout[1]*mdbout[6]*/daout[0] ; "(3 terms, 4 symbols) gflt_data.1.register02[10].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register02[10].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register02[9].D = gflt_data.1.register02[9]*daout[1] + gflt_data.1.register02[9]*daout[0] + /daout[1]*mdbout[5]*/daout[0] ; "(3 terms, 4 symbols) gflt_data.1.register02[9].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register02[9].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register02[8].D = gflt_data.1.register02[8]*daout[1] + gflt_data.1.register02[8]*daout[0] + /daout[1]*mdbout[4]*/daout[0] ; "(3 terms, 4 symbols) gflt_data.1.register02[8].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register02[8].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register02[7].D = gflt_data.1.register02[7]*daout[1] + gflt_data.1.register02[7]*daout[0] + /daout[1]*mdbout[3]*/daout[0] ; "(3 terms, 4 symbols) gflt_data.1.register02[7].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register02[7].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register02[6].D = gflt_data.1.register02[6]*daout[1] + gflt_data.1.register02[6]*daout[0] + /daout[1]*mdbout[2]*/daout[0] ; "(3 terms, 4 symbols) gflt_data.1.register02[6].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register02[6].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register02[5].D = gflt_data.1.register02[5]*daout[1] + gflt_data.1.register02[5]*daout[0] + /daout[1]*mdbout[1]*/daout[0] ; "(3 terms, 4 symbols) gflt_data.1.register02[5].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register02[5].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register02[4].D = gflt_data.1.register02[4]*daout[1] + gflt_data.1.register02[4]*daout[0] + mdbout[0]*/daout[1]*/daout[0] ; "(3 terms, 4 symbols) gflt_data.1.register02[4].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register02[4].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register02[3].D = 0 ; "(1 term, 0 symbols) gflt_data.1.register02[3].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register02[3].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register02[2].D = 0 ; "(1 term, 0 symbols) gflt_data.1.register02[2].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register02[2].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register02[1].D = 0 ; "(1 term, 0 symbols) gflt_data.1.register02[1].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register02[1].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.register02[0].D = 0 ; "(1 term, 0 symbols) gflt_data.1.register02[0].CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.register02[0].RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.sync.1.q1.D = mdb[0] ; "(1 term, 1 symbol) gflt_data.1.sync.1.q1.CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.sync.1.q1.RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.sync.2.q1.D = mdb[1] ; "(1 term, 1 symbol) gflt_data.1.sync.2.q1.CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.sync.2.q1.RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.sync.3.q1.D = mdb[2] ; "(1 term, 1 symbol) gflt_data.1.sync.3.q1.CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.sync.3.q1.RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.sync.4.q1.D = mdb[3] ; "(1 term, 1 symbol) gflt_data.1.sync.4.q1.CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.sync.4.q1.RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.sync.5.q1.D = mdb[4] ; "(1 term, 1 symbol) gflt_data.1.sync.5.q1.CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.sync.5.q1.RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.sync.6.q1.D = mdb[5] ; "(1 term, 1 symbol) gflt_data.1.sync.6.q1.CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.sync.6.q1.RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.sync.7.q1.D = mdb[6] ; "(1 term, 1 symbol) gflt_data.1.sync.7.q1.CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.sync.7.q1.RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.sync.8.q1.D = mdb[7] ; "(1 term, 1 symbol) gflt_data.1.sync.8.q1.CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.sync.8.q1.RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.sync.9.q1.D = da[0] ; "(1 term, 1 symbol) gflt_data.1.sync.9.q1.CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.sync.9.q1.RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.sync.10.q1.D = da[1] ; "(1 term, 1 symbol) gflt_data.1.sync.10.q1.CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.sync.10.q1.RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.sync.11.q1.D = a_abort ; "(1 term, 1 symbol) gflt_data.1.sync.11.q1.CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.sync.11.q1.RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.sync.12.q1.D = a_accept ; "(1 term, 1 symbol) gflt_data.1.sync.12.q1.CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.sync.12.q1.RESET = noa_rst ; "(1 term, 1 symbol) gflt_data.1.sync.13.q1.D = a_reset ; "(1 term, 1 symbol) gflt_data.1.sync.13.q1.CLK = sclk_4 ; "(1 term, 1 symbol) gflt_data.1.sync.13.q1.RESET = noa_rst ; "(1 term, 1 symbol) state_and_com_regs.1.register06[13].D = bwrite*db[13]*reg06 + /bwrite* state_and_com_regs.1.register06[13] + /reg06* state_and_com_regs.1.register06[13] ; "(3 terms, 4 symbols) state_and_com_regs.1.register06[13].CLK = /leb2 ; "(1 term, 1 symbol) state_and_com_regs.1.register06[13].RESET = noa_rst ; "(1 term, 1 symbol) state_and_com_regs.1.register06[12].D = bwrite*db[12]*reg06 + /bwrite* state_and_com_regs.1.register06[12] + /reg06* state_and_com_regs.1.register06[12] ; "(3 terms, 4 symbols) state_and_com_regs.1.register06[12].CLK = /leb2 ; "(1 term, 1 symbol) state_and_com_regs.1.register06[12].RESET = noa_rst ; "(1 term, 1 symbol) state_and_com_regs.1.register06[11].D = bwrite*db[11]*reg06 + /bwrite* state_and_com_regs.1.register06[11] + /reg06* state_and_com_regs.1.register06[11] ; "(3 terms, 4 symbols) state_and_com_regs.1.register06[11].CLK = /leb2 ; "(1 term, 1 symbol) state_and_com_regs.1.register06[11].RESET = noa_rst ; "(1 term, 1 symbol) state_and_com_regs.1.register06[10].D = bwrite*db[10]*reg06 + /bwrite* state_and_com_regs.1.register06[10] + /reg06* state_and_com_regs.1.register06[10] ; "(3 terms, 4 symbols) state_and_com_regs.1.register06[10].CLK = /leb2 ; "(1 term, 1 symbol) state_and_com_regs.1.register06[10].RESET = noa_rst ; "(1 term, 1 symbol) state_and_com_regs.1.register06[9].D = bwrite*db[9]*reg06 + /bwrite* state_and_com_regs.1.register06[9] + /reg06* state_and_com_regs.1.register06[9] ; "(3 terms, 4 symbols) state_and_com_regs.1.register06[9].CLK = /leb2 ; "(1 term, 1 symbol) state_and_com_regs.1.register06[9].RESET = noa_rst ; "(1 term, 1 symbol) state_and_com_regs.1.register06[8].D = bwrite*db[8]*reg06 + /bwrite* state_and_com_regs.1.register06[8] + /reg06* state_and_com_regs.1.register06[8] ; "(3 terms, 4 symbols) state_and_com_regs.1.register06[8].CLK = /leb2 ; "(1 term, 1 symbol) state_and_com_regs.1.register06[8].RESET = noa_rst ; "(1 term, 1 symbol) state_and_com_regs.1.register06[7].D = bwrite*db[7]*reg06 + /bwrite* state_and_com_regs.1.register06[7] + /reg06* state_and_com_regs.1.register06[7] ; "(3 terms, 4 symbols) state_and_com_regs.1.register06[7].CLK = /leb2 ; "(1 term, 1 symbol) state_and_com_regs.1.register06[7].RESET = noa_rst ; "(1 term, 1 symbol) state_and_com_regs.1.register06[5].D = bwrite*db[5]*reg06 + /bwrite* state_and_com_regs.1.register06[5] + /reg06* state_and_com_regs.1.register06[5] ; "(3 terms, 4 symbols) state_and_com_regs.1.register06[5].CLK = /leb2 ; "(1 term, 1 symbol) state_and_com_regs.1.register06[5].RESET = noa_rst ; "(1 term, 1 symbol) state_and_com_regs.1.register06[2].D = bwrite*db[2]*reg06 + /bwrite* state_and_com_regs.1.register06[2] + /reg06* state_and_com_regs.1.register06[2] ; "(3 terms, 4 symbols) state_and_com_regs.1.register06[2].CLK = /leb2 ; "(1 term, 1 symbol) state_and_com_regs.1.register06[2].RESET = noa_rst ; "(1 term, 1 symbol) state_and_com_regs.1.register06[0].D = bwrite*db[0]*reg06 + /bwrite* state_and_com_regs.1.register06[0] + /reg06* state_and_com_regs.1.register06[0] ; "(3 terms, 4 symbols) state_and_com_regs.1.register06[0].CLK = /leb2 ; "(1 term, 1 symbol) state_and_com_regs.1.register06[0].RESET = noa_rst ; "(1 term, 1 symbol) adc_signals.1.q1.CLK = sclk_4 ; "(1 term, 1 symbol) adc_signals.1.q1.RESET = noa_rst ; "(1 term, 1 symbol) adc_signals.1.q1.D(~) = /abusy*/testbusy*/vbusy ; "(1 term, 3 symbols) adc_signals.1.q3.CLK = sclk_4 ; "(1 term, 1 symbol) adc_signals.1.q3.RESET = noa_rst ; "(1 term, 1 symbol) adc_signals.1.q3.D(~) = /af_error*/vf_error ; "(1 term, 2 symbols) adc_signals.1.q5.CLK = sclk_4 ; "(1 term, 1 symbol) adc_signals.1.q5.RESET = noa_rst ; "(1 term, 1 symbol) adc_signals.1.q5.D(~) = /aerror*/verror ; "(1 term, 2 symbols) reset_and_test.1.q1_reset.EQN = /noa_rst* /reset_and_test.1.level_to_pulse.1.pulse*entestbusy ; "(1 term, 3 symbols) reset_and_test.1.q2.D = 1 ; "(1 term, 0 symbols) reset_and_test.1.q2.CLK = reset_and_test.1.q2_clk ; "(1 term, 1 symbol) reset_and_test.1.q2.RESET = /reset_and_test.1.q_reset ; "(1 term, 1 symbol) reset_and_test.1.q3.D = reset_and_test.1.q2 ; "(1 term, 1 symbol) reset_and_test.1.q3.CLK = sclk_4 ; "(1 term, 1 symbol) reset_and_test.1.q3.RESET = /reset_and_test.1.q_reset ; "(1 term, 1 symbol) reset_and_test.1.q2_clk.EQN(~) = /s_rst*/vsoa_reset ; "(1 term, 2 symbols) reset_and_test.1.q_reset.EQN = /noa_rst*/oa_reset ; "(1 term, 2 symbols) reset_and_test.1.level_to_pulse.1.pulse.D = 1 ; "(1 term, 0 symbols) reset_and_test.1.level_to_pulse.1.pulse.CLK = clrtestbusy ; "(1 term, 1 symbol) reset_and_test.1.level_to_pulse.1.pulse.RESET = reset_and_test.1.level_to_pulse.1.clr ; "(1 term, 1 symbol) reset_and_test.1.level_to_pulse.1.clr.EQN(~) = /noa_rst* /reset_and_test.1.level_to_pulse.1.pulse ; "(1 term, 2 symbols) last_abort.1.q1.D = a_acceptout ; "(1 term, 1 symbol) last_abort.1.q1.CLK = a_abortout ; "(1 term, 1 symbol) last_abort.1.q1.RESET = /last_abort.1.q_reset ; "(1 term, 1 symbol) last_abort.1.q3.D = last_abort.1.q1 ; "(1 term, 1 symbol) last_abort.1.q3.CLK = a_acceptout ; "(1 term, 1 symbol) last_abort.1.q3.RESET = /last_abort.1.q_reset ; "(1 term, 1 symbol) last_abort.1.q_reset.EQN = /last_abort.1.q3*/noa_rst ; "(1 term, 2 symbols) PLDocument: Y:\clock\zeus\slave\pld2\pld2.doc SOLUTIONS Fri Feb 25 17:03:27 2000 PARTITIONING CRITERIA : WEIGHT PRICE 10 ; TEMPLATE = MV512_184 ; PARTITIONING SOLUTIONS : ==> Solution 1: MV512_184 FUSEMAP FILES FOR SOLUTION 1: Device 1 (MV512_184) : Y:\clock\zeus\slave\pld2\pld2.j1 PLDocument: Y:\clock\zeus\slave\pld2\pld2.doc PINOUT DIAGRAMS Fri Feb 25 17:03:27 2000 Device 1 - MV512_184 -- Pinout for QFP package +-------+------+----------------------+ +-------+------+----------------------+ | Pin | Type | Signal | | Pin | Type | Signal | +-------+------+----------------------+ +-------+------+----------------------+ | 1 |Jtag | | | 51 |Vcc | | | 2 |Biput | mdb[0] | | 52 |Biput | a_abort | | 3 |Biput | mdb[1] | | 53 |Biput | a_accept | | 4 |Biput | mdb[2] | | 54 |Biput | a_reset | | 5 |Biput | mdb[3] | | 55 |Biput | a_abortout | | 6 |Biput | mdb[4] | | 56 |Biput | a_acceptout | | 7 |Biput | mdb[5] | | 57 |Biput | a_resetout | | 8 |Biput | mdb[6] | | 58 |Biput | | | 9 |Biput | mdb[7] | | 59 |Biput | | | 10 |Vcc | | | 60 |Jtag | | | 11 |GND | | | 61 |GND | | | 12 |Biput | | | 62 |Vcc | | | 13 |Biput | | | 63 |Biput | | | 14 |Biput | | | 64 |Biput | | | 15 |Biput | | | 65 |Biput | | | 16 |Biput | | | 66 |Biput | | | 17 |Biput | | | 67 |Biput | | | 18 |Biput | | | 68 |Biput | | | 19 |Biput | | | 69 |Biput | | | 20 |GND | | | 70 |Biput | | | 21 |Biput | mdbout[0] | | 71 |GND | | | 22 |Biput | mdbout[1] | | 72 |Vcc | | | 23 |Biput | mdbout[2] | | 73 |Biput | bplane_abort | | 24 |Biput | mdbout[3] | | 74 |Biput | bplane_accept | | 25 |Biput | mdbout[4] | | 75 |Biput | bplane_busy | | 26 |Biput | mdbout[5] | | 76 |Biput | bplane_empty | | 27 |Biput | mdbout[6] | | 77 |Biput | bplane_error | | 28 |Biput | mdbout[7] | | 78 |Biput | bplane_f_error | | 29 |In/CLK| | | 79 |Biput | bplane_reset | | 30 |Vcc | | | 80 |Biput | a_clkon | | 31 |GND | | | 81 |GND | | | 32 |In/CLK| sclk_4 | | 82 |Biput | | | 33 |Biput | | | 83 |Biput | | | 34 |Biput | | | 84 |Biput | | | 35 |Biput | | | 85 |Biput | | | 36 |Biput | | | 86 |Biput | | | 37 |Biput | | | 87 |Biput | | | 38 |Biput | | | 88 |Vcc | | | 39 |Biput | | | 89 |GND | | | 40 |Biput | | | 90 |GND | | | 41 |GND | | | 91 |GND | | | 42 |Biput | da[0] | | 92 |GND | | | 43 |Biput | da[1] | | 93 |Vcc | | | 44 |Biput | daout[0] | | 94 |Biput | vsoa_reset | | 45 |Biput | daout[1] | | 95 |Biput | vbusy | | 46 |Biput | | | 96 |Biput | vf_error | | 47 |Biput | | | 97 |Biput | verror | | 48 |Biput | | | 98 |Biput | entestbusy | | 49 |Biput | | | 99 |Biput | clrtestbusy | | 50 |GND | | | 100 |GND | | +-------+------+----------------------+ +-------+------+----------------------+ Device 1 - MV512_184 -- Pinout for QFP package (continued) +-------+------+----------------------+ +-------+------+----------------------+ | Pin | Type | Signal | | Pin | Type | Signal | +-------+------+----------------------+ +-------+------+----------------------+ | 101 |Biput | | | 151 |GND | | | 102 |Biput | | | 152 |In/CLK| leb2 | | 103 |Biput | | | 153 |Biput | | | 104 |Biput | | | 154 |Biput | | | 105 |Biput | | | 155 |Biput | | | 106 |Biput | | | 156 |Biput | | | 107 |Biput | | | 157 |Biput | | | 108 |Biput | | | 158 |Biput | | | 109 |Vcc | | | 159 |Biput | | | 110 |GND | | | 160 |Biput | | | 111 |Biput | abusy | | 161 |GND | | | 112 |Biput | aerror | | 162 |Biput | | | 113 |Biput | af_error | | 163 |Biput | db[15] | | 114 |Biput | | | 164 |Biput | | | 115 |Biput | busy | | 165 |Biput | db[14] | | 116 |Biput | f_error | | 166 |Biput | | | 117 |Biput | error | | 167 |Biput | db[13] | | 118 |Biput | nerror | | 168 |Biput | | | 119 |Vcc | | | 169 |Biput | db[12] | | 120 |GND | | | 170 |GND | | | 121 |Jtag | | | 171 |Vcc | | | 122 |Biput | | | 172 |Biput | | | 123 |Biput | | | 173 |Biput | db[11] | | 124 |Biput | | | 174 |Biput | | | 125 |Biput | | | 175 |Biput | db[10] | | 126 |Biput | | | 176 |Biput | | | 127 |Biput | | | 177 |Biput | db[9] | | 128 |Biput | | | 178 |Biput | | | 129 |Biput | | | 179 |Biput | db[8] | | 130 |Vcc | | | 180 |Jtag | | | 131 |GND | | | 181 |GND | | | 132 |Biput | reg00 | | 182 |Vcc | | | 133 |Biput | reg02 | | 183 |Biput | | | 134 |Biput | reg04 | | 184 |Biput | db[7] | | 135 |Biput | reg06 | | 185 |Biput | | | 136 |Biput | reg08 | | 186 |Biput | db[6] | | 137 |Biput | | | 187 |Biput | | | 138 |Biput | | | 188 |Biput | db[5] | | 139 |Biput | | | 189 |Biput | | | 140 |GND | | | 190 |Biput | db[4] | | 141 |Biput | s12[0] | | 191 |GND | | | 142 |Biput | s12[1] | | 192 |Vcc | | | 143 |Biput | s12[2] | | 193 |Biput | | | 144 |Biput | s12[3] | | 194 |Biput | db[3] | | 145 |Biput | | | 195 |Biput | | | 146 |Biput | | | 196 |Biput | db[2] | | 147 |Biput | | | 197 |Biput | | | 148 |Biput | | | 198 |Biput | db[1] | | 149 |In/CLK| | | 199 |Biput | | | 150 |Vcc | | | 200 |Biput | db[0] | +-------+------+----------------------+ +-------+------+----------------------+ Device 1 - MV512_184 -- Pinout for QFP package (continued) +-------+------+----------------------+ +-------+------+----------------------+ | Pin | Type | Signal | | Pin | Type | Signal | +-------+------+----------------------+ +-------+------+----------------------+ | 201 |GND | | | 221 |Biput | | | 202 |Biput | | | 222 |Biput | | | 203 |Biput | | | 223 |Biput | | | 204 |Biput | | | 224 |Biput | | | 205 |Biput | | | 225 |Biput | | | 206 |Biput | bwrite | | 226 |Biput | | | 207 |Biput | bread | | 227 |Biput | | | 208 |Vcc | | | 228 |Biput | | | 209 |GND | | | 229 |Vcc | | | 210 |GND | | | 230 |GND | | | 211 |GND | | | 231 |Biput | s_rst | | 212 |GND | | | 232 |Biput | noa_rst | | 213 |Vcc | | | 233 |Biput | | | 214 |Biput | | | 234 |Biput | | | 215 |Biput | | | 235 |Biput | | | 216 |Biput | | | 236 |Biput | noa_reset | | 217 |Biput | | | 237 |Biput | oa_reset | | 218 |Biput | | | 238 |Biput | testbusy | | 219 |Biput | | | 239 |Vcc | | | 220 |GND | | | 240 |GND | | +-------+------+----------------------+ +-------+------+----------------------+ DEVICE SELECTION: Device Manuf Fam Pack Temp Price User1 User2 1) M5-512/184-10HC AMD CMOS QFP COM $ 0.00 0 0 2) M5-512/184-10HI AMD CMOS QFP EXT $ 0.00 0 0 3) M5-512/184-12HC AMD CMOS QFP COM $ 0.00 0 0 4) M5-512/184-12HI AMD CMOS QFP EXT $ 0.00 0 0 5) M5-512/184-15HC AMD CMOS QFP COM $ 0.00 0 0 6) M5-512/184-15HI AMD CMOS QFP EXT $ 0.00 0 0 7) M5-512/184-20HI AMD CMOS QFP EXT $ 0.00 0 0 ==> M5-512/184-7HC AMD CMOS QFP COM $ 0.00 0 0 9) M5LV-512/184-10HC AMD V3.3 QFP COM $ 0.00 0 0 10) M5LV-512/184-10HI AMD V3.3 QFP EXT $ 0.00 0 0 11) M5LV-512/184-12HC AMD V3.3 QFP COM $ 0.00 0 0 12) M5LV-512/184-12HI AMD V3.3 QFP EXT $ 0.00 0 0 13) M5LV-512/184-15HC AMD V3.3 QFP COM $ 0.00 0 0 14) M5LV-512/184-15HI AMD V3.3 QFP EXT $ 0.00 0 0 15) M5LV-512/184-20HI AMD V3.3 QFP EXT $ 0.00 0 0 16) M5LV-512/184-7HC AMD V3.3 QFP COM $ 0.00 0 0 17) M5LV-512/184-7HI AMD V3.3 QFP EXT $ 0.00 0 0 PLDocument: Y:\clock\zeus\slave\pld2\pld2.doc WIRELIST Fri Feb 25 17:03:27 2000 +------------------+-------------------+-------+ | Signal | Device | Pin | +------------------+-------------------+-------+ | reg00 | MV512_184_1 | 132 | | reg02 | MV512_184_1 | 133 | | reg04 | MV512_184_1 | 134 | | reg06 | MV512_184_1 | 135 | | reg08 | MV512_184_1 | 136 | | bread | MV512_184_1 | 207 | | bwrite | MV512_184_1 | 206 | | leb2 | MV512_184_1 | 152 | | noa_rst | MV512_184_1 | 232 | | sclk_4 | MV512_184_1 | 32 | | mdb[7] | MV512_184_1 | 9 | | mdb[6] | MV512_184_1 | 8 | | mdb[5] | MV512_184_1 | 7 | | mdb[4] | MV512_184_1 | 6 | | mdb[3] | MV512_184_1 | 5 | | mdb[2] | MV512_184_1 | 4 | | mdb[1] | MV512_184_1 | 3 | | mdb[0] | MV512_184_1 | 2 | | da[1] | MV512_184_1 | 43 | | da[0] | MV512_184_1 | 42 | | a_abort | MV512_184_1 | 52 | | a_accept | MV512_184_1 | 53 | | a_reset | MV512_184_1 | 54 | | bplane_accept | MV512_184_1 | 74 | | bplane_abort | MV512_184_1 | 73 | | bplane_reset | MV512_184_1 | 79 | | bplane_error | MV512_184_1 | 77 | | bplane_f_error | MV512_184_1 | 78 | | bplane_busy | MV512_184_1 | 75 | | bplane_empty | MV512_184_1 | 76 | | a_clkon | MV512_184_1 | 80 | | abusy | MV512_184_1 | 111 | | af_error | MV512_184_1 | 113 | | aerror | MV512_184_1 | 112 | | s_rst | MV512_184_1 | 231 | | db[15] | MV512_184_1 | 163 | | db[14] | MV512_184_1 | 165 | | db[13] | MV512_184_1 | 167 | | db[12] | MV512_184_1 | 169 | | db[11] | MV512_184_1 | 173 | | db[10] | MV512_184_1 | 175 | | db[9] | MV512_184_1 | 177 | | db[8] | MV512_184_1 | 179 | | db[7] | MV512_184_1 | 184 | | db[6] | MV512_184_1 | 186 | | db[5] | MV512_184_1 | 188 | | db[4] | MV512_184_1 | 190 | | db[3] | MV512_184_1 | 194 | | db[2] | MV512_184_1 | 196 | | db[1] | MV512_184_1 | 198 | | db[0] | MV512_184_1 | 200 | +------------------+-------------------+-------+ +------------------+-------------------+-------+ | Signal | Device | Pin | +------------------+-------------------+-------+ | s12[3] | MV512_184_1 | 144 | | s12[2] | MV512_184_1 | 143 | | s12[1] | MV512_184_1 | 142 | | s12[0] | MV512_184_1 | 141 | | mdbout[7] | MV512_184_1 | 28 | | mdbout[6] | MV512_184_1 | 27 | | mdbout[5] | MV512_184_1 | 26 | | mdbout[4] | MV512_184_1 | 25 | | mdbout[3] | MV512_184_1 | 24 | | mdbout[2] | MV512_184_1 | 23 | | mdbout[1] | MV512_184_1 | 22 | | mdbout[0] | MV512_184_1 | 21 | | daout[1] | MV512_184_1 | 45 | | daout[0] | MV512_184_1 | 44 | | a_abortout | MV512_184_1 | 55 | | a_acceptout | MV512_184_1 | 56 | | a_resetout | MV512_184_1 | 57 | | vsoa_reset | MV512_184_1 | 94 | | vbusy | MV512_184_1 | 95 | | vf_error | MV512_184_1 | 96 | | verror | MV512_184_1 | 97 | | entestbusy | MV512_184_1 | 98 | | clrtestbusy | MV512_184_1 | 99 | | busy | MV512_184_1 | 115 | | f_error | MV512_184_1 | 116 | | error | MV512_184_1 | 117 | | nerror | MV512_184_1 | 118 | | testbusy | MV512_184_1 | 238 | | oa_reset | MV512_184_1 | 237 | | noa_reset | MV512_184_1 | 236 | +------------------+-------------------+-------+